Page 1 www.DataSheet4U.com Preliminary User’s Manual www.DataSheet4U.com 78K0S/KA1+ 8-Bit Single-Chip Microcontrollers µ PD78F9221 µ PD78F9222 Document No. U16898EJ1V0UD00 (1st edition) Date Published November 2003 N CP(K) © 2003 Printed in Japan...
Page 2 www.DataSheet4U.com [MEMO] www.DataSheet4U.com Preliminary User’s Manual U16898EJ1V0UD...
Page 3 www.DataSheet4U.com NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 www.DataSheet4U.com INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of the 78K0S/KA1+ in order to design and develop its application systems and programs. The target devices are the following subseries products. µ •...
Page 7 www.DataSheet4U.com Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: ××× (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ...
Page 8 Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E www.DataSheet4U.com Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...
Page 9: Table Of Contents
www.DataSheet4U.com CONTENTS CHAPTER 1 OVERVIEW......................... 14 Features ............................14 Application Fields ........................14 Ordering Information ......................... 15 Pin Configuration (Top View) ....................15 78K0S/Kx1+ Product Lineup..................... 16 Block Diagram..........................17 Functional Outline ........................18 www.DataSheet4U.com CHAPTER 2 PIN FUNCTIONS....................... 19 Pin Function List........................
Page 10 www.DataSheet4U.com 3.4.2 Short direct addressing........................40 3.4.3 Special function register (SFR) addressing .................41 3.4.4 Register addressing........................42 3.4.5 Register indirect addressing ......................43 3.4.6 Based addressing........................44 3.4.7 Stack addressing .........................44 CHAPTER 4 PORT FUNCTIONS ......................45 Functions of Ports ........................45 Port Configuration ........................46 4.2.1 Port 2............................47 www.DataSheet4U.com 4.2.2...
Page 11 www.DataSheet4U.com 6.4.6 One-shot pulse output operation ....................109 Cautions Related to 16-Bit Timer/Event Counter 00 ............114 CHAPTER 7 8-BIT TIMER 80......................118 Function of 8-Bit Timer 80.......................118 Configuration of 8-Bit Timer 80 ....................119 Register Controlling 8-Bit Timer 80 ..................121 Operation of 8-Bit Timer 80.....................122 7.4.1 Operation as interval timer ......................
Page 12 www.DataSheet4U.com 11.1 Functions of Serial Interface UART6..................173 11.2 Configuration of Serial Interface UART6 ................177 11.3 Registers Controlling Serial Interface UART6 ..............180 11.4 Operation of Serial Interface UART6..................189 11.4.1 Operation stop mode .........................189 11.4.2 Asynchronous serial interface (UART) mode................190 11.4.3 Dedicated baud rate generator ....................206 CHAPTER 12 INTERRUPT FUNCTIONS ....................213 12.1 Interrupt Function Types......................213 12.2 Interrupt Sources and Configuration ..................214...
Page 13 www.DataSheet4U.com 18.1 Features ............................260 18.2 Memory Configuration......................261 18.3 Functional Outline ........................262 18.4 Writing with Flash Programmer ..................... 264 18.5 Programming Environment.....................266 18.6 Communication Mode ......................266 18.7 Processing of Pins on Board....................267 18.7.1 X1 and X2 pins .......................... 267 18.7.2 RESET pin ..........................267 18.7.3 Port pins ............................
Page 14: Chapter 1 Overview
www.DataSheet4U.com CHAPTER 1 OVERVIEW 1.1 Features µ µ O Minimum instruction execution time selectable from high speed (0.2 s) and low speed (3.2 s) (with CPU clock of 10 MHz) O General-purpose registers: 8 bits × 8 registers O ROM and RAM capacities Item Program Memory (Flash Memory) Memory (Internal High-Speed RAM)
Page 15: Ordering Information
CHAPTER 1 OVERVIEW www.DataSheet4U.com 1.3 Ordering Information Part Number Package Internal ROM µ PD78F9221MC-5A4 20-pin plastic SSOP (7.62 mm (300)) Flash memory µ PD78F9222MC-5A4 20-pin plastic SSOP (7.62 mm (300)) Flash memory 1.4 Pin Configuration (Top View) 20-pin plastic SSOP (7.62 mm (300)) µ...
Page 16: 78K0S/Kx1+ Product Lineup
CHAPTER 1 OVERVIEW www.DataSheet4U.com 1.5 78K0S/Kx1+ Product Lineup The following table shows the product lineup of the 78K0S/Kx1+. Part Number 78K0S/KU1+ 78K0S/KY1+ 78K0S/KA1+ 78K0S/KB1+ Item Number of pins 8 pins 16 pins 20 pins 30 pins Internal Flash memory 1 KB, 2 KB, 4 KB 1 KB, 2 KB, 4 KB 2 KB 4 KB...
Page 17: Block Diagram
CHAPTER 1 OVERVIEW www.DataSheet4U.com 1.6 Block Diagram TO00/TI010/P31 Port 2 P20 to P23 16-bit timer event counter 00 TI000/P30 P30, P31 Port 3 8-bit timer 80 Port 4 P40 to P45 TOH1/P42 8-bit timer H1 78K0S Flash Port 12 P121 to P123 www.DataSheet4U.com Low-speed memory...
Page 18: Functional Outline
CHAPTER 1 OVERVIEW www.DataSheet4U.com 1.7 Functional Outline µ µ Item PD78F9221 PD78F9222 Internal Flash memory 2 KB 4 KB memory High-speed RAM 128 bytes 256 bytes Memory space 64 KB X1 input clock (oscillation frequency) Crystal/ceramic/external clock input: 10 MHz (V = 4.0 to 5.5 V), 6 MHz (V = 3.0 to 5.5 V), 5 MHz (V = 2.7 to 5.5 V),...
Page 19: Chapter 2 Pin Functions
www.DataSheet4U.com CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List (1) Port pins Pin Name Function After Reset Alternate- Function Pin P20 to P23 Port 2. Input ANI0 to ANI3 4-bit I/O port. Can be set to input or output mode in 1-bit units. An on-chip pull-up resistor can be connected by setting software.
Page 20 CHAPTER 2 PIN FUNCTIONS www.DataSheet4U.com (2) Non-port pins Pin Name Function After Reset Alternate- Function Pin INTP0 Input External interrupt input for which the valid edge (rising edge, Input P30/TI000 falling edge, or both rising and falling edges) can be specified INTP1 P43/TxD6 INTP2...
Page 21: Pin Functions
CHAPTER 2 PIN FUNCTIONS www.DataSheet4U.com 2.2 Pin Functions 2.2.1 P20 to P23 (Port 2) P20 to P23 constitute a 4-bit I/O port, port 2. In addition to I/O port pins, these pins also have a function to input analog signals to the A/D converter. These pins can be set to the following operation modes in 1-bit units. (1) Port mode P20 to P23 function as a 4-bit I/O port.
Page 22: P40 To P45 (Port 4)
CHAPTER 2 PIN FUNCTIONS www.DataSheet4U.com 2.2.3 P40 to P45 (Port 4) P40 to P45 constitute a 6-bit I/O port, port 4. In addition to I/O port pins, these pins also have functions to output a timer signal, input external interrupt request signals, and input/output the data of the serial interface. These pins can be set to the following operation modes in 1-bit units.
Page 23: Vdd
CHAPTER 2 PIN FUNCTIONS www.DataSheet4U.com 2.2.9 V This is the positive power supply pin. 2.2.10 V This is the ground pin. 2.3 Pin I/O Circuits and Connection of Unused Pins Table 2-1 shows I/O circuit type of each pin and the connections of unused pins. For the configuration of the I/O circuit of each type, refer to Figure 2-1.
Page 24 CHAPTER 2 PIN FUNCTIONS www.DataSheet4U.com Figure 2-1. Pin I/O Circuits Type 2 Type 11 Pull up P-ch enable Data P-ch IN/OUT Output N-ch disable Schmitt-triggered input with hysteresis characteristics Comparator P-ch www.DataSheet4U.com N-ch (Threshold voltage) Input enable Type 3-C Type 16-B Feedback cut-off P-ch...
Page 25: Chapter 3 Cpu Architecture
www.DataSheet4U.com CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The 78K0S/KA1+ can access up to 64 KB of memory space. Figures 3-1 and 3-2 show the memory maps. µ Figure 3-1. Memory Map ( PD78F9221) F F F F H Special function registers (SFR) 256 ×...
Page 26 CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com µ Figure 3-2. Memory Map ( PD78F9222) F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H F E F F H Internal high-speed RAM 256 × 8 bits F E 0 0 H F D F F H www.DataSheet4U.com...
Page 27: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The 78K0S/KA1+ provides the following internal ROMs (or flash memory) containing the following capacities. Table 3-1.
Page 28: Special Function Register (Sfr) Area
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see Table 3-3). 3.1.4 Data memory addressing The 78K0S/KA1+ is provided with a wide range of addressing modes to make memory manipulation as efficient as possible.
Page 29 CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com µ Figure 3-4. Data Memory Addressing ( PD78F9222) F F F F H Special function registers (SFR) SFR addressing 256 × 8 bits F F 2 0 H F E 1 F H F F 0 0 H F E F F H Short direct addressing Internal high-speed RAM...
Page 30: Processor Registers
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.2 Processor Registers The 78K0S/KA1+ provides the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 31 CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com (d) Carry flag (CY) This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area.
Page 32: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
Page 33: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.2.3 Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions.
Page 34 CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com Table 3-3. Special Function Registers (1/2) Address Special Function Register (SFR) Name Symbol Number of Bits Manipulated After Reset Simultaneously 1 Bit 8 Bits 16 Bits √ √ − FF02H Port register 2 Note 1 √...
Page 35 CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com Table 3-3. Special Function Registers (2/2) Address Special Function Register (SFR) Name Symbol Number of Bits Manipulated After Reset Simultaneously 1 Bit 8 Bits 16 Bits √ √ − FF80H A/D converter mode register √ √...
Page 36: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 37: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces. [Illustration] In case of CALL !addr16 and BR !addr16 instructions CALL or BR...
Page 38: Register Addressing
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed. [Illustration] www.DataSheet4U.com Preliminary User’s Manual U16898EJ1V0UD...
Page 39: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.4 Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] www.DataSheet4U.com Identifier...
Page 40: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal high- speed RAM is mapped at FE20H to FEFFH and the special function registers (SFR) are mapped at FF00H to FF1FH.
Page 41: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.4.3 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to FF1FH are accessed with short direct addressing.
Page 42: Register Addressing
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.4.4 Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
Page 43: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces.
Page 44: Based Addressing
CHAPTER 3 CPU ARCHITECTURE www.DataSheet4U.com 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored.
Page 45: Chapter 4 Port Functions
www.DataSheet4U.com CHAPTER 4 PORT FUNCTIONS Functions of Ports The 78K0S/KA1+ has the ports shown in Figure 4-1, which can be used for various control operations. Table 4-1 shows the functions of each port. In addition to digital I/O port functions, each of these ports has an alternate function. For details, refer to CHAPTER 2 PIN FUNCTIONS.
Page 46: Port Configuration
CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com Table 4-1. Port Functions Pin Name Function After Reset Alternate- Function Pin P20 to P23 Port 2. Input ANI0 to ANI3 4-bit I/O port. Can be set to input or output mode in 1-bit units. On-chip pull-up resistor can be connected by setting software.
Page 47: Port 2
CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com 4.2.1 Port 2 Port 2 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 2 (PU2).
Page 48: Www.datasheet4U.com 4.2.2 Port 3
CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com 4.2.2 Port 3 Pins P30 and P31 constitute a 2-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 3 (PM3). When the P30 to P31 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (PU3).
Page 49: Port 4
CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com Figure 4-4. Block Diagram of P34 P34/RESET Reset Option byte www.DataSheet4U.com Read signal 4.2.3 Port 4 Port 4 is a 6-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4).
Page 50 CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com Figure 4-5. Block Diagram of P40 and P45 PU40, PU45 P-ch www.DataSheet4U.com PORT Output latch P40, P45 (P40, P45) PM40, PM45 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal Preliminary User’s Manual U16898EJ1V0UD...
Page 51 CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com Figure 4-6. Block Diagram of P41 and P44 PU41, PU44 P-ch Alternate function www.DataSheet4U.com PORT Output latch P41/INTP3, (P41, P44) P44/RxD6 PM41, PM44 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal Preliminary User’s Manual U16898EJ1V0UD...
Page 52 CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com Figure 4-7. Block Diagram of P42 PU42 P-ch www.DataSheet4U.com PORT Output latch P42/TOH1 (P42) PM42 Alternate function PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal Preliminary User’s Manual U16898EJ1V0UD...
Page 53 CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com Figure 4-8. Block Diagram of P43 PU43 P-ch Alternate function www.DataSheet4U.com PORT Output latch P43/Tx6/INTP1 (P43) PM43 Alternate function PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal Preliminary User’s Manual U16898EJ1V0UD...
Page 54: Port 12
CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com 4.2.4 Port 12 Port 12 is a 3-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 12 (PM12). When the P123 pin is used as an input port, an on-chip pull-up resistor can be connected by using pull-up resistor option register 12 (PU12).
Page 55 CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com Figure 4-10. Block Diagram of P123 PU12 PU123 P-ch www.DataSheet4U.com PORT Output latch P123 (P123) PM12 PM123 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 Read signal WR××: Write signal Preliminary User’s Manual U16898EJ1V0UD...
Page 56: Registers Controlling Port Functions
CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com 4.2.5 Port 13 This is a 1-bit output-only port. Figure 4-11 shows the block diagram of port 13. Figure 4-11. Block Diagram of P130 www.DataSheet4U.com PORT Output latch P130 (P130) Read signal WR××: Write signal Remark When a reset is input, P130 outputs a low level.
Page 57 CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com Figure 4-12. Format of Port Mode Register Address: FF22H, After reset: FFH, R/W Symbol PM23 PM22 PM21 PM20 Address: FF23H, After reset: FFH, R/W Symbol PM31 PM30 Address: FF24H, After reset: FFH, R/W www.DataSheet4U.com Symbol PM45 PM44 PM43...
Page 58 CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com Figure 4-13. Format of Port Register Address: FF02H, After reset: 00H (Output latch) R/W Symbol Note Note Address: FF03H, After reset: 00H (Output latch) R/W Symbol Address: FF04H, After reset: 00H (Output latch) R/W www.DataSheet4U.com Symbol Address: FF0CH, After reset: 00H (Output latch) R/W Symbol...
Page 59 CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com Figure 4-14. Format of Port Mode Control Register 2 Address: FF84H, After reset: R/W Symbol PMC2 PMC23 PMC22 PMC21 PMC20 PMC2n Specification of operation mode (n = 0 to 3) Port mode Alternate-function mode (A/D converter) Table 4-3.
Page 60 CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com (4) Pull-up resistor option registers (PU2, PU3, PU4, PU12) These registers are used to specify whether an on-chip pull-up resistor is connected to P20 to P23, P30, P31, P40 to P45, and P123. By setting PU2, PU3, PU4, or PU12, an on-chip pull-up resistor can be connected to the port pin corresponding to the bit of PU2, PU3, PU4, or PU12.
Page 61: Operation Of Port Function
CHAPTER 4 PORT FUNCTIONS www.DataSheet4U.com Operation of Port Function The operation of a port differs, as follows, depending on the setting of the I/O mode. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units.
Page 62: Chapter 5 Clock Generators
www.DataSheet4U.com CHAPTER 5 CLOCK GENERATORS Functions of Clock Generators The clock generators include a circuit that generates a clock (system clock) to be supplied to the CPU and peripheral hardware, and a circuit that generates a clock (interval time generation clock) to be supplied to the watchdog timer and 8-bit timer H1 (TMH1).
Page 63: Configuration Of Clock Generators
CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com Configuration of Clock Generators The clock generators consist of the following hardware. Table 5-1. Configuration of Clock Generators Item Configuration Control registers Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed Ring-OSC mode register (LSRCM) High-speed Ring-OSC mode register (HSRCM) Oscillation stabilization time select register (OSTS) Oscillators...
Page 64 CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com Figure 5-1. Block Diagram of Clock Generators Internal bus Oscillation stabilization Preprocessor clock Processor clock time select register (OSTS) control register (PPCC) control register (PCC) OSTS1 OSTS0 PPCC1 PPCC0 PCC1 System clock oscillation Controller stabilization time counter CPU clock STOP System clock...
Page 65: Registers Controlling Clock Generators
CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com Registers Controlling Clock Generators The clock generators are controlled by the following five registers. • Processor clock control register (PCC) • Preprocessor clock control register (PPCC) • Low-speed Ring-OSC mode register (LSRCM) • High-speed Ring-OSC mode register (HSRCM) •...
Page 66 CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com The fastest instruction of the 78K0S/KA1+ is executed in two CPU clocks. Therefore, the relationship between the CPU clock (f ) and the minimum instruction execution time is as shown in Table 5-2. Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time Note CPU Clock (f Minimum Instruction Execution Time: 2/f...
Page 67 CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com If crystal/ceramic oscillation or external clock input is selected as the system clock source, the high-speed Ring- OSC oscillator must be oscillated during self-programming of the flash memory. While self-programming is not executed, stop oscillation of the high-speed Ring-OSC oscillator to reduce the current consumption. For self- programming of the flash memory, refer to CHAPTER 18 FLASH MEMORY.
Page 68: System Clock Oscillators
CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com STOP mode is released Voltage waveform of X1 pin Caution 3. The oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. Remarks 1.
Page 69: Crystal/Ceramic Oscillator
CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com 5.4.2 Crystal/ceramic oscillator The crystal/ceramic oscillator oscillates using a crystal or ceramic resonator connected between the X1 and X2 pins. If the crystal/ceramic oscillator is selected by the option byte as the system clock source, the X1 and X2 pins are used as crystal or ceramic resonator connection pins.
Page 70 CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com Figure 5-8 shows examples of incorrect resonator connection. Figure 5-8. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (b) Crossed signal lines PORT www.DataSheet4U.com (d) Current flowing through ground line of oscillator (c) Wiring near high fluctuating current (Potential at points A, B, and C fluctuates.) PORT...
Page 71: External Clock Input Circuit
CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com Figure 5-8. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched www.DataSheet4U.com 5.4.3 External clock input circuit This circuit supplies a clock from an external IC to the X1 pin. If external clock input is selected by the option byte as the system clock source, the X2 pin can be used as an I/O port pin.
Page 72: Operation Of Cpu Clock Generator
CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com Operation of CPU Clock Generator A clock (f ) is supplied to the CPU from the system clock (f ) oscillated by one of the following three types of oscillators. • High-speed Ring-OSC oscillator: Internally oscillates a clock of 8 MHz (TYP.). •...
Page 73 CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com (a) The internal reset signal is generated by the power-on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system clock is selected. Then the high-speed Ring-OSC clock operates as the system clock.
Page 74 CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com Figure 5-12. Timing Chart of Default Start by Crystal/Ceramic Oscillator RESET Internal reset System clock Crystal/ceramic CPU clock oscillator clock PCC = 02H, PPCC = 02H www.DataSheet4U.com Option byte is read. Clock oscillation System clock is selected. stabilization (Operation stops: 8/f + 96/f...
Page 75 CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com Figure 5-13. Status Transition of Default Start by Crystal/Ceramic Oscillation Power application > 2.1 V ±0.1 V Reset by power-on clear Reset signal Crystal/ceramic oscillation selected www.DataSheet4U.com by option byte Start with PCC = 02H, PPCC = 02H Wait for clock oscillation stabilization...
Page 76 CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com Figure 5-14. Timing of Default Start by External Clock Input RESET Internal reset System clock External clock input CPU clock PCC = 02H, PPCC = 02H www.DataSheet4U.com Option byte is read. System clock is selected. (Operation stops: 8/f + 96/f Remark f...
Page 77: Operation Of Clock Generator Supplying Clock To Peripheral Hardware
CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com Operation of Clock Generator Supplying Clock to Peripheral Hardware The following two types of clocks are supplied to the peripheral hardware. • Clock to peripheral hardware (f • Low-speed Ring-OSC clock (f (1) Clock to peripheral hardware The clock to the peripheral hardware is supplied by dividing the system clock (f ).
Page 78 CHAPTER 5 CLOCK GENERATORS www.DataSheet4U.com Figure 5-16. Status Transition of Low-Speed Ring-OSC Oscillator Power application > 2.1 V ±0.1 V Reset by power-on clear Reset signal Select by option byte if low-speed Ring-OSC www.DataSheet4U.com can be stopped or not Can be stopped Cannot be stopped Clock source of Clock source of...
Page 79: Chapter 6 16-Bit Timer/Event Counter 00
www.DataSheet4U.com CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates interrupt requests at the preset time interval. • Number of counts: 2 to 65536 (2) External event counter www.DataSheet4U.com 16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of a signal input...
Page 80: Configuration Of 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 consists of the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Configuration Timer counter 16-bit timer counter 00 (TM00) Register 16-bit timer capture/compare registers 000, 010 (CR000, CR010) Timer input TI000, TI010...
Page 81 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read.
Page 82 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins (1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1) CR000 Capture Trigger TI000 Pin Valid Edge ES010 ES000 Falling edge...
Page 83 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com (3) 16-bit capture/compare register 010 (CR010) CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00).
Page 84: Registers To Control 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Registers to Control 16-Bit Timer/Event Counter 00 The following six types of registers are used to control 16-bit timer/event counter 00. • 16-bit timer mode control register 00 (TMC00) • Capture/compare control register 00 (CRC00) •...
Page 85 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FF60H After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 TMC001 Operating mode and clear TO00 inversion timing selection Interrupt request generation mode selection Operation stop...
Page 86 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit capture/compare registers (CR000, CR010). CRC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets the value of CRC00 to 00H. Figure 6-6.
Page 87 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot pulse output operation enable/disable, and output trigger of one-shot pulse by software.
Page 88 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and the TI000, TI010 pin input valid edges. PRM00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets the value of PRM00 to 00H.
Page 89 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO00/TI010/INTP2 pin for timer output, set PM31 and the output latch of P31 to 0. When using the P30/TI000/INTP0 and P31/TO00/TI010/INTP2 pins as a timer input, set PM30 and PM31 to 1.
Page 90: Operation Of 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-10 allows operation as an interval timer. Setting The basic operation setting procedure is as follows.
Page 91 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-10. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000...
Page 92 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-11. Interval Timer Configuration Diagram 16-bit timer capture/compare register 000 (CR000) INTTM000 Note 16-bit timer counter 00 OVF00 (TM00) Noise TI000/INTP0/P30 eliminator Clear circuit www.DataSheet4U.com Note OVF00 is set to 1 only when 16-bit timer capture/compare register 000 is set to FFFFH. Figure 6-12.
Page 93: External Event Counter Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com 6.4.2 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-14 for the set value). <2> Set the count clock by using the PRM00 register. <3>...
Page 94 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-14. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001...
Page 95 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-15. External Event Counter Configuration Diagram Internal bus 16-bit timer capture/compare register 000 (CR000) Match INTTM000 Clear Note Noise eliminator 16-bit timer counter 00 (TM00) OVF00 www.DataSheet4U.com Valid edge of TI000 Note OVF00 is 1 only when 16-bit timer capture/compare register 000 is set to FFFFH. Figure 6-16.
Page 96: Pulse Width Measurement Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
Page 97 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set.
Page 98 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-19. Configuration Diagram for Pulse Width Measurement by Free-Running Counter 16-bit timer/counter 00 OVF00 (TM00) 16-bit timer capture/compare TI000/INTP0/P30 register 010 (CR010) INTTM010 www.DataSheet4U.com Internal bus Figure 6-20. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock TM00 count value...
Page 99 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin. When the edge specified by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set.
Page 100 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-22. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count clock 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 D2 + 2 TM00 count value TI000 pin input CR010 capture value...
Page 101 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI000 pin. When the rising or falling edge specified by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set.
Page 102 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-24. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM00 count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 TI000 pin input...
Page 103 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-25. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts at valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001...
Page 104: Square-Wave Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com 6.4.4 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-27 for the set value). <3>...
Page 105 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-27. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 TOC00 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting “11”...
Page 106: Ppg Output Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com 6.4.5 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-29 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1>...
Page 107 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-29. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000...
Page 108 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-30. Configuration Diagram of PPG Output 16-bit timer capture/compare register 000 (CR000) Clear 16-bit timer counter 00 circuit (TM00) Noise TI000/INTP0/P30 eliminator TO00/TI010/ www.DataSheet4U.com INTP2/P31 16-bit timer capture/compare register 010 (CR010) Figure 6-31. PPG Output Operation Timing Count clock M −...
Page 109: One-Shot Pulse Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is as follows. <1>...
Page 110 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-32. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Free-running mode (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 www.DataSheet4U.com CRC00...
Page 111 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-33. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 0CH (TM00 count starts) Count clock − − TM00 count 0000H 0001H N + 1 0000H M + 1 M + 2 CR010 set value CR000 set value OSPT00...
Page 112 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-34. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts at valid edge of TI000 pin.
Page 113 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Figure 6-35. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) Count clock − − TM00 count value 0000H 0001H 0000H N + 1 N + 2 M + 1 M + 2...
Page 114: Cautions Related To 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com Cautions Related to 16-Bit Timer/Event Counter 00 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.
Page 115 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com (6) Operation of OVF00 flag <1> The OVF00 flag is also set to 1 in the following case. Either of the clear & start mode entered on a match between TM00 and CR000, clear & start at the valid edge of the TI000 pin, or free-running mode is selected.
Page 116 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com (8) Timer operation <1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010). <2> Regardless of the CPU’s operation mode, when the timer stops, the signals input to pins TI000/TI010 are not acknowledged.
Page 117 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 www.DataSheet4U.com <Changing duty (CR010)> 1. Disable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 0). 2. Disable the INTTM000 interrupt (TMMK000 = 1). 3. Rewrite CR010. 4. Wait for 1 cycle of the TM00 count clock. 5.
Page 118: Chapter 7 8-Bit Timer 80
www.DataSheet4U.com CHAPTER 7 8-BIT TIMER 80 Function of 8-Bit Timer 80 8-bit timer 80 has an 8-bit interval timer function and generates an interrupt at intervals specified in advance. Table 7-1. Interval Time of 8-Bit Timer 80 Minimum Interval Time Maximum Interval Time Resolution µ...
Page 119: Configuration Of 8-Bit Timer 80
CHAPTER 7 8-BIT TIMER 80 www.DataSheet4U.com Configuration of 8-Bit Timer 80 8-bit timer 80 consists of the following hardware. Table 7-2. Configuration of 8-Bit Timer 80 Item Configuration Timer counter 8-bit timer counter 80 (TM80) Register 8-bit compare register 80 (CR80) Control register 8-bit timer mode control register 80 (TMC80) www.DataSheet4U.com...
Page 120 CHAPTER 7 8-BIT TIMER 80 www.DataSheet4U.com (1) 8-bit compare register 80 (CR80) This 8-bit register always compares its set value with the count value of 8-bit timer/counter 80 (TM80). It generates an interrupt request signal (INTTM80) if the two values match. CR80 is set by using an 8-bit memory manipulation instruction.
Page 121: Register Controlling 8-Bit Timer 80
CHAPTER 7 8-BIT TIMER 80 www.DataSheet4U.com Register Controlling 8-Bit Timer 80 8-bit timer 80 is controlled by 8-bit timer mode control register 80 (TMC80). (1) 8-bit timer mode control register 80 (TMC80) This register is used to enable or stop the operation of 8-bit timer/counter 80 (TM80), and to set the count clock of TM80.
Page 122: Operation Of 8-Bit Timer 80
CHAPTER 7 8-BIT TIMER 80 www.DataSheet4U.com Operation of 8-Bit Timer 80 7.4.1 Operation as interval timer When 8-bit timer 80 operates as an interval timer, it can repeatedly generate an interrupt at intervals specified by the count value set in advance to 8-bit compare register 80 (CR80). To use 8-bit timer 80 as an interval timer, make the following setting.
Page 123 CHAPTER 7 8-BIT TIMER 80 www.DataSheet4U.com Figure 7-5. Timing of Interval Timer Operation Count clock TM80 count value Clear Clear CR80 www.DataSheet4U.com TCE80 Count start INTTM80 Interrupt acknowledged Interrupt acknowledged TO80 Interval time Interval time Interval time Remark Interval time = (N + 1) × t: N = 00H to FFH Preliminary User’s Manual U16898EJ1V0UD...
Page 124: Notes On 8-Bit Timer 80
CHAPTER 7 8-BIT TIMER 80 www.DataSheet4U.com Notes on 8-Bit Timer 80 (1) Error when timer starts The time from starting the timer to generation of the match signal includes an error of up to 1.5 clocks. This is because, if the timer is started while the count clock is high, the rising edge may be immediately detected and the counter may be incremented (refer to Figure 7-6).
Page 125: Chapter 8 8-Bit Timer H1
www.DataSheet4U.com CHAPTER 8 8-BIT TIMER H1 Functions of 8-Bit Timer H1 8-bit timer H1 has the following functions. • Interval timer • PWM output mode • Square-wave output Configuration of 8-Bit Timer H1 www.DataSheet4U.com 8-bit timer H1 consists of the following hardware. Table 8-1.
Page 126 Figure 8-1. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode register 1 (TMHMD1) 8-bit timer H 8-bit timer H TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 compare register compare register 11 (CMP11) 01 (CMP01) Decoder TOH1/P42 Selector Output latch...
Page 127 CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com (1) 8-bit timer H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 8-2. Format of 8-Bit Timer H Compare Register 01 (CMP01) Address: FF0EH After reset: 00H Symbol...
Page 128: Registers Controlling 8-Bit Timer H1
CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com Registers Controlling 8-Bit Timer H1 The following three registers are used to control 8-Bit Timer H1. • 8-bit timer H mode register 1 (TMHMD1) • Port mode register 4 (PM4) • Port register 4 (P4) (1) 8-bit timer H mode register 1 (TMHMD1) This register controls the mode of timer H.
Page 129 CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com Figure 8-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF70H After reset: 00H <7> <1> <0> Symbol TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable Stop timer count operation (counter is cleared to 0) Enable timer count operation (count operation started by inputting clock) CKS12 CKS11...
Page 130 CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com (2) Port mode register 4 (PM4) This register sets port 4 input/output in 1-bit units. When using the P42/TOH1 pin for timer output, clear PM42 and the output latch of P42 to 0. PM4 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to FFH.
Page 131: Operation Of 8-Bit Timer H1
CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com Operation of 8-Bit Timer H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is generated and 8-bit timer counter H1 is cleared to 00H. Compare register 11 (CMP11) is not used in interval timer mode.
Page 132 CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 01H 00H 8-bit timer counter H1 Clear Clear www.DataSheet4U.com...
Page 133 CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP01 = FFH Count clock Count start 8-bit timer counter H1 Clear Clear CMP01 www.DataSheet4U.com TMHE1 INTTMH1 TOH1 Interval time (c) Operation when CMP01 = 00H Count clock Count start 8-bit timer counter H1...
Page 134: Operation As Pwm Output Mode
CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com 8.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during timer operation is prohibited.
Page 135 CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com <4> When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register.
Page 136 CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are within the following range. 00H ≤...
Page 137 CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com Figure 8-9. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP01 www.DataSheet4U.com...
Page 138 CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com Figure 8-9. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter H1 CMP01 www.DataSheet4U.com CMP11 TMHE1 INTTMH1...
Page 139 CHAPTER 8 8-BIT TIMER H1 www.DataSheet4U.com Figure 8-9. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 01H → 03H, CMP01 = A5H) Count clock 8-bit timer counter H1 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP01...
Page 140: Chapter 9 Watchdog Timer
www.DataSheet4U.com CHAPTER 9 WATCHDOG TIMER Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 14 RESET FUNCTION.
Page 141 CHAPTER 9 WATCHDOG TIMER www.DataSheet4U.com Table 9-2. Option Byte Setting and Watchdog Timer Operation Mode Option Byte Setting Low-Speed Ring-OSC Cannot Be Stopped Low-Speed Ring-OSC Can Be Stopped by Software • Selectable by software (f Note 1 Watchdog timer clock Fixed to f or stopped) •...
Page 142: Configuration Of Watchdog Timer
CHAPTER 9 WATCHDOG TIMER www.DataSheet4U.com Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 9-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 9-1. Block Diagram of Watchdog Timer www.DataSheet4U.com Clock Output...
Page 143: Registers Controlling Watchdog Timer
CHAPTER 9 WATCHDOG TIMER www.DataSheet4U.com Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. • Watchdog timer mode register (WDTM) • Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released.
Page 144 CHAPTER 9 WATCHDOG TIMER www.DataSheet4U.com Cautions 1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “low-speed Ring-OSC cannot be stopped” is selected by the option byte, other values are ignored). 2. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction.
Page 145: Operation Of Watchdog Timer
CHAPTER 9 WATCHDOG TIMER www.DataSheet4U.com Operation of Watchdog Timer 9.4.1 Watchdog timer operation when “low-speed Ring-OSC cannot be stopped” is selected by option byte The operation clock of watchdog timer is fixed to low-speed Ring-OSC. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
Page 146 CHAPTER 9 WATCHDOG TIMER www.DataSheet4U.com Figure 9-4. Status Transition Diagram When “Low-Speed Ring-OSC Cannot Be Stopped” Is Selected by Option Byte Reset WDT clock: f Overflow time: 1.09 s (TYP.) WDTE = “ACH” Clear WDT counter. WDT clock is fixed to f Select overflow time (settable only once).
Page 147: Watchdog Timer Operation When "Low-Speed Ring-Osc Can Be Stopped By Software" Is Selected By Option Byte
CHAPTER 9 WATCHDOG TIMER www.DataSheet4U.com 9.4.2 Watchdog timer operation when “low-speed Ring-OSC can be stopped by software” is selected by option byte The operation clock of the watchdog timer can be selected as either the low-speed Ring-OSC clock or the clock to peripheral hardware.
Page 148 CHAPTER 9 WATCHDOG TIMER www.DataSheet4U.com Figure 9-5. Status Transition Diagram When “Low-Speed Ring-OSC Can Be Stopped by Software” Is Selected by Option Byte Reset WDT clock: f Overflow time: 1.09 s (TYP.) WDCS4 = 1 WDT clock = f Select overflow time (settable only once).
Page 149: Watchdog Timer Operation In Stop Mode (When "Low-Speed Ring-Osc Can Be Stopped By Software" Is Selected By Option Byte)
CHAPTER 9 WATCHDOG TIMER www.DataSheet4U.com 9.4.3 Watchdog timer operation in STOP mode (when “low-speed Ring-OSC can be stopped by software” is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the clock to peripheral hardware or low-speed Ring-OSC clock is being used.
Page 150 CHAPTER 9 WATCHDOG TIMER www.DataSheet4U.com (2) When the watchdog timer operation clock is the low-speed Ring-OSC clock (f ) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, operation stops for 8 clocks of the low-speed Ring-OSC clock and then counting is started again using the operation clock before the operation was stopped.
Page 151: Watchdog Timer Operation In Halt Mode (When "Low-Speed Ring-Osc Can Be Stopped By Software" Is Selected By Option Byte)
CHAPTER 9 WATCHDOG TIMER www.DataSheet4U.com 9.4.4 Watchdog timer operation in HALT mode (when “low-speed Ring-OSC can be stopped by software” is selected by option byte) The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of the watchdog timer is the clock to peripheral hardware (f ) or low-speed Ring-OSC clock (f ).
Page 152: Chapter 10 A/D Converter
www.DataSheet4U.com CHAPTER 10 A/D CONVERTER 10.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to ANI3) with a resolution of 10 bits. The A/D converter has the following function. •...
Page 153 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com Table 10-1. Sampling Time and A/D Conversion Time Sampling Conversion = 8 MHz = 10 MHz Note 1 Note 2 Time Time Sampling Conversion Sampling Conversion Note 1 Note 2 Note 1 Note 2 Time Time Time Time...
Page 154 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com Figure 10-2 shows the block diagram of A/D converter. Figure 10-2. Block Diagram of A/D Converter ADCS bit ANI0/P20 Sample & hold circuit ANI1/P21 Voltage comparator ANI2/P22 ANI3/P23 Successive approximation www.DataSheet4U.com register (SAR) Controller INTAD A/D conversion result register (ADCR, ADCRH) ADS1...
Page 155: Configuration Of A/D Converter
CHAPTER 10 A/D CONVERTER www.DataSheet4U.com 10.2 Configuration of A/D Converter The A/D converter consists of the following hardware. Table 10-2. Registers of A/D Converter Used on Software Item Configuration Registers Successive approximation register (SAR) 10-bit A/D conversion result register (ADCR) 8-bit A/D conversion result register (ADCRH) A/D converter mode register (ADM) Analog input channel specification register (ADS)
Page 156 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com (6) 10-bit A/D conversion result register (ADCR) The result of A/D conversion is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCR register holds the result of A/D conversion in its lower 10 bits (the higher 6 bits are fixed to 0).
Page 157: Registers Used By A/D Converter
CHAPTER 10 A/D CONVERTER www.DataSheet4U.com 10.3 Registers Used by A/D Converter The A/D converter uses the following six registers. • A/D converter mode register (ADM) • Analog input channel specification register (ADS) • 10-bit A/D conversion result register (ADCR) • 8-bit A/D conversion result register (ADCRH) •...
Page 158 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 10-4.
Page 159 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com Table 10-3. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (only reference voltage generator consumes power) Note Conversion mode (reference voltage generator operation stopped Conversion mode (reference voltage generator operates) Note Data of first conversion cannot be used.
Page 160 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 10-6.
Page 161 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com (4) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit resolution result. ADCRH can be read by an 8-bit memory manipulation instruction. Reset input makes ADCRH undefined.
Page 162: A/D Converter Operations
CHAPTER 10 A/D CONVERTER www.DataSheet4U.com 10.4 A/D Converter Operations 10.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). µ <2> Set ADCE to 1 and wait for 1 s or longer.
Page 163 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com Figure 10-11. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result ADCR, Conversion www.DataSheet4U.com ADCRH result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 164: Input Voltage And Conversion Results
CHAPTER 10 A/D CONVERTER www.DataSheet4U.com 10.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
Page 165: A/D Converter Operation Mode
CHAPTER 10 A/D CONVERTER www.DataSheet4U.com 10.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed. (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register...
Page 166 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com The setting method is described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
Page 167: How To Read A/D Converter Characteristics Table
CHAPTER 10 A/D CONVERTER www.DataSheet4U.com 10.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 168 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
Page 169: Cautions For A/D Converter
CHAPTER 10 A/D CONVERTER www.DataSheet4U.com 10.6 Cautions for A/D Converter (1) Operating current in standby mode The A/D converter stops operating in the standby mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) of the A/D converter mode register (ADM) to 0 (see Figure 10-3). (2) Input range of ANI0 to ANI3 Observe the rated range of the ANI0 to ANI3 input voltage.
Page 170 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com (5) ANI0/P20 to ANI3/P23 <1> The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to P23). When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access port 2 while conversion is in progress;...
Page 171 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
Page 172 CHAPTER 10 A/D CONVERTER www.DataSheet4U.com (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 10-22. Internal Equivalent Circuit of ANIn Pin ANIn LSI internal www.DataSheet4U.com Table 10-4. Resistance and Capacitance Values of Equivalent Circuit 2.7 V T.B.D.
Page 173: Chapter 11 Serial Interface Uart6
www.DataSheet4U.com CHAPTER 11 SERIAL INTERFACE UART6 11.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 174 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master.
Page 175 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com Figure 11-2. LIN Reception Operation Wakeup Synchronous Synchronous Indent Data field Data field Checksum signal frame break field field field field Sleep Data Data Data Note 5 reception reception reception reception reception Note 2 13 bits reception Disable...
Page 176 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com Figure 11-3. Port Configuration for LIN Reception Operation Selector P44/R RXD6 input Port mode (PM44) Output latch (P44) www.DataSheet4U.com Selector Selector P30/INTP0/TI000 INTP0 input Port mode Port input (PM30) selection control (ISC0) Output latch <ISC0>...
Page 177: Configuration Of Serial Interface Uart6
CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com 11.2 Configuration of Serial Interface UART6 Serial interface UART6 consists of the following hardware. Table 11-1. Configuration of Serial Interface UART6 Item Configuration Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers...
Page 178 Figure 11-4. Block Diagram of Serial Interface UART6 Note TI000, INTP0 Filter INTSR6 Reception control INTSRE6 Receive shift register 6 (RXS6) Asynchronous serial Asynchronous serial Asynchronous serial interface Baud rate Receive buffer register 6 interface operation mode interface reception error control register 6 (ASICL6) generator (RXB6)
Page 179 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6).
Page 180: Registers Controlling Serial Interface Uart6
CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com 11.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) •...
Page 181 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) RXE6 Enabling/disabling reception Disable reception (synchronously reset the reception circuit). Enable reception PS61 PS60 Transmission operation Reception operation Parity bit not output. Reception without parity Note Output 0 parity.
Page 182 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. Reset input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0.
Page 183 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
Page 184 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset input clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 185 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset input sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 186 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 187 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length.
Page 188 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input signal is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 189: Operation Of Serial Interface Uart6
CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com 11.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 11.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.
Page 190: Asynchronous Serial Interface (Uart) Mode
CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com 11.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 191 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com The relationship between the register settings and pins is shown below. Table 11-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM43 PM44 UART6 Pin Function Operation TxD6/INTP1/P43 RxD6/P44 Note Note Note Note ×...
Page 192 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 11-13 and 11-14 show the format and waveform example of the normal transmit/receive data. Figure 11-13. Format of Normal UART Transmit/Receive Data 1.
Page 193 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com Figure 11-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame www.DataSheet4U.com Start...
Page 194 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 195 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (c) Normal transmission The T D6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6).
Page 196 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
Page 197 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com Figure 11-16 shows an example of the continuous transmission processing flow. Figure 11-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary www.DataSheet4U.com number of times? Read ASIF6 TXBF6 = 0? Write TXB6.
Page 198 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com Figure 11-17 shows the timing of starting continuous transmission, and Figure 11-18 shows the timing of ending continuous transmission. Figure 11-17. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start...
Page 199 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com Figure 11-18. Timing of Ending Continuous Transmission Data (n − 1) Start Start Data (n) Parity Parity Stop Stop Stop INTST6 Data (n − 1) TXB6 Data (n) Data (n − 1) TXS6 Data (n) TXBF6 www.DataSheet4U.com TXSF6...
Page 200 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (e) Normal reception Reception is enabled and the R D6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6 pin input is detected.
Page 201 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
Page 202 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (g) Noise filter of receive data The RXD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
Page 203 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (h) SBF transmission When the device is incorporated in LIN, the SBF (Synchronous Break Field) transmission control function is used for transmission. For the transmission operation of LIN, see Figure 11-1 LIN Transmission Operation. An SBF length that is a low-level width of 13 bits or more is set by bits 4 to 2 (SBL62 to SBL60) of asynchronous serial interface control register 6 (ASICL6).
Page 204 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com Figure 11-22. Example of Setting Procedure of SBF Transmission (Flowchart) Start Read BRGC6 register and save current set value of BRGC6 register to general- purpose register. Clear TXE6 and RXE6 bits of ASIM6 register to 0 (to disable transmission/ reception).
Page 205 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 11-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
Page 206: Dedicated Baud Rate Generator
CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com 11.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 207 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com Figure 11-25. Configuration of Baud Rate Generator POWER6 Baud rate generator POWER6, TXE6 (or RXE6) Selector 8-bit counter XCLK6 www.DataSheet4U.com Match detector Baud rate CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6 RXE6:...
Page 208 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.
Page 209 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (3) Example of setting baud rate Table 11-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.0 MHz = 4.19 MHz [bps] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS60...
Page 210 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 211 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2...
Page 212 CHAPTER 11 SERIAL INTERFACE UART6 www.DataSheet4U.com (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.
Page 213: Chapter 12 Interrupt Functions
www.DataSheet4U.com CHAPTER 12 INTERRUPT FUNCTIONS 12.1 Interrupt Function Types All interrupts are controlled as maskable interrupts. • Maskable interrupts These interrupts undergo mask control. If two or more interrupt requests are simultaneously generated, each interrupt has a predetermined priority as shown in Table 12-1. A standby release signal is generated.
Page 214: Interrupt Sources And Configuration
CHAPTER 12 INTERRUPT FUNCTIONS www.DataSheet4U.com 12.2 Interrupt Sources and Configuration There are a total of 14 interrupt sources, and up to four reset sources (see Table 12-1). Table 12-1. Interrupt Sources Note 1 Interrupt Type Priority Interrupt Source Internal/ Vector Table Basic External Address...
Page 215 CHAPTER 12 INTERRUPT FUNCTIONS www.DataSheet4U.com Figure 12-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus Vector table address generator Interrupt request www.DataSheet4U.com Standby release signal (B) External maskable interrupt Internal bus External interrupt mode register (INTM0, INTM1) Vector table address generator Edge...
Page 216: Interrupt Function Control Registers
CHAPTER 12 INTERRUPT FUNCTIONS www.DataSheet4U.com 12.3 Interrupt Function Control Registers The interrupt functions are controlled by the following four types of registers. • Interrupt request flag registers (IF0, IF1) • Interrupt mask flag registers (MK0, MK1) • External interrupt mode registers (INTM0, INTM1) •...
Page 217 CHAPTER 12 INTERRUPT FUNCTIONS www.DataSheet4U.com Interrupt request flag registers (IF0, IF1) An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the instruction is executed. It is cleared to 0 by executing an instruction when the interrupt request is acknowledged or when a reset signal is input.
Page 218 CHAPTER 12 INTERRUPT FUNCTIONS www.DataSheet4U.com Interrupt mask flag registers (MK0, MK1) The interrupt mask flag is used to enable and disable the corresponding maskable interrupts. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets MK0 and MK1 to FFH. Figure 12-3.
Page 219 CHAPTER 12 INTERRUPT FUNCTIONS www.DataSheet4U.com External interrupt mode register 0 (INTM0) This register is used to set the valid edge of INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. Reset input clears INTM0 to 00H. Figure 12-4. Format of External Interrupt Mode Register 0 (INTM0) Address: FFECH After reset: 00H Symbol...
Page 220 CHAPTER 12 INTERRUPT FUNCTIONS www.DataSheet4U.com External interrupt mode register 1 (INTM1) INTM1 is used to specify the valid edge for INTP3. INTM1 is set with an 8-bit memory manipulation instruction. Reset input clears INTM1 to 00H. Figure 12-5. Format of External Interrupt Mode Register 1 (INTM1) Address: FFEDH After reset: 00H Symbol...
Page 221: Interrupt Servicing Operation
CHAPTER 12 INTERRUPT FUNCTIONS www.DataSheet4U.com 12.4 Interrupt Servicing Operation 12.4.1 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status (when the IE flag is set to 1).
Page 222 CHAPTER 12 INTERRUPT FUNCTIONS www.DataSheet4U.com Figure 12-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (Interrupt request generated) ××MK = 0? www.DataSheet4U.com Interrupt request pending IE = 1? Interrupt request pending Vectored interrupt servicing ××IF: Interrupt request flag ××MK: Interrupt mask flag Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable)
Page 223 CHAPTER 12 INTERRUPT FUNCTIONS www.DataSheet4U.com Figure 12-9. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) 8 clocks Clock Interrupt Saving PSW and PC, jump servicing MOV A, r to interrupt servicing program Interrupt www.DataSheet4U.com If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgment processing...
Page 224: Multiple Interrupt Servicing
CHAPTER 12 INTERRUPT FUNCTIONS www.DataSheet4U.com 12.4.2 Multiple interrupt servicing Multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is being serviced can be performed using a priority order system. When two or more interrupts are generated at once, interrupt servicing is performed according to the priority assigned to each interrupt request in advance (see Table 12-1).
Page 225: Interrupt Request Pending
CHAPTER 12 INTERRUPT FUNCTIONS www.DataSheet4U.com 12.4.3 Interrupt request pending Some instructions may keep pending the acknowledgment of an instruction request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt and external interrupt) is generated during the execution.
Page 226: Chapter 13 Standby Function
www.DataSheet4U.com CHAPTER 13 STANDBY FUNCTION 13.1 Standby Function and Configuration 13.1.1 Standby function Table 13-1. Relationship Between Operation Clocks in Each Operation Status Status Low-Speed Ring-OSC Oscillator System Clock Clock Supplied to Peripheral Note 1 Note 2 Hardware Operation Mode LSRSTOP = 0 LSRSTOP = 1 www.DataSheet4U.com...
Page 227 CHAPTER 13 STANDBY FUNCTION www.DataSheet4U.com (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, select the HALT mode if processing must be immediately started by an interrupt request when the STOP mode is released because the operation stops for the duration of eight clocks of the low-speed Ring- OSC clock (because an additional wait time for stabilizing oscillation elapses when crystal/ceramic oscillation...
Page 228: Registers Used During Standby
CHAPTER 13 STANDBY FUNCTION www.DataSheet4U.com 13.1.2 Registers used during standby The oscillation stabilization time after the standby mode is released is controlled by the oscillation stabilization time select register (OSTS). Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATORS. (1) Oscillation stabilization time select register (OSTS) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released.
Page 229: Standby Function Operation
CHAPTER 13 STANDBY FUNCTION www.DataSheet4U.com 13.2 Standby Function Operation 13.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operating statuses in the HALT mode are shown below. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set.
Page 230 CHAPTER 13 STANDBY FUNCTION www.DataSheet4U.com (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out.
Page 231 CHAPTER 13 STANDBY FUNCTION www.DataSheet4U.com (b) Release by reset input When the reset signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 13-3.
Page 232: Stop Mode
CHAPTER 13 STANDBY FUNCTION www.DataSheet4U.com 13.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set.
Page 233 CHAPTER 13 STANDBY FUNCTION www.DataSheet4U.com (2) STOP mode release Figure 13-4. Operation Timing When STOP Mode Is Released <1> If high-speed Ring-OSC clock or external input clock is selected as system clock to be supplied STOP mode is released. STOP mode System clock oscillation www.DataSheet4U.com...
Page 234 CHAPTER 13 STANDBY FUNCTION www.DataSheet4U.com (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 13-5.
Page 235 CHAPTER 13 STANDBY FUNCTION www.DataSheet4U.com (b) Release by reset input When the reset signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 13-6. STOP Mode Release by Reset Input (1) If CPU clock is high-speed Ring-OSC clock or external input clock STOP instruction...
Page 236: Chapter 14 Reset Function
www.DataSheet4U.com CHAPTER 14 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
Page 237 CHAPTER 14 RESET FUNCTION www.DataSheet4U.com Figure 14-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF LVIRF Clear Reset signal of watchdog timer Clear www.DataSheet4U.com Reset signal RESET Reset signal to Reset signal of LVIM/LVIS register power-on-clear circuit Reset signal Reset signal of...
Page 238 CHAPTER 14 RESET FUNCTION www.DataSheet4U.com Figure 14-2. Timing of Reset by RESET Input <1> With high-speed Ring-OSC clock or external clock input High-speed Ring-OSC clock or external clock input Normal operation Reset period CPU clock Normal operation (reset processing, CPU clock) in progress (oscillation stops) RESET...
Page 239 CHAPTER 14 RESET FUNCTION www.DataSheet4U.com Figure 14-3. Timing of Reset by Overflow of Watchdog Timer <1> With high-speed Ring-OSC clock or external clock input High-speed Ring-OSC clock or external clock input Normal operation Reset period CPU clock Normal operation (reset processing, CPU clock) in progress (oscillation stops) Operation stops because option byte is referenced.
Page 240 CHAPTER 14 RESET FUNCTION www.DataSheet4U.com Figure 14-4. Reset Timing by RESET Input in STOP Mode <1> With high-speed Ring-OSC clock or external clock input STOP instruction is executed. High-speed Ring-OSC clock or external clock input Normal operation Stop status Reset period CPU clock Normal operation (reset processing, CPU clock) in progress...
Page 241 CHAPTER 14 RESET FUNCTION www.DataSheet4U.com Table 14-1. Hardware Statuses After Reset Acknowledgment (1/2) Hardware Status After Reset Note 1 Program counter (PC) Contents of reset vector table (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Undefined Data memory...
Page 242 CHAPTER 14 RESET FUNCTION www.DataSheet4U.com Table 14-1. Hardware Statuses After Reset Acknowledgment (2/2) Hardware Status After Reset Serial interface UART6 Receive buffer register 6 (RXB6) Transmit buffer register 6 (TXB6) Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission error status register 6 (ASIF6)
Page 243: Register For Confirming Reset Source
CHAPTER 14 RESET FUNCTION www.DataSheet4U.com 14.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0S/KA1+. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
Page 244: Chapter 15 Power-On-Clear Circuit
www.DataSheet4U.com CHAPTER 15 POWER-ON-CLEAR CIRCUIT 15.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. • Compares supply voltage (V = 2.1 V ±0.1 V), and generates internal reset signal ) and detection voltage (V when V <...
Page 245: Configuration Of Power-On-Clear Circuit
CHAPTER 15 POWER-ON-CLEAR CIRCUIT www.DataSheet4U.com 15.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 15-1. Figure 15-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − www.DataSheet4U.com Detection voltage source 15.3 Operation of Power-on-Clear Circuit = 2.1 V ±0.1 V) are compared, In the power-on-clear circuit, the supply voltage (V ) and detection voltage (V...
Page 246: Cautions For Power-On-Clear Circuit
CHAPTER 15 POWER-ON-CLEAR CIRCUIT www.DataSheet4U.com 15.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 247 CHAPTER 15 POWER-ON-CLEAR CIRCUIT www.DataSheet4U.com Figure 15-3. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset source WDTRF of RESF register = 1? www.DataSheet4U.com Reset processing by watchdog timer LVIRF of RESF register = 1? Reset processing by low-voltage detector Power-on clear/external...
Page 248: Chapter 16 Low-Voltage Detector
www.DataSheet4U.com CHAPTER 16 LOW-VOLTAGE DETECTOR 16.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. • Compares supply voltage (V ) and detection voltage (V ), and generates an internal interrupt signal or internal reset signal when V <...
Page 249: Registers Controlling Low-Voltage Detector
CHAPTER 16 LOW-VOLTAGE DETECTOR www.DataSheet4U.com 16.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detect register (LVIM) • Low-voltage detection level select register (LVIS) (1) Low-voltage detect register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 250 CHAPTER 16 LOW-VOLTAGE DETECTOR www.DataSheet4U.com (2) Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 16-3. Format of Low-Voltage Detection Level Select Register (LVIS) Address: FF51H, After reset: 00H R/W Symbol LVIS...
Page 251: Operation Of Low-Voltage Detector
CHAPTER 16 LOW-VOLTAGE DETECTOR www.DataSheet4U.com 16.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. • Used as reset Compares the supply voltage (V ) and detection voltage (V ), and generates an internal reset signal when <...
Page 252 CHAPTER 16 LOW-VOLTAGE DETECTOR www.DataSheet4U.com Figure 16-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (V LVI detection voltage POC detection voltage Time <2> LVIMK flag (set by software) <1> LVION flag Not cleared Not cleared (set by software) www.DataSheet4U.com <3>...
Page 253 CHAPTER 16 LOW-VOLTAGE DETECTOR www.DataSheet4U.com (2) When used as interrupt • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select register (LVIS).
Page 254: Cautions For Low-Voltage Detector
CHAPTER 16 LOW-VOLTAGE DETECTOR www.DataSheet4U.com 16.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. <1>...
Page 255 CHAPTER 16 LOW-VOLTAGE DETECTOR www.DataSheet4U.com Figure 16-6. Example of Software Processing After Release of Reset (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Check The reset source (power-on clear, WDT, or LVI) Note 2 reset source can be identified by the RESF register.
Page 256 CHAPTER 16 LOW-VOLTAGE DETECTOR www.DataSheet4U.com Figure 16-6. Example of Software Processing After Release of Reset (2/2) • Checking reset source Check reset source WDTRF of RESF register = 1? www.DataSheet4U.com Reset processing by watchdog timer LVIRF of RESF register = 1? Power-on-clear/external reset generated Reset processing by...
Page 257: Chapter 17 Option Byte
www.DataSheet4U.com CHAPTER 17 OPTION BYTE The 78K0S/KA1+ has an area called an option byte at address 0080H of the flash memory. When using the product, be sure to set the following functions by using the option byte. 1. Selection of system clock source •...
Page 258 CHAPTER 17 OPTION BYTE www.DataSheet4U.com Figure 17-2. Format of Option Byte (1/2) Address: FF80H DEFOSTS1 DEFOSTS0 RMCE OSCSEL1 OSCSEL0 RINGOSC RINGOSC Low-speed Ring-OSC clock oscillation Cannot be stopped Can be stopped by software Cautions 1. If it is selected that low-speed Ring-OSC clock oscillation cannot be stopped, the count clock to the watchdog timer (WDT) is fixed to low-speed Ring-OSC.
Page 259 CHAPTER 17 OPTION BYTE www.DataSheet4U.com Figure 17-2. Format of Option Byte (2/2) DEFOSTS1 DEFOSTS0 Oscillation stabilization time on power application or reset input µ /fx (102.4 µ /fx (409.6 /fx (3.27 ms) /fx (13.1 ms) Caution The setting of this option is valid only when the crystal/ceramic oscillation clock is selected as the system clock source.
Page 260: Chapter 18 Flash Memory
www.DataSheet4U.com CHAPTER 18 FLASH MEMORY Flash memory versions are commonly used in the following development environments and mass production applications. For altering software after the 78K0S/KA1+ is soldered onto the target system. For data adjustment when starting mass production. For differentiating software according to the specification in small scale production of various models. For facilitating inventory management.
Page 261: Memory Configuration
CHAPTER 18 FLASH MEMORY www.DataSheet4U.com 18.2 Memory Configuration The 4/2 KB internal flash memory area is divided into 16/8 blocks and can be programmed/erased in block units. All the blocks can also be erased at once. Figure 18-1. Flash Memory Mapping 0FFFH Block 15 (256 bytes) 0F00H...
Page 262: Functional Outline
CHAPTER 18 FLASH MEMORY www.DataSheet4U.com 18.3 Functional Outline The internal flash memory of the 78K0S/KA1+ can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the 78K0S/KA1+ has already been mounted on the target system or not (on- board/off-board programming).
Page 263 CHAPTER 18 FLASH MEMORY www.DataSheet4U.com Table 18-2. Basic Functions Support ( : Supported, ×: Not supported) Function Functional Outline On-Board/Off-Board Self Programming Programming Block erasure The contents of specified memory blocks are erased. × Chip erasure The contents of the entire memory area are erased all at once.
Page 264: Writing With Flash Programmer
CHAPTER 18 FLASH MEMORY www.DataSheet4U.com 18.4 Writing with Flash Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0S/KA1+ has been mounted on the target system. The connectors that connect the dedicated flash programmer must be mounted on the target system.
Page 265 CHAPTER 18 FLASH MEMORY www.DataSheet4U.com Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 18-2. Example of Wiring Adapter for Flash Memory Writing VDD (2.7 to 5.5 V) www.DataSheet4U.com VDD2 RFU3 RFU2 RFU1 FLMD1 FLMD0...
Page 266: Programming Environment
CHAPTER 18 FLASH MEMORY www.DataSheet4U.com 18.5 Programming Environment The environment required for writing a program to the flash memory is illustrated below. Figure 18-3. Environment for Writing Program to Flash Memory RS-232C Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 RESET Note DGCLK 78K0S/KA1+ Dedicated flash Note...
Page 267: Processing Of Pins On Board
CHAPTER 18 FLASH MEMORY www.DataSheet4U.com 18.7 Processing of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
Page 268: Programming Method
CHAPTER 18 FLASH MEMORY www.DataSheet4U.com 18.8 Programming Method 18.8.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 18-6. Flash Memory Manipulation Procedure Start Flash memory programming mode is set www.DataSheet4U.com Manipulate flash memory End? Preliminary User’s Manual U16898EJ1V0UD...
Page 269: Flash Memory Programming Mode
CHAPTER 18 FLASH MEMORY www.DataSheet4U.com 18.8.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the 78K0S/KA1+ in the flash memory programming mode. When the 78K0S/KA1+ is connected to the flash programmer and a communication command is transmitted to the microcontroller, the microcontroller is set in the flash memory programming mode.
Page 270: Flash Memory Programming By Self Writing
CHAPTER 18 FLASH MEMORY www.DataSheet4U.com 18.9 Flash Memory Programming by Self Writing The 78K0S/KA1+ supports a self programming function that can be used to rewrite the flash memory via a user program, making it possible to upgrade programs in the field. Cautions 1.
Page 271: Chapter 19 Instruction Set Overview
www.DataSheet4U.com CHAPTER 19 INSTRUCTION SET OVERVIEW This chapter lists the instruction set of the 78K0S/KA1+. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 19.1 Operation 19.1.1 Operand identifiers and description methods Operands are described in “Operand”...
Page 272: Description Of "Operation" Column
CHAPTER 19 INSTRUCTION SET OVERVIEW www.DataSheet4U.com 19.1.2 Description of “Operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair www.DataSheet4U.com DE register pair HL register pair Program counter Stack pointer...
Page 273: Operation List
CHAPTER 19 INSTRUCTION SET OVERVIEW www.DataSheet4U.com 19.2 Operation List Mnemonic Operand Bytes Clocks Operation Flag AC CY r ← byte r, #byte (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte A ← r Note 1 A, r r ← A Note 1 r, A A ←...
Page 274 CHAPTER 19 INSTRUCTION SET OVERVIEW www.DataSheet4U.com Mnemonic Operand Bytes Clocks Operation Flag AC CY rp ← word MOVW rp, #word AX ← (saddrp) AX, saddrp (saddrp) ← AX saddrp, AX AX ← rp Note AX, rp rp ← AX Note rp, AX AX ↔...
Page 275 CHAPTER 19 INSTRUCTION SET OVERVIEW www.DataSheet4U.com Mnemonic Operand Bytes Clocks Operation Flag AC CY A, CY ← A − byte − CY × × × SUBC A, #byte (saddr), CY ← (saddr) − byte − CY × × × saddr, #byte A, CY ←...
Page 276 CHAPTER 19 INSTRUCTION SET OVERVIEW www.DataSheet4U.com Mnemonic Operand Bytes Clocks Operation Flag AC CY A − byte × × × A, #byte (saddr) − byte × × × saddr, #byte A − r × × × A, r A − (saddr) ×...
Page 277 CHAPTER 19 INSTRUCTION SET OVERVIEW www.DataSheet4U.com Mnemonic Operand Bytes Clocks Operation Flag AC CY (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) CALL !addr16 PC ← addr16, SP ← SP − 2 (SP − 1) ← (PC + 1) , (SP −...
Page 278: Instructions Listed By Addressing Type
CHAPTER 19 INSTRUCTION SET OVERVIEW www.DataSheet4U.com 19.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte saddr !addr16 [DE] [HL] $addr16 None...
Page 279 CHAPTER 19 INSTRUCTION SET OVERVIEW www.DataSheet4U.com (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd Operand #word saddrp None 1st Operand ADDW SUBW MOVW MOVW MOVW CMPW XCHW Note MOVW MOVW INCW DECW PUSH saddrp MOVW www.DataSheet4U.com MOVW...
Page 280 CHAPTER 19 INSTRUCTION SET OVERVIEW www.DataSheet4U.com (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand !addr16 [addr5] $addr16 1st Operand Basic instructions CALL CALLT Compound instructions DBNZ www.DataSheet4U.com (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP Preliminary User’s Manual U16898EJ1V0UD...
Page 281: Chapter 20 Electrical Specifications (Target Values)
www.DataSheet4U.com CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) These specifications are only target values, and may not be satisfied by mass-produced products. Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +0.3 −0.3 to V Note + 0.3...
Page 282 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) www.DataSheet4U.com = −40 to +85°C, V X1 Oscillator Characteristics (T = 2.0 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit 4.0 V ≤ V ≤ 5.5 V Ceramic Oscillation 10.0 Note resonator frequency (f...
Page 283 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) www.DataSheet4U.com = −40 to +85°C, V High-Speed Ring-OSC Oscillator Characteristics (T = 2.0 to 5.5 V) Resonator Parameter Conditions MIN. TYP. MAX. Unit 2.7 V ≤ V ≤ 5.5 V On-chip high-speed Ring-OSC Oscillation frequency (f 7.60 8.00 8.40...
Page 284 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) www.DataSheet4U.com = −40 to +85°C, V DC Characteristics (T = 2.0 to 5.5 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2.0 V ≤ V ≤ 5.5 V Output current, high Pins other than Per pin –5 P20 to P23...
Page 285 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) www.DataSheet4U.com = −40 to +85°C, V DC Characteristics (T = 2.0 to 5.5 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Pull-up = 0 V kΩ resistance value Note 2 Supply Crystal/ceramic = 10 MHz When A/D converter is stopped 12.2 = 5.0 V ±10%...
Page 286 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) www.DataSheet4U.com AC Characteristics = −40 to +85°C, V (1) Basic operation (T = 2.0 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V ≤ V ≤ 5.5 V µ Cycle time (minimum Crystal/ceramic oscillation instruction execution time) clock, external clock input...
Page 287 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) www.DataSheet4U.com vs. V (Crystal/Ceramic Oscillation Clock, External Clock Input) Guaranteed www.DataSheet4U.com operation range 0.33 Supply voltage V vs. V (High-speed Ring-OSC Clock) Guaranteed operation range 0.25 Supply voltage V Preliminary User’s Manual U16898EJ1V0UD...
Page 288 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) www.DataSheet4U.com = −40 to +85°C, V (2) Serial interface (T = 2.0 to 5.5 V) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate 312.5 kbps AC Timing Test Points (Excluding X1 Input) 0.8V 0.8V...
Page 289 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) www.DataSheet4U.com = −40 to +85°C, 2.7 V ≤ AV ≤ V ≤ 5.5 V) A/D Converter Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 4.0 V ≤ AV ≤ 4.5 V ±0.2 ±0.4 Notes 1, 2 Overall error...
Page 290 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) www.DataSheet4U.com = −40 to +85°C) POC Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage µ : 0 V → 2.0 V Power supply rise time Note Response delay time 1 When power supply rises, after reaching PTHD detection voltage (MAX.)
Page 291 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) www.DataSheet4U.com = −40 to +85°C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage LVI0 LVI1 LVI2 LVI3 LVI4 3.15 3.45 LVI5 2.95 3.25 LVI6 2.85 LVI7 LVI8 www.DataSheet4U.com 2.25 2.35 2.45 LVI9...
Page 292 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) www.DataSheet4U.com = –10°C to +70°C, 2.7 V ≤ V ≤ 5.5 V, V Flash Memory Programming Characteristics (T = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 1 Erase time Chip unit T.B.D T.B.D eraca...
Page 293: Chapter 21 Package Drawing
www.DataSheet4U.com CHAPTER 21 PACKAGE DRAWING 20-PIN PLASTIC SSOP (7.62 mm (300)) detail of lead end www.DataSheet4U.com NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 6.65±0.15 its true position (T.P.) at maximum material condition. 0.475 MAX. 0.65 (T.P.) +0.08 0.24 −0.07...
Page 294: Appendix A Development Tools
www.DataSheet4U.com APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the 78K0S/KA1+. Figure A-1 shows development tools. • Compatibility with PC98-NX series Unless stated otherwise, products which are supported by IBM PC/AT and compatibles can also be used with the PC98-NX series.
Page 295 APPENDIX A DEVELOPMENT TOOLS www.DataSheet4U.com Figure A-1. Development Tools Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger • C compiler package • System simulator • Device file • C library source file Note 1 www.DataSheet4U.com Control software...
Page 296: Software Package
APPENDIX A DEVELOPMENT TOOLS www.DataSheet4U.com A.1 Software Package SP78K0S This is a package that bundles the software tools required for development of the 78K/0S Series. Software package The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S/Kx1 (provisional name), and device files µ...
Page 297: Control Software
APPENDIX A DEVELOPMENT TOOLS www.DataSheet4U.com ×××× in the part number differs depending on the host machine and operating system to be used. Remark µ S××××RA78K0S µ S××××CC78K0S ×××× Host Machine Supply Media AB13 PC-9800 series, IBM PC/AT Japanese Windows 3.5” 2HD FD and compatibles BB13 English Windows...
Page 298: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS www.DataSheet4U.com A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator for debugging hardware and software of application system using 78K/0S In-circuit emulator Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine. IE-78K0S-NS-A This in-circuit emulator has a coverage function in addition to the functions of the IE-78K0S- In-circuit emulator...
Page 299: Debugging Tools (Software)
APPENDIX A DEVELOPMENT TOOLS www.DataSheet4U.com A.6 Debugging Tools (Software) ID78K0S-NS This debugger supports the in-circuit emulators for the 78K/0S Series, IE-78K0S-NS and IE- Integrated debugger 78K0S-NS-A. ID78K0S-NS is Windows-based software. This debugger has enhanced debugging functions supporting C language. By using its window integration function that associates the source program, disassemble display, and memory display with trace results, the trace results can be displayed corresponding to the source program.
Page 300: Appendix B Notes On Target System Design
www.DataSheet4U.com APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following show the conditions when connecting the emulation probe to the conversion connector and conversion socket. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system.
Page 301: Appendix C Register Index
www.DataSheet4U.com APPENDIX C REGISTER INDEX C.1 Register Index (Register Name) 8-bit A/D conversion result register (ADCRH) … 161 8-bit compare register 80 (CR80) … 120 8-bit timer counter 80 (TM80) … 120 8-bit timer H compare register 01 (CMP01) … 127 8-bit timer H compare register 11 (CMP11) …...
Page 302 APPENDIX C REGISTER INDEX www.DataSheet4U.com Low voltage detect register (LVIM) … 249 Low voltage detection level select register (LVIS) … 250 Low-speed Ring-OSC mode register (LSRCM) … 66 Oscillation stabilization time selection register (OSTS) … 67 Port mode control register 2 (PMC2) … 58, 161 Port mode register 2 (PM2) …...
Page 303: Register Index (Symbol)
APPENDIX C REGISTER INDEX www.DataSheet4U.com C.2 Register Index (Symbol) ADCR: 10-bit A/D conversion result register … 160 ADCRH: 8-bit A/D conversion result register … 161 ADM: A/D converter mode register … 158 ADS: Analog input channel specify register … 160 ASICL6: Asynchronous serial interface control register 6 …...
Page 304 APPENDIX C REGISTER INDEX www.DataSheet4U.com Port register 2 … 57 Port register 3 … 57 Port register 4 … 57 P12: Port register 12 … 57 P13: Port register 13 … 57 PCC: Processor clock control register … 65 PM2: Port mode register 2 …...

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Mpd78f9221 Mpd78f9222

NEC 78K0S/KA1+ Preliminary User's Manual

Chapter 1 Overview

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generators

Chapter 6 16-Bit Timer/Event Counter 00

Chapter 7 8-Bit Timer 80

Chapter 8 8-Bit Timer H1

Chapter 9 Watchdog Timer

Chapter 10 A/D Converter

Chapter 11 Serial Interface Uart6

Chapter 12 Interrupt Functions

Chapter 13 Standby Function

Chapter 14 Reset Function

Chapter 15 Power-On-Clear Circuit

Chapter 16 Low-Voltage Detector

Chapter 17 Option Byte

Chapter 18 Flash Memory

Chapter 19 Instruction Set Overview

Chapter 20 Electrical Specifications (Target Values)

Chapter 21 Package Drawing

Appendix A Development Tools

Appendix B Notes on Target System Design

Appendix C Register Index

Quick Links

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Summary of Contents for NEC 78K0S/KA1+