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NEC mPD17P133 Manuals
Manuals and User Guides for NEC mPD17P133. We have
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NEC mPD17P133 manual available for free PDF download: User Manual
NEC mPD17P133 User Manual (289 pages)
4-Bit Single-Chip Microcontroller
Brand:
NEC
| Category:
Microcontrollers
| Size: 1.14 MB
Table of Contents
Table of Contents
6
Chapter 1 General
16
Function List
17
Ordering Information
18
Block Diagram
19
PIN CONFIGURATION (Top View)
21
Chapter 2 Pin Functions
24
Pin Functions
24
Pins in Normal Operation Mode
24
Pins in Program Memory Write/Verify Mode
26
Pin Input/Output Circuit
27
Handling Unused Pins
32
CAUTIONS on USE of the RESET and INT PINS (in Normal Operation Mode Only)
33
Chapter 3 Program Counter (Pc)
34
Program Counter Configuration
34
Program Counter Operation
34
Program Counter
34
Program Counter at Reset
35
Program Counter During Execution of the Branch Instruction (BR)
35
Program Counter During Execution of Subroutine Calls (CALL)
36
Program Counter During Execution of Return Instructions (RET, RETSK, RETI)
37
Program Counter During Table Reference (MOVT)
37
Program Counter During Execution of Skip Instructions (SKE, SKGE, SKLT, SKNE, SKT SKF)
37
Program Counter When an Interrupt Is Received
37
Cautions on Program Counter Operation
37
Chapter 4 Program Memory (Rom)
38
Program Memory Configuration
38
Program Memory Usage
39
Flow of the Program
39
Chapter 5 Data Memory (Ram)
46
Data Memory Configuration
46
System Register (SYSREG)
47
Data Buffer (DBF)
47
General Register (GR)
47
Port Registers
48
General Data Memory
48
Uninstalled Data Memory
48
Chapter 6 Stack
50
Stack Configuration
50
Functions of the Stack
50
Address Stack Register
51
Interrupt Stack Register
51
Stack Pointer (Sp) and Interrupt Stack Register
51
Stack Operation During Subroutines, Table References, and Interrupts
52
Stack Operation During Subroutine Calls (CALL) and Returns (RET, RETSK)
52
Stack Operation During Table Reference (MOVT DBF, @AR)
53
Executing RETI Instruction
54
Stack Nesting Levels and the Push and Pop Instructions
54
Chapter 7 System Register (Sysreg)
56
System Register Configuration
56
Address Register (Ar)
58
Address Register Configuration
58
Address Register Functions
58
Address Register Used as a Peripheral Register
59
Window Register (Wr)
60
Window Register Configuration
60
Window Register Functions
60
Bank Register (Bank)
61
INDEX REGISTER (IX) and DATA MEMORY ROW ADDRESS POINTER (Memory Pointer: MP)
62
Index Register (IX)
62
Data Memory Row Address Pointer (Memory Pointer: MP)
62
MPE=0 and IXE=0 (no Data Memory Modification)
65
MPE=1 and IXE=0 (Diagonal Indirect Data Transfer)
67
MPE=0 and IXE=1 (Index Modification)
69
Example of Operation When MPE=0 and IXE=0
72
Example of Operation When MPE=0 and IXE=1
72
General Register Pointer (Rp)
74
Example of Operation When MPE=1 and IXE=0
72
General Register Pointer Configuration
74
Functions of the General Register Pointer
75
Program Status Word (Psword)
76
Program Status Word Configuration
76
Functions of the Program Status Word
77
Index Enable Flag (IXE)
78
Zero Flag (Z) and Compare Flag (CMP)
78
Carry Flag (CY)
79
Binary-Coded Decimal Flag (BCD)
79
Caution on Use of Arithmetic Operations on the Program Status Word
79
Cautions on Use of the System Register
80
Reserved Words for Use with the System Register
80
Handling of System Register Addresses Fixed at
82
Chapter 8 General Register (Gr)
84
General Register Configuration
84
Functions of the General Register
84
Chapter 9 Register File (Rf)
86
Register File Configuration
86
Configuration of the Register File
86
Relationship between the Register File and Data Memory
86
Functions of the Register File
87
Control Register Functions
87
Register File Manipulation Instructions
88
Control Register
90
Cautions on Using the Register File
90
Concerning Operation of the Control Register (Read-Only and Unused Registers)
90
Register File Symbol Definitions and Reserved Words
91
Chapter 10 Data Buffer (Dbf)
94
Data Buffer Configuration
94
Functions of the Data Buffer
95
Data Buffer and Peripheral Hardware
96
Data Transfer with Peripheral Hardware
97
Chapter 11 Arithmetic and Logic Unit
100
Alu Block Configuration
100
Functions of the Alu Block
100
Functions of the ALU
100
Functions of Temporary Registers a and B
105
Functions of the Status Flip-Flop
105
Performing Operations in 4-Bit Binary
106
Performing Operations in BCD
106
Performing Operations in the ALU Block
108
Arithmetic Operations (Addition and Subtraction in 4-Bit Binary and Bcd)
109
Addition and Subtraction When CMP=0 and BCD=0
110
Addition and Subtraction When CMP=1 and BCD=0
110
Addition and Subtraction When CMP=0 and BCD=1
110
Addition and Subtraction When CMP=1 and BCD=1
111
Cautions on Use of Arithmetic Operations
111
Logical Operations
111
Bit Judgement
112
TRUE (1) Bit Judgement
113
FALSE (0) Bit Judgement
113
Comparison Judgement
114
Equal To" Judgement
115
Not Equal To" Judgement
115
Greater than or Equal To" Judgement
116
Less Than" Judgement
116
Rotations
117
Rotation to the Right
117
Rotation to the Left
118
Chapter 12 Ports
120
Port 0A (P0A , P0A 1 , P0A 2 , P0A 3 )
120
Port 0B (P0B , P0B 1 , P0B 2 , P0B 3 )
121
Port 0C (P0C , P0C , P0C , P0C )
122
In the Case of the Μ PD17120 and 17121
122
Port 0C
123
In the Case of the Μ PD17132
123
Port P0D (Pp0D /Sck, Pp0D /So, Pp0D /Si, Pp0D /Tmout)
124
PORT 0E (P0E0, P0E1/V ) ... V , Μ PD17132, 17133, 17P132, and 17P133 Only
126
Cautions When Operating Port Registers
127
Port Control Register
128
Input/Output Switching by Group I/O
128
Input/Output Switching by Bit I/O
129
Chapter 13 Peripheral Hardware
132
8-Bit Timer Counter (Tm)
132
8-Bit Timer Counter Configuration
132
8-Bit Timer Counter Control Register
134
Operation of 8-Bit Timer Counters
135
Selecting Count Pulse
135
Setting a Count Value in Modulo Register and Calculation Method
136
Margin of Error of Interval Time
139
Reading Count Register Values
141
Timer Output
144
Timer Resolution and Maximum Setting Time
145
COMPARATOR (Mpd17132, 17133, 17P132, and 17P133 ONLY)
146
Configuration of Comparator
146
Functions of Comparator
147
Serial Interface (Sio)
150
Functions of the Serial Interface
150
3-Wire Serial Interface Operation Modes
152
Setting Values in the Shift Register
156
Reading Values from the Shift Register
157
Program Example of Serial Interface
158
Chapter 14 Interrupt Functions
160
Interrupt Sources and Vector Address
161
Hardware Components of the Interrupt Control Circuit
162
Interrupt Request Flag (IRQ×××) and the Interrupt Enable Flag (IP×××)
162
EI/DI Instruction
162
Interrupt Sequence
167
Acceptance of Interrupts
167
Return from the Interrupt Routine
169
Interrupt Acceptance Timing
170
Program Example of Interrupt
173
Chapter 15 Standby Functions
176
Outline of Standby Function
176
Halt Mode
178
HALT Mode Setting
178
Start Address after HALT Mode Is Canceled
178
HALT Setting Condition
180
Stop Mode
182
STOP Mode Setting
182
Start Address after STOP Mode Cancellation
182
STOP Setting Condition
184
Chapter 16 Reset
186
Reset Functions
186
Resetting
187
Power-On/Power-Down Reset Function
188
Conditions Required to Enable the Power-On Reset Function
188
Description and Operation of the Power-On Reset Function
189
Condition Required for Use of the Power-Down Reset Function
191
Description and Operation of the Power-Down Reset Function
191
Chapter 17 One-Time Prom Writing/Verifying
194
Differences between Mask Rom Version and One-Time Prom Version
194
Operating Mode in Program Memory Writing/Verifying
195
Writing Procedure of Program Memory
196
Reading Procedure of Program Memory
197
Chapter 18 Instruction Set
200
Overview of the Instruction Set
200
Legend
201
List of the Instruction Set
202
Assembler (As17K) Macro Instructions
203
Instructions
204
Addition Instructions
204
Subtraction Instructions
217
Logical Operation Instructions
226
Judgment Instruction
231
Comparison Instructions
233
Rotation Instructions
236
Transfer Instructions
237
Branch Instructions
254
Subroutine Instructions
256
Interrupt Instructions
262
Other Instructions
264
Chapter 19 Assembler Reserved Words
266
Mask Option Pseudo Instructions
266
OPTION and ENDOP Pseudo Instructions
266
Mask Option Definition Pseudo Instructions
267
Reserved Symbols
269
List of Reserved Symbols ( Μ PD17120, 17121)
269
List of Reserved Symbols ( Μ PD17132, 17133, 17P132, 17P133)
275
Appendix A Development Tools
282
Appendix B Ordering Mask Rom
284
Appendix C Cautions to Take in System Clock Oscillation Circuit Configurations
286
Appendix D Instruction List
288
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