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NEC mPD780204A Manuals
Manuals and User Guides for NEC mPD780204A. We have
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NEC mPD780204A manual available for free PDF download: User Manual
NEC mPD780204A User Manual (418 pages)
8-Bit Single-Chip Microcontrollers
Brand:
NEC
| Category:
Microcontrollers
| Size: 1.75 MB
Table of Contents
Table of Contents
10
Chapter 1 Outline
24
Features
24
Applications
25
Ordering Information
25
Quality Grade
25
Pin Configuration (Top View)
26
Series Lineup
29
Block Diagram
31
Overview of Functions
32
Mask Options
33
Mask Options in Mask ROM Versions
33
Chapter 2 Pin Functions
34
Pin Function List
34
Normal Operating Mode Pins
34
PROM Programming Mode Pins ( Μ PD78P0208 Only)
37
Description of Pin Functions
38
P00 to P04 (Port 0)
38
P10 to P17 (Port 1)
38
P20 to P27 (Port 2)
39
P30 to P37 (Port 3)
39
P70 to P74 (Port 7)
40
P80 to P87 (Port 8)
40
P90 to P97 (Port 9)
40
P100 to P107 (Port 10)
41
P110 to P117 (Port 11)
41
P120 to P127 (Port 12)
41
FIP0 to FIP12
41
Vload
42
Av Ref
42
Av DD
42
Av Ss
42
Reset
42
X1 and X2
42
XT1 and XT2
42
VDD
42
Vss
42
VPP ( Μ PD78P0208 Only)
42
Pin I/O Circuits and Recommended Connection of Unused Pins
43
Types of Pin I/O Circuits
43
Pin I/O Circuits
45
Chapter 3 Cpu Architecture
48
Memory Space
48
Memory Map ( Μ PD780204 and Μ PD780204A)
48
Memory Map ( Μ PD780205 and Μ PD780205A)
49
Memory Map ( Μ PD780206)
50
Memory Map ( Μ PD780208)
51
Memory Map ( Μ PD78P0208)
52
Internal Program Memory Space
53
Internal ROM Capacity
53
Vector Table
53
Internal Data Memory Space
54
Special-Function Register (SFR) Area
54
Data Memory Addressing
55
Data Memory Addressing ( Μ PD780204 and Μ PD780204A)
55
Data Memory Addressing ( Μ PD780205 and Μ PD780205A)
56
Data Memory Addressing ( Μ PD780206)
57
Data Memory Addressing ( Μ PD780208)
58
Data Memory Addressing ( Μ PD78P0208)
59
Processor Registers
60
Control Registers
60
Program Counter Format
60
Program Status Word Format
60
Stack Pointer Format
61
Data to be Reset from Stack Memory
62
General-Purpose Registers
63
Data to be Saved to Stack Memory
62
General-Purpose Register Configuration
63
Special-Function Registers (Sfrs)
64
Special-Function Register List
65
Instruction Address Addressing
68
Relative Addressing
68
Immediate Addressing
69
Table Indirect Addressing
70
Register Addressing
71
Operand Address Addressing
72
Implied Addressing
72
Register Addressing
73
Direct Addressing
74
Short Direct Addressing
75
Special-Function Register (SFR) Addressing
76
Register Indirect Addressing
77
Based Addressing
78
Based Indexed Addressing
79
Stack Addressing
79
Chapter 4 Port Functions
80
Port Functions
80
Port Types
80
Port Functions
81
Port Configuration
83
Port 0
83
Block Diagram of P00 and P04
84
Block Diagram of P01 to P03
84
Port 1
85
Block Diagram of P10 to P17
85
Port 2
86
Block Diagram of P20, P21, P23 to P26
86
Block Diagram of P22 and P27
87
Port 3
88
Block Diagram of P30 to P37
88
Port 7
89
Block Diagram of P70 to P74
89
Port 8
90
Block Diagram of P80 to P87
90
Port 9
91
Block Diagram of P90 to P97
91
Port 10
92
Block Diagram of P100 to P107
92
Port 11
93
Block Diagram of P110 to P117
93
Port 12
94
Block Diagram of P120 to P127
94
Port Function Control Registers
95
Port Mode Register and Output Latch Setting When Alternate Function Is Used
95
Format of Port Mode Register
96
Format of Pull-Up Resistor Option Register
97
Port Function Operations
98
Operations on I/O Port
98
Reading from I/O Port
98
Writing to I/O Port
98
Comparison between Mask Option of Mask ROM Version and Μ PD78P0208
99
Selection of Mask Option
99
Chapter 5 Clock Generator
100
Clock Generator Functions
100
Clock Generator Configuration
100
Clock Generater Block Diagram
101
Clock Generator Control Registers
102
Feedback Resistor of Subsystem Clock
102
Format of Processor Clock Control Register
103
Relationship between CPU Clock and Minimum Instruction Execution Time
104
Format of Display Mode Register 0
105
Format of Display Mode Register 1
108
System Clock Oscillator
109
External Circuit of Main System Clock Oscillator
109
Subsystem Clock Oscillator
110
Main System Clock Oscillator
109
External Circuit of Subsystem Clock Oscillator
110
Examples of Incorrect Resonator Connection
111
Divider
113
When Subsystem Clock Is Not Used
113
Clock Generator Operations
114
Main System Clock Operations
115
Main System Clock Stop Function
115
Subsystem Clock Operations
116
Changing System Clock and CPU Clock Settings
117
Maximum Time Required for CPU Clock Switchover
117
System Clock and CPU Clock Switching Procedure
118
Time Required for Switchover between System Clock and CPU Clock
117
System Clock and CPU Clock Switching
118
Chapter 6 16-Bit Timer/Event Counter
119
Outline of Timers Incorporated in Μ PD780208 Subseries
119
16-Bit Timer/Event Counter Functions
120
Timer/Event Counter Operations
120
16-Bit Timer/Event Counter Interval Time
121
16-Bit Timer/Event Counter Square-Wave Output Ranges
121
16-Bit Timer/Event Counter Configuration
122
16-Bit Timer/Event Counter Control Registers
127
Format of Timer Clock Select Register 0
128
Format of 16-Bit Timer Mode Control Register
130
Format of 16-Bit Timer Output Control Register
131
Format of Port Mode Register 3
132
Format of External Interrupt Mode Register
133
Format of Sampling Clock Select Register
134
16-Bit Timer/Event Counter Operations
135
Interval Timer Operations
135
16-Bit Timer/Event Counter Interval Time
136
Interval Timer Operation Timing
136
PWM Output Operations
137
Pulse Width Measurement Operations
138
Configuration Diagram for Pulse Width Measurement in Free-Running Mode
139
External Event Counter Operation
140
External Event Counter Configuration Diagram
141
Square-Wave Output Operation
142
16-Bit Timer/Event Counter Square-Wave Output Ranges
142
16-Bit Timer/Event Counter Operating Precautions
143
Capture Register Data Retention Timing
144
Chapter 7 8-Bit Timer/Event Counter
145
8-Bit Timer/Event Counter Functions
145
8-Bit Timer/Event Counter Mode
145
8-Bit Timer/Event Counter Interval Time
146
8-Bit Timer/Event Counter Square-Wave Output Ranges
147
16-Bit Timer/Event Counter Mode
148
Interval Time When 8-Bit Timer/Event Counter Is Used as 16-Bit Timer/Event Counter
148
Is Used as 16-Bit Timer/Event Counter
149
8-Bit Timer/Event Counter Configuration
150
Block Diagram of 8-Bit Timer/Event Counter Output Controller 1
152
8-Bit Timer/Event Counter Control Registers
153
Format of Timer Clock Select Register 1
154
Format of 8-Bit Timer Mode Control Register
155
Format of 8-Bit Timer Output Control Register
156
Format of Port Mode Register 3
157
8-Bit Timer/Event Counter Operations
158
8-Bit Timer/Event Counter Mode
158
8-Bit Timer/Event Counter 1 Interval Time
159
8-Bit Timer/Event Counter 2 Interval Time
159
External Event Counter Operation Timing (with Rising Edge Specified)
160
8-Bit Timer/Event Counter Square-Wave Output Ranges
161
Square-Wave Output Operation Timing
161
16-Bit Timer/Event Counter Mode
162
(TM1 and TM2) Is Used as 16-Bit Timer/Event Counter
163
External Event Counter Operation Timing (with Rising Edge Specified)
164
(TM1 and TM2) Are Used as 16-Bit Timer/Event Counter
165
Square-Wave Output Operation Timing
165
8-Bit Timer/Event Counter Operating Precautions
166
Timing after Compare Register Change During Timer Count Operation
167
Chapter 8 Watch Timer
168
Watch Timer Functions
168
Interval Timer Interval Time
168
Watch Timer Configuration
169
Watch Timer Control Registers
169
Format of Timer Clock Select Register 2
171
Format of Watch Timer Mode Control Register
172
Watch Timer Operations
173
Interval Timer Interval Time
173
Interval Timer Operation
173
Watch Timer Operation
173
Chapter 9 Watchdog Timer
174
Watchdog Timer Functions
174
Watchdog Timer Program Loop Detection Time
174
Interval Time
174
Watchdog Timer Configuration
175
Watchdog Timer Control Registers
177
Format of Timer Clock Select Register 2
178
Format of Watchdog Timer Mode Register
179
Watchdog Timer Operations
180
Watchdog Timer Operation
180
Watchdog Timer Program Loop Detection Time
180
Interval Timer Operation
181
Chapter 10 Clock Output Controller
182
Clock Output Controller Functions
182
Clock Output Controller Configuration
183
Clock Output Function Control Registers
183
Format of Timer Clock Select Register 0
184
Format of Port Mode Register 3
185
Chapter 11 Buzzer Output Controller
186
Buzzer Output Controller Functions
186
Buzzer Output Controller Configuration
186
Buzzer Output Function Control Registers
187
Format of Timer Clock Select Register 2
188
Format of Port Mode Register 3
189
Chapter 12 A/D Converter
190
A/D Converter Functions
190
A/D Converter Configuration
190
A/D Converter Block Diagram
191
A/D Converter Control Registers
194
Format of A/D Converter Mode Register
195
Format of A/D Converter Input Select Register
196
A/D Converter Operations
197
Basic Operations of A/D Converter
197
Basic Operation of A/D Converter
198
Input Voltage and Conversion Results
199
A/D Converter Operating Mode
200
A/D Conversion by Software Start
201
A/D Converter Precautions
202
Analog Input Pin Processing
203
A/D Conversion End Interrupt Request Generation Timing
204
Chapter 13 Serial Interface Channel 0
205
Functions of Serial Interface Channel 0
206
Configuration of Serial Interface Channel 0
207
Control Registers of Serial Interface Channel 0
211
Format of Timer Clock Select Register 3
212
Format of Serial Operating Mode Register 0
213
Format of Serial Bus Interface Control Register
214
Format of Interrupt Timing Specification Register
216
Operations of Serial Interface Channel 0
217
Operation Stop Mode
217
3-Wire Serial I/O Mode Operation
218
Wire Serial I/O Mode Timing
221
RELT and CMDT Operations
222
SBI Mode Operation
223
Example of Serial Bus Configuration with SBI
224
SBI Transfer Timing
226
Bus Release Signal
227
Address
228
Commands
229
Acknowledge Signal
230
BUSY and READY Signals
231
RELT, CMDT, RELD, and CMDD Operations (Master)
236
ACKT Operation
237
ACKE Operations
238
ACKD Operations
239
Pin Configuration
242
2-Wire Serial I/O Mode Operation
249
Wire Serial I/O Mode Timing
253
RELT and CMDT Operations
254
SCK0/P27 Pin Output Manipulation
255
Chapter 14 Serial Interface Channel 1
256
Functions of Serial Interface Channel 1
256
Configuration of Serial Interface Channel 1
257
Control Registers of Serial Interface Channel 1
260
Format of Timer Clock Select Register 3
261
Format of Serial Operating Mode Register 1
262
Format of Automatic Data Transmit/Receive Control Register
264
Format of Automatic Data Transmit/Receive Interval Specification Register
265
Operations of Serial Interface Channel 1
268
Operation Stop Mode
268
3-Wire Serial I/O Mode Operation
269
Wire Serial I/O Mode Timing
270
Circuit for Switching Transfer Bit Order
271
3-Wire Serial I/O Mode Operation with Automatic Transmit/Receive Function
272
Basic Transmission/Reception Mode Operation Timing
279
Basic Transmission/Reception Mode Flowchart
280
Basic Transmission Mode Operation Timing
283
Basic Transmission Mode Flowchart
284
Buffer RAM Operation in 6-Byte Transmission (in Basic Transmission Mode)
285
Repeat Transmission Mode Operation Timing
287
Repeat Transmission Mode Flowchart
288
Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode)
289
Automatic Transmission/Reception Suspension and Restart
291
System Configuration with Busy Control Option
292
Operation Timing When Using Busy Control Option (BUSY0 = 0)
293
Operation Timing When Using Busy & Strobe Control Option (BUSY0 = 0)
294
Operation Timing of Bit Slippage Detection Function Using Busy Signal (BUSY0 = 1)
295
Automatic Transmit/Receive Interval
296
Interval Determined by CPU Processing (with Internal Clock Operation)
297
Interval Determined by CPU Processing (with External Clock Operation)
298
Chapter 15 Vfd Controller/Driver
299
VFD Controller/Driver Functions
299
VFD Controller Operation Timing in Display Mode 1 (DSPM05 = 0)
300
VFD Controller/Driver Configuration
301
VFD Controller/Driver Control Registers
303
Control Registers
303
Format of Display Mode Register 0
305
Format of Display Mode Register 1
307
Format of Display Mode Register 2
308
One-Display Period and Cut Width
310
Selecting Display Mode
311
Display Mode and Display Output
312
Display Data Memory
313
Key Scan Flag and Key Scan Data
314
Key Scan Flag
314
Key Scan Data
314
Light Leakage of VFD
315
Display Examples
317
Segment Type (Display Mode 1: DSPM05 = 0)
318
Dot Type (Display Mode 1: DSPM05 = 0)
320
Relationship between Display Data Memory Contents and Segment Outputs in 35-Segment X 16-Digit Display Mode
321
Display Type in Which a Segment Spans Two or more Grids (Display Mode 2: DSPM05 = 1)
322
Display Data Memory Configuration and Data Reading Order (Display Mode 2)
322
Grid Driving Timing
324
Calculating Total Power Dissipation
326
Segment Type (Display Mode 1: DSPM05 = 0)
326
Relationship between Display Data Memory Contents and Segment Outputs in 10-Segment X 11-Digit Display Mode
328
Dot Type (Display Mode 1: DSPM05 = 0)
329
Relationship between Display Data Memory Contents and Segment Outputs in 35-Segment X 16-Digit Display Mode
331
Display Type in Which a Segment Spans Two or more Grids (Display Mode 2: DSPM05 = 1)
332
Grid Driving Timing
333
Chapter 16 Interrupt and Test Functions
335
Interrupt Function Types
335
Interrupt Sources and Configuration
336
Basic Configuration of Interrupt Function
337
Interrupt Function Control Registers
339
Format of Interrupt Request Flag Register
340
Format of Interrupt Mask Flag Register
341
Format of Priority Specification Flag Register
342
Format of External Interrupt Mode Register
343
Format of Sampling Clock Select Register
344
Noise Eliminator I/O Timing (When Rising Edge Is Detected)
345
Format of Program Status Word
346
Interrupt Servicing Operations
347
Non-Maskable Interrupt Request Acknowledgment Operation
347
Non-Maskable Interrupt Request Acknowledgment Flowchart
348
Non-Maskable Interrupt Request Acknowledgment Operation
349
Maskable Interrupt Request Acknowledgment Operation
350
Interrupt Request Acknowledge Processing Algorithm
351
Software Interrupt Request Acknowledgment Operation
352
Multiple Interrupt Servicing
353
Multiple Interrupt Servicing Example
354
Interrupt Request Hold
356
Test Functions
357
Test Function Control Registers
357
Test Input Signal Acknowledgment Operation
358
Chapter 17 Standby Function
359
Standby Function and Configuration
359
Standby Function
359
Standby Function Control Register
360
Standby Function Operations
361
HALT Mode
361
HALT Mode Release by Interrupt Request Generation
362
HALT Mode Release by RESET Input
363
STOP Mode
364
STOP Mode Release by Interrupt Request Generation
365
STOP Mode Release by RESET Input
366
Chapter 18 Reset Function
367
Reset Function
367
Timing of Reset by RESET Input
368
Hardware Status after Reset
369
CHAPTER 19 Μ PD78P0208
371
Internal Memory Size Switching Register
372
Format of Internal Memory Size Switching Register (IMS)
373
Internal Expansion RAM Size Switching Register
374
PROM Programming
375
Operating Modes
375
PROM Write Procedure
377
Page Program Mode Timing
378
Byte Program Mode Flowchart
379
Byte Program Mode Timing
380
PROM Read Procedure
381
Screening of One-Time PROM Version
382
Chapter 20 Instruction Set
383
Conventions
384
Operand Identifiers and Description Methods
384
Description of "Operation" Column
385
Description of "Flag Operation" Column
385
Operation List
386
Instructions Listed by Addressing Type
394
APPENDIX A DIFFERENCES between Μ PD78044H, 780228, and 780208 SUBSERIES
398
Appendix Bdevelopment Tools
399
B-1 Configuration of Development Tools
400
Software Package
401
Language Processing Software
401
B.1 Software Package
401
Control Software
402
B.3 Control Software
402
PROM Programming Tools
403
Hardware
403
Software
403
Debugging Tools (Hardware)
404
When Using In-Circuit Emulator IE-78K0-NS, IE-78K0-NS-A
404
When Using In-Circuit Emulator IE-78001-R-A
405
Debugging Tools (Software)
406
Embedded Software
407
B.7 Embedded Software
407
Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A
408
Conversion Socket (EV-9200GF-100) Package Drawing and Recommended Footprint
409
B-3 Recommended Footprint for EV-9200GF-100 (for Reference Purposes Only)
410
Notes on Target System Design
411
B-5 Connection Conditions of Target System (When NP-100GF-TQ Is Used)
412
Appendix Cregister Index
413
Register Index (by Register Name)
413
Register Index (by Register Symbol)
415
Appendix D Revision History
417
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