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?PD70F3302Y
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Manuals and User Guides for NEC ?PD70F3302Y. We have
1
NEC ?PD70F3302Y manual available for free PDF download: User Manual
NEC ?PD70F3302Y User Manual (709 pages)
32-bit Single-Chip Microcontrollers
Brand:
NEC
| Category:
Microcontrollers
| Size: 4.03 MB
Table of Contents
Table of Contents
8
Chapter 1 Introduction
17
K1 Series Product Lineup
17
V850Es/Kx1+, V850Es/Kx1 Products Lineup
17
78K0/Kx1+, 78K0/Kx1 Products Lineup
20
Features
23
Applications
24
Ordering Information
24
Pin Configuration (Top View)
25
Function Block Configuration
27
Overview of Functions
31
Chapter 2 Pin Functions
32
List of Pin Functions
32
Pin I/O Circuits and Recommended Connection of Unused Pins
36
Pin I/O Circuits
38
Chapter 3 Cpu Functions
40
Features
40
CPU Register Set
41
Program Register Set
42
System Register Set
43
Operating Modes
49
Address Space
50
CPU Address Space
50
Wraparound of CPU Address Space
51
Memory Map
52
Areas
54
Recommended Use of Address Space
56
Peripheral I/O Registers
58
Special Registers
65
Cautions
68
Chapter 4 Port Functions
71
Features
71
Basic Port Configuration
71
Port Configuration
72
Port 0
78
Port 3
80
Port 4
85
Port 5
87
Port 7
90
Port 9
91
Port CM
97
Port DL
99
Block Diagrams
101
Port Register Setting When Alternate Function Is Used
119
Cautions
123
Cautions on Bit Manipulation Instruction for Port N Register (Pn)
123
Hysteresis Characteristics
124
Chapter 5 Clock Generation Function
125
Overview
125
Configuration
126
Registers
128
Operation
133
Operation of each Clock
133
Clock Output Function
133
External Clock Input Function
133
PLL Function
134
Overview
134
Register
134
Usage
135
Chapter 6 16-Bit Timer/Event Counter P (Tmp)
136
Overview
136
Functions
136
Configuration
137
Registers
139
Operation
150
Interval Timer Mode (TP0MD2 to TP0MD0 Bits = 000)
151
External Event Count Mode (TP0MD2 to TP0MD0 Bits = 001)
161
External Trigger Pulse Output Mode (TP0MD2 to TP0MD0 Bits = 010)
169
One-Shot Pulse Output Mode (TP0MD2 to TP0MD0 Bits = 011)
181
PWM Output Mode (TP0MD2 to TP0MD0 Bits = 100)
188
Free-Running Timer Mode (TP0MD2 to TP0MD0 Bits = 101)
197
Pulse Width Measurement Mode (TP0MD2 to TP0MD0 Bits = 110)
214
Timer Output Operations
220
Eliminating Noise on Capture Trigger Input Pin (Tip0A)
221
Cautions
223
Chapter 7 16-Bit Timer/Event Counter 0
224
Functions
224
Configuration
225
Registers
231
Operation
238
Interval Timer Operation
238
Square Wave Output Operation
241
External Event Counter Operation
244
Operation in Clear & Start Mode Entered by TI010 Pin Valid Edge Input
247
Free-Running Timer Operation
262
PPG Output Operation
271
One-Shot Pulse Output Operation
274
Pulse Width Measurement Operation
279
Special Use of TM01
287
Rewriting CR011 Register During TM01 Operation
287
Setting LVS01 and LVR01 Bits
287
Cautions
289
Chapter 8 8-Bit Timer/Event Counter 5
293
Functions
293
Configuration
294
Registers
297
Operation
300
Operation as Interval Timer
300
Operation as External Event Counter
302
Square-Wave Output Operation
303
8-Bit PWM Output Operation
305
Operation as Interval Timer (16 Bits)
308
Operation as External Event Counter (16 Bits)
310
Square-Wave Output Operation (16-Bit Resolution)
311
Cautions
312
Chapter 9 8-Bit Timer H
313
Functions
313
Configuration
313
Registers
316
Operation
320
Operation as Interval Timer/Square Wave Output
320
PWM Output Mode Operation
323
Carrier Generator Mode Operation
329
Chapter 10 Interval Timer, Watch Timer
336
Interval Timer BRG
336
Functions
336
Configuration
336
Registers
338
Operation
340
Watch Timer
341
Functions
341
Configuration
341
Register
342
Operation
344
Cautions
346
Chapter 11 Watchdog Timer Functions
347
Watchdog Timer 1
347
Functions
347
Configuration
349
Registers
349
Operation
351
Watchdog Timer 2
353
Functions
353
Configuration
354
Registers
354
Operation
356
Chapter 12 Real-Time Output Function (Rto)
357
Function
357
Configuration
358
Registers
359
Operation
361
Usage
362
Cautions
362
Security Function
363
Chapter 13 A/D Converter
365
Overview
365
Functions
365
Configuration
366
Registers
368
Operation
377
Basic Operation
377
Trigger Modes
378
Operation Modes
379
Power Fail Detection Function
382
Setting Method
383
Cautions
385
How to Read A/D Converter Characteristics Table
391
Chapter 14 Asynchronous Serial Interface (Uart)
395
Features
395
Configuration
396
Registers
398
Interrupt Request Signals
407
Operation
408
Data Format
408
Transmit Operation
409
Continuous Transmission Operation
411
Receive Operation
415
Reception Error
417
Parity Types and Corresponding Operation
418
Receive Data Noise Filter
419
SBF Transmission/Reception (UART0 Only)
420
Dedicated Baud Rate Generator N (Brgn)
424
Baud Rate Generator N (Brgn) Configuration
424
Serial Clock Generation
425
Baud Rate Setting Example
428
Allowable Baud Rate Range During Reception
429
Transfer Rate During Continuous Transmission
431
Cautions
431
Chapter 15 Clocked Serial Interface 0 (Csi0)
432
Features
432
Configuration
433
Registers
436
Operation
445
Transmission/Reception Completion Interrupt Request Signal (Intcsi0N)
445
Single Transfer Mode
447
Continuous Transfer Mode
450
Output Pins
458
Chapter 16 I C Bus
459
Features
459
Configuration
462
Registers
464
Functions
477
Pin Configuration
477
I C Bus Definitions and Control Methods
478
Start Condition
478
Addresses
479
Transfer Direction Specification
479
Ack
480
Stop Condition
481
Wait State
482
Wait State Cancellation Method
484
C Interrupt Request Signals (INTIIC0)
485
Master Device Operation
486
Slave Device Operation (When Receiving Slave Address (Match with Address))
489
Slave Device Operation (When Receiving Extension Code)
493
Arbitration Loss Operation (Operation as Slave after Arbitration Loss)
497
Operation Without Communication
497
Operation When Arbitration Loss Occurs (no Communication after Arbitration Loss)
499
Interrupt Request Signal (INTIIC0) Generation Timing and Wait Control
506
Address Match Detection Method
507
Error Detection
507
Extension Code
508
Arbitration
509
Wakeup Function
510
Communication Reservation
511
When Communication Reservation Function Is Enabled (IICF0.IICRSV0 Bit = 0)
511
When Communication Reservation Function Is Disabled (IICF0.IICRSV0 Bit = 1)
514
Cautions
515
Communication Operations
516
Master Operation in Single Master System
517
Master Operation in Multimaster System
518
Slave Operation
521
Timing of Data Communication
524
Chapter 17 Interrupt/Exception Processing Function
531
Overview
531
Features
531
Non-Maskable Interrupts
534
Operation
537
Restore
538
NP Flag
539
Maskable Interrupts
540
Operation
540
Restore
542
Priorities of Maskable Interrupts
543
Interrupt Control Register (Xxlcn)
547
Interrupt Mask Registers 0, 1, 3 (IMR0, IMR1, IMR3)
549
In-Service Priority Register (ISPR)
550
ID Flag
551
Watchdog Timer Mode Register 1 (WDTM1)
552
External Interrupt Request Input Pins (NMI, INTP0 to INTP7)
553
Noise Elimination
553
Edge Detection
555
Software Exceptions
559
Operation
559
Restore
560
EP Flag
561
Exception Trap
562
Illegal Opcode
562
Debug Trap
564
Multiple Interrupt Servicing Control
566
Interrupt Response Time
568
Periods in Which Interrupts Are Not Acknowledged by CPU
569
Cautions
569
Chapter 18 Key Interrupt Function
570
Function
570
Register
571
Chapter 19 Standby Function
572
Overview
572
Registers
575
HALT Mode
578
Setting and Operation Status
578
Releasing HALT Mode
578
IDLE Mode
580
Setting and Operation Status
580
Releasing IDLE Mode
580
STOP Mode
582
Setting and Operation Status
582
Releasing STOP Mode
582
Securing Oscillation Stabilization Time When STOP Mode Is Released
584
Subclock Operation Mode
585
Setting and Operation Status
585
Releasing Subclock Operation Mode
585
Sub-IDLE Mode
587
Setting and Operation Status
587
Releasing Sub-IDLE Mode
587
Chapter 20 Reset Function
589
Overview
589
Configuration
589
Register to Check Reset Source
590
Reset Sources
591
Reset Operation Via RESET Pin
591
Reset Operation by WDTRES1 Signal
595
Reset Operation by WDTRES2 Signal
596
Power-On-Clear Reset Operation
597
Reset Operation by Low-Voltage Detector
600
Reset Operation by Clock Monitor
601
Reset Output Function
602
Chapter 21 Clock Monitor
603
Function
603
Registers
603
Operation
605
Internal Oscillation Clock Operation Mode
608
Setting and Operation Status
608
Releasing Internal Oscillation Clock Operation Mode
608
Internal Oscillation HALT Mode
611
Setting and Operation Status
611
Releasing Internal Oscillation HALT Mode
611
Chapter 22 Low-Voltage Detector
613
Function
613
Configuration
613
Registers
614
Operation
616
Chapter 23 Power-On-Clear Circuit
618
Function
618
Configuration
618
Operation
619
Chapter 24 Rom Correction Function
620
Overview
620
Control Registers
621
Correction Address Registers 0 to 3 (CORAD0 to CORAD3)
621
Correction Control Register (CORCN)
622
ROM Correction Operation and Program Flow
622
Chapter 25 Mask Option/Option Byte
624
Mask Option (Mask ROM Versions)
624
Option Byte (Flash Memory Versions)
625
Chapter 26 Flash Memory
626
Features
626
Memory Configuration
627
Functional Outline
628
Rewriting by Dedicated Flash Programmer
632
Programming Environment
632
Communication Mode
633
Flash Memory Control
638
Selection of Communication Mode
639
Communication Commands
640
Pin Connection
641
Rewriting by Self Programming
646
Overview
646
Features
647
Standard Self Programming Flow
648
Flash Functions
649
Pin Processing
649
Internal Resources Used
650
Chapter 27 On-Chip Debug Function
651
ROM Security Function
651
Security ID
651
Setting
652
Cautions
653
Chapter 28 Electrical Specifications
654
Chapter 29 Package Drawings
676
Chapter 30 Recommended Soldering Conditions
678
Appendix A Development Tools
680
Software Package
683
Language Processing Software
683
Control Software
683
A.1 Software Package
683
Debugging Tools (Hardware)
684
When Using IECUBE QB-V850ESKX1H
684
When Using MINICUBE QB-V850MINI
686
Debugging Tools (Software)
688
Embedded Software
689
Flash Memory Writing Tools
689
A.6 Embedded Software
689
Appendix B Instruction Set List
690
Conventions
690
Instruction Set (in Alphabetical Order)
693
Appendix C Register Index
700
Appendix D Revision History
706
Major Revisions in this Edition
706
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