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NEC PD78212 manual available for free PDF download: User Manual
NEC PD78212 User Manual (487 pages)
8-BIT SINGLE-CHIP MICROCOMPUTER SUB-SERIES
Brand:
NEC
| Category:
Computer Hardware
| Size: 3.11 MB
Table of Contents
Table of Contents
12
Fig. no
20
Title, Page
20
Table no
29
Title, Page
29
Chapter 1 General
30
Features
32
Ordering Information and Quality Grade
33
Ordering Information
33
Quality Grade
34
Pin Configuration (Top View)
35
Normal Operating Mode
35
PROM Programming Mode
40
Example Application System (Printer)
45
Block Diagram
46
Functions
47
DIFFERENCES between the Μ PD78210 and Μ PD78213
49
DIFFERENCES between the Μ PD78214 SUB-SERIES and Μ PD78218A SUB-SERIES
50
DIFFERENCES between the Μ PD78212 and Μ PD78212(A)
51
DIFFERENCES between the Μ PD78213 and Μ PD78214, and the Μ PD78213(A) and Μ PD78214(A)
51
DIFFERENCES between the Μ PD78P214 and Μ PD78P214(A)
51
DIFFERENCES between the Μ PD78212, Μ PD78213, Μ PD78214, and Μ PD78P214
52
Functional Differences
52
Package Differences
52
Chapter 2 Pin Functions
54
Pin Function List
54
Normal Operating Mode
54
PROM Programming Mode
56
Pin Functions
56
Normal Operating Mode
56
Port 2 Functions
56
Port 3 Operating Mode
58
Port 6 Operating Mode
59
PROM Programming Mode
60
I/O Circuits and Unused-Pin Handling
62
Types of I/O Circuits and Unused-Pin Handling
62
I/O Circuits Provided for Pins
63
Notes
64
Chapter 3 Cpu Function
66
Memory Space
66
Memory Map of Μ PD78212 (EA Pin Driven High)
67
Memory Map of Μ PD78212 (EA Pin Driven Low)
68
Memory Map of Μ PD78213, Μ PD78214, or Μ PD78P214 (EA Pin Driven Low)
69
Memory Map of Μ PD78214, Μ PD78P214 (EA Pin Driven High)
70
Internal Program Memory Area
71
Vector Table
71
Internal RAM Area
72
Special Function Register (SFR) Area
72
External SFR Area
72
External Memory Space
72
External Extension Data Memory Space
72
Sample Data Transfer between Banks
73
Registers
74
Program Counter (PC)
74
Program Status Word (PSW)
74
Configuration of the Program Counter
74
Configuration of the Program Status Word
74
Stack Pointer (SP)
75
Configuration of the Stack Pointer
75
Selecting a Register Bank
75
General-Purpose Registers
76
Data Saved to the Stack Area
76
Data Restored from the Stack Area
76
Configuration of General-Purpose Registers
77
Function Names and Absolute Names
78
Special Function Registers (SFR)
79
Special Function Registers (SFR)
80
Notes
82
Chapter 4 Clock Generator
84
Configuration and Function
84
Block Diagram of Clock Generator
84
External Circuit for the Clock Oscillator
84
Notes
85
Inputting an External Clock
85
Using the Crystal/Ceramic Oscillator
85
Point from Which Signals Can be Drawn When an External Clock Is Input
85
Notes on Connection of the Oscillator
86
Incorrect Oscillator Connections
86
Chapter 5 Port Functions
88
Digital I/O Ports
88
Port Configuration
88
Port 0
89
Number of I/O Ports
89
Port Functions
89
Hardware Configuration
90
Setting the Input/Output Mode and Control Mode
90
Configuration of Port 0
90
Port 0 Mode Register Format
90
Operation
91
Built-In Pull-Up Resistor
91
Driving Transistors
91
Port Specified as an Output Port
91
Example of Driving a Transistor
91
Port 2
92
Functions of Port 2
92
Hardware Configuration
93
Operation
93
Setting the Input Mode and Control Mode
93
Block Diagram of Port 2
93
Built-In Pull-Up Resistor
94
Port Specified as an Input Port
94
Built-In Pull-Up Resistor Format
94
Port 3
95
Connection of Pull-Up Resistors (Port 2)
95
Port 3 Operating Modes
96
Hardware Configuration
97
Block Diagram of P30 (Port 3)
97
Block Diagram of P31, and P34 through P37 (Port 3)
98
Block Diagram of P32 (Port 3)
99
Setting the I/O Mode and Control Mode
100
Block Diagram of P33 (Port 3)
100
Port 3 Mode Register Format
101
Port 3 Mode Control Register (PMC3) Format
101
Operation
102
Port Specified as an Output Port
102
Port Specified as an Input Port
102
Built-In Pull-Up Resistor
103
Port Specified as a Control Signal Input or Output
103
Pull-Up-Resistor-Option Register Format
103
Port 4
104
Connection of Pull-Up Resistors (Port 3)
104
Hardware Configuration
105
Setting the I/O Mode and Control Mode
105
Block Diagram of Port 4
105
Port 4 Operating Modes
105
Operation
106
Port Specified as an Output Port
106
Port Specified as an Input Port
106
Built-In Pull-Up Resistor
107
Pull-Up-Resistor-Option Register Format
107
Driving Leds Directly
108
Connection of Pull-Up Resistors (Port
108
Example of Driving an LED Directly
108
Port 5
109
Hardware Configuration
109
Setting the I/O Mode and Control Mode
109
Block Diagram of Port 5
109
Port 5 Mode Register Format
110
Operation
110
Port Specified as an Output Port
110
Port 5 Operating Modes
110
Built-In Pull-Up Resistor
111
Port Specified as an Input Port
111
Pull-Up-Resistor-Option Register Format
111
Driving Leds Directly
112
Example of Driving an LED Directly
112
Port 6
113
Port 6 Operating Modes
113
Hardware Configuration
114
Port 6 Control Pin Functions and the Required Operations
117
Setting the I/O Mode and Control Mode
117
Port 6 Mode Register Format
118
Operation
119
Port Specified as an Input Port
119
Port Specified as an Output Port
119
Built-In Pull-Up Resistor
120
Pull-Up-Resistor-Option Register Format
120
Note
121
Port 7
121
Hardware Configuration
121
Setting the I/O Mode and Control Mode
121
Notes
122
Operation
122
Port Specified as an Input Port
122
Chapter 6 Real-Time Output Function
124
Configuration and Function
124
Access to the Real-Time Output Port
126
Configuration of the Buffer Registers (P0H and P0L)
126
Port 0 Operating Modes and Operations Needed for the Port 0 Buffer Registers
127
Output Trigger for the Real-Time Output Port
128
Real-Time Output Control Register (Rtpc)
126
Real-Time Output Port Control Register (RTPC) Format
126
Real-Time Output Port Operation Timing
129
Real-Time Output Port Operation Timing (Controlling 2 Channels Independently of each Other)
130
Application Example
131
Real-Time Output Port Operation Timing
131
Contents of the Control Register for the Real-Time Output Function
132
Real-Time Output Function Setting Procedure
132
Interrupt Request Handling When the Real-Time Output Function Is Used
133
Notes
133
Chapter 7 Timer/Counter Units
136
Timer/Counter Types and Functions
136
Block Diagrams of Timer/Counter Units
137
Functions
138
Configuration
138
Intervals of 16-Bit Timer/Counter
138
Programmable Square Wave Output Setting Range of 16-Bit Timer/Counter
138
Pulse Width Measurement Range of 16-Bit Timer/Counter
138
Bit Timer/Counter Control Registers
140
Format of Timer Control Register 0 (TMC0)
141
Format of Capture/Compare Control Register 0 (CRC0)
141
Format of Timer Output Control Register (TOC)
142
Operation of 16-Bit Timer 0 (TM0)
143
Basic Operation of 16-Bit Timer 0 (TM0)
143
TM0 Cleared by a Coincidence with Compare Register (CR01)
144
Clear Operation When the CE0 Bit Is Reset to 0
145
Compare Register and Capture Register Operations
146
Compare Operation
146
TM0 Cleared after a Coincidence Is Detected
147
Basic Operation of Output Control Circuit
148
Capture Operation
148
Timer Output (TO0, TO1) Operation
149
Toggle Output Operation
150
TO0 and TO1 Toggle Output
150
PWM Pulse Output
151
PWM Output on TO0 and TO1
151
Example of PWM Output Using TM0
152
PWM Output When CR00 = FFFFH
152
Example of Rewriting Compare Register CR00
153
Example of PWM Output Signal with a 100% Duty Factor
153
Example of PPG Output Using TM0
154
PPG Output on TO0
154
PPG Output When CR00 = CR01
155
PPG Output When CR00 = 0000H
155
Example of PPG Output Signal with a 100% Duty Factor
156
Example of Rewriting Compare Register CR00
156
Example of PPG Output Period Made Longer
157
Sample Applications
158
Timing of Interval Timer Operation (1)
158
Setting of Control Registers for Interval Timer Operation (1)
159
Setting Procedure for Interval Timer Operation (1)
159
Interrupt Request Handling for Interval Timer Operation (1)
160
Timing of Interval Timer Operation (2)
160
Setting of Control Registers for Interval Timer Operation (2)
161
Setting Procedure for Interval Timer Operation (2)
161
Timing of Pulse Width Measurement
162
Setting of Control Registers for Pulse Width Measurement
162
Setting Procedure for Pulse Width Measurement
163
Interrupt Request Handling for Pulse Width Calculation
163
Example of PWM Signal Output by 16-Bit Timer/Counter
164
Setting of Control Registers for PWM Output Operation
164
Setting Procedure for PWM Output
165
Changing Duty Factor of PWM Output
165
Example of PPG Signal Output by 16-Bit Timer/Counter
166
Setting of Control Registers for PPG Output Operation
166
Setting Procedure for PPG Output
167
Changing Duty Factor of PPG Output
167
Functions
168
Intervals of 8-Bit Timer/Counter 1
168
Pulse Width Measurement Range of 8-Bit Timer/Counter 1
168
Configuration
169
Block Diagram of 8-Bit Timer/Counter 1
169
Bit Timer/Counter 1 Control Registers
172
Format of Timer Control Register 1 (TMC1)
172
Format of Prescaler Mode Register 1 (PRM1)
173
Format of Capture/Compare Control Register 1 (CRC1)
173
Operation of 8-Bit Timer 1 (TM1)
174
Basic Operation of 8-Bit Timer 1 (TM1)
174
TM1 Cleared by a Coincidence with Compare Register (Cr1M)
175
TM1 Cleared after Capture Operation
176
Clear Operation When the CE1 Bit Is Reset to 0
176
Compare Register and Capture/Compare Register Operations
177
Compare Operation
178
TM1 Cleared after a Coincidence Is Detected
178
Capture Operation
179
TM1 Cleared after Capture Operations
180
Sample Applications
180
Timing of Interval Timer Operation (1)
181
Setting of Control Registers for Interval Timer Operation (1)
181
Setting Procedure for Interval Timer Operation (1)
182
Interrupt Request Handling for Interval Timer Operation (1)
182
Timing of Interval Timer Operation (2)
183
Setting of Control Registers for Interval Timer Operation (2)
183
Setting Procedure for Interval Timer Operation (2)
184
Timing of Pulse Width Measurement
185
Setting of Control Registers for Pulse Width Measurement
186
Interrupt Request Handling for Pulse Width Calculation
187
Setting Procedure for Pulse Width Measurement
187
Functions
188
Intervals of 8-Bit Timer/Counter 2
188
Programmable Square Wave Output Setting Range of 8-Bit Timer/Counter 2
189
Pulse Width Measurement Range of 8-Bit Timer/Counter 2
189
Block Diagram of 8-Bit Timer/Counter 2
190
Clock Signals that Can be Applied to 8-Bit Timer/Counter 2
190
Bit Timer/Counter 2 Control Registers
192
Format of Timer Control Register 1 (TMC1)
192
Format of Prescaler Mode Register 1 (PRM1)
193
Configuration
190
Format of Capture/Compare Control Register 2 (CRC2)
194
Format of Timer Output Control Register (TOC)
195
Operation of 8-Bit Timer 2 (TM2)
196
Basic Operation of 8-Bit Timer 2 (TM2)
196
TM2 Cleared by a Coincidence with Compare Register (CR21)
197
TM2 Cleared after Capture Operation
197
Clear Operation When the CE2 Bit Is Reset to 0
198
External Event Counter Function
199
External Event Count Timing of 8-Bit Timer/Counter 2
200
Interrupt Request Generation Using External Event Counter
201
Example Where Input of no Valid Edge Cannot be Distinguished from Input of Only One Valid Edge with External Event Counter
202
How to Distinguish Input of no Valid Edge from Input of Only One Valid Edge with External Event Counter
202
One-Shot Timer Function
204
One-Shot Timer Operation
204
Compare Operation
205
Compare Register and Capture Register Operations
205
TM2 Cleared after a Coincidence Is Detected
206
Capture Operation
207
TM2 Cleared after Capture Operation
208
Basic Operation of Output Control Circuit
208
Timer Output (TO2, TO3) Operation
209
Toggle Output Operation
210
PWM Pulse Output
211
PWM Output
211
TO2 and TO3 Toggle Output
211
Example of PWM Output Using TM2
212
PWM Output on TO2 and TO3
212
PWM Output When CR20 = FFH
213
Example of Rewriting a Compare Register
213
Example of PWM Output Signal with a 100% Duty Factor
214
PPG Output
214
Example of PPG Output Using TM2
215
PPG Output on TO2
215
PPG Output When CR20 = CR21
216
PPG Output When CR20 = 00H
216
Example of Rewriting Compare Register CR20
217
Example of PPG Output Signal with a 100% Duty Factor
217
Example of PPG Output Period Made Longer
218
Sample Applications
219
Timing of Interval Timer Operation (1)
219
Setting of Control Registers for Interval Timer Operation (1)
220
Setting Procedure for Interval Timer Operation (1)
220
Interrupt Request Handling for Interval Timer Operation (1)
221
Timing of Interval Timer Operation (2)
221
Setting of Control Registers for Interval Timer Operation (2)
222
Setting Procedure for Interval Timer Operation (2)
223
Timing of Pulse Width Measurement
224
Setting of Control Registers for Pulse Width Measurement
224
Setting Procedure for Pulse Width Measurement
225
Example of PWM Signal Output by 8-Bit Timer/Counter 2
226
Interrupt Request Handling for Pulse Width Calculation
226
Setting of Control Registers for PWM Output Operation
227
Changing Duty Factor of PWM Output
228
Setting Procedure for PWM Output
228
Example of PPG Signal Output by 8-Bit Timer/Counter 2
228
Setting of Control Registers for PPG Output Operation
229
Changing Duty Factor of PPG Output
230
Setting Procedure for PPG Output
230
External Event Counter Operation
230
Setting of Control Registers for External Event Counter Operation
231
Setting Procedure for External Event Counter Operation
231
One-Shot Timer Operation
232
Setting of Control Registers for One-Shot Timer Operation
232
Setting Procedure for One-Shot Timer Operation
233
Procedure for Starting an Additional One-Shot Timer Operation
233
Configuration
234
Functions
234
Intervals of 8-Bit Timer/Counter 3
234
Block Diagram of 8-Bit Timer/Counter 3
235
Bit Timer/Counter 3 Control Registers
236
Format of Timer Control Register 0 (TMC0)
236
Format of Prescaler Mode Register 0 (PRM0)
236
Operation of 8-Bit Timer 3 (TM3)
237
Basic Operation of 8-Bit Timer 3 (TM3)
237
TM3 Cleared by a Coincidence with Compare Register (CR30)
238
Clear Operation When the CE3 Bit Is Reset to 0
238
Compare Register Operation
239
Timing of Interval Timer Operation
240
Sample Applications
240
Compare Operation
240
Common Notes on All Timers/Counters
241
Notes
241
Setting of Control Registers for Interval Timer Operation
241
Setting Procedure for Interval Timer Operation
241
Count Start Operation
243
Count Operation Stop
243
Timing of Count Operation Stop and Restart
243
Maximum Number of Wait States Inserted When Registers Associated with Timers/Counters Are Accessed
244
Example of PWM Output Signal with a 100% Duty Factor
245
Example of PPG Output Signal with a 100% Duty Factor
246
Example of PPG Output Period Made Longer
247
Notes on 16-Bit Timer/Counter
248
Notes on 8-Bit Timer/Counter 2
248
Example Where Input of no Valid Edge Cannot be Distinguished from Input of Only One Valid Edge with External Event Counter
249
Interrupt Request Generation Using External Event Counter
249
How to Distinguish Input of no Valid Edge from Input of Only One Valid Edge with External Event Counter
250
Notes on Using In-Circuit Emulators
251
Interrupt Generation Timing Change by an Erroneously Detected Edge
252
Chapter 8 A/D Converter
254
Configuration
254
Modes Generating the INTAD
254
Example of Capacitors Connected to the A/D Converter Pins
256
A/D Converter Mode Register (Adm)
257
A/D Converter Mode Register (ADM) Format
258
Basic A/D Converter Operation
259
Relations between Analog Input Voltages and A/D Conversion Results
260
Select Mode
261
Select Mode Operation Timing
261
A/D Conversion Time
261
Scan Mode
262
Scan Mode Operation Timing
262
A/D Conversion Activated by Software Start
263
Software-Started Select-Mode A/D Conversion
263
A/D Conversion Activated by Hardware Start
264
Software-Started Scan-Mode A/D Conversion
264
Example of Malfunction in a Hardware-Started A/D Conversion
265
Select-Mode A/D Conversion Started by Hardware
266
Interrupt Request from the A/D Converter
268
Setting for Use of An6 and An7
268
Notes
268
Conditions to Generate Interrupt Requests in each A/D Converter Operating Mode
268
Example of Capacitors Connected to the A/D Converter Pins
269
Example of Malfunction in a Hardware-Started A/D Conversion
270
Chapter 9 Asynchronous Serial Interface
272
Configuration
272
Asynchronous Serial Interface Control Register
274
Format of the Asynchronous Serial Interface Mode Register (ASIM)
275
Asynchronous Serial Interface Operations
276
Data Format
276
Parity Types and Operations
276
Format of the Asynchronous Serial Interface Status Register (ASIS)
276
Format of the Transmission/Reception Data at the Asynchronous Serial Interface
276
Transmission
277
Asynchronous Serial Interface Transmission Completion Interrupt Timing
277
Reception
278
Reception Error
278
Asynchronous Serial Interface Reception Completion Interrupt Timing
278
Reception Error Timing
279
Causes of Reception Errors
279
Baud Rate Generator
280
Baud Rate Generator Control Register (BRGC)
280
Configuration of the Baud Rate Generator for UART
280
Baud Rate Generator Clock Configuration
280
Baud Rate Generator Control Register (BRGC) Format
281
Operation of the Baud Rate Generator for UART
282
Example of Setting the BRGC Register When the Baud Rate Generator for UART Is Used
283
Baud Rate Setting
283
Example of Setting the Baud Rate When 8-Bit Timer/Counter 3 Is Used
285
Example of Setting the BRGC When the External Baud Rate Input (ASCK Is Used
287
Notes
287
Examples of Setting the BRGC When an External Baud Rate Input (ASCK) Is Used
287
Function
288
Configuration
288
Chapter 10 Clock Synchronous Serial Interface
288
Control Registers
291
Clock Synchronous Serial Interface Mode Register (CSIM)
291
Format of the Clock Synchronous Serial Interface Mode Register (CSIM)
291
Serial Bus Interface Control Register (SBIC)
292
Reading/Writing the Contents of the SBIC Register
292
Format of Serial Bus Interface Control Register (SBIC)
293
Operations in the Three-Wire Serial I/O Mode
294
Basic Operation Timing
294
Sample System Configuration with Three-Wire Serial I/O
294
Timing in Three-Wire Serial I/O Mode
295
Sample Connection with a Device Having Two-Wire Serial I/O
295
Operation When Only Transmission Is Permitted
296
Operation When Only Reception Is Permitted
296
Operation When both Transmission and Reception Are Permitted
296
Action to be Taken When the Serial Clock and Shift Become Asynchronous
297
Sbi Mode
297
Features of SBI
297
Sample Serial Bus Configured with SBI
298
Configuration of the Serial Interface
299
Pin Configuration
299
Detecting an Address Match
301
Control Registers in SBI Mode
301
Format of Clock Synchronous Serial Interface Mode Register (CSIM)
302
Format of SBIC Register
303
Configuration of Shift Register and Related Components
305
Sbi Communication and Signals
306
SBI Transfer Timing
306
Bus Release Signal
306
Address
307
Command Signal
307
Selecting a Slave Device by Its Address
307
Command and Data
308
Acknowledge Signal
308
Busy Signal (BUSY) and Ready Signal (READY)
309
Signals
309
Busy Signal and Ready Signal
309
Operation of RELT, CMDT, RELD, and CMDD
309
Signals in SBI Mode
309
ACKT Operation
310
ACKE Operations
310
ACKD Operations
311
BSYE Operation
312
Communication
316
Releasing the Busy State
316
Setting Wake-Up
316
Starting Transmission and Reception
316
Conditions Governing Release of BUSY
316
Notes
321
External Interrupt Mode Registers (Intm0, Intm1)
322
Chapter 11 Edge Detection Function
322
Pins P20 to P26 and Use of Detected Edge
322
Format of External Interrupt Mode Register 0 (INTM0)
323
Format of External Interrupt Mode Register 1 (INTM1)
324
Edge Detection on Pin P20
325
Edge Detection on Pins P21 to P26
326
Erroneously Detected Edges
326
Notes
327
Erroneously Detected Edges
328
Chapter 12 Interrupt Functions
330
Interrupt Request Handling Modes
330
Software Interrupt Request
331
Interrupt Request Sources
331
Nonmaskable Interrupt Request
332
Selecting an Interrupt Source
332
INTM1 Register Format
332
Interrupt Handling Control Registers
333
ADM Register Format
333
Interrupt Request Flag Register (IF0)
334
Interrupt Request Flag Register (IF0) Format
334
Flags for Interrupt Request Sources
334
Interrupt Mask Register (MK0)
335
Interrupt Service Mode Register (ISM0)
335
Priority Specification Flag Register (PR0)
335
Interrupt Service Mode Register (ISM0) Format
335
Interrupt Status Register (IST)
336
Interrupt Status Register (IST) Format
336
Interrupt Handling
337
Accepting Nonmaskable Interrupts
337
Accepting Software Interrupts
337
Program Status Word Format
337
Accepting an NMI Interrupt Request
338
Accepting Maskable Interrupts
340
Interrupt Handling Algorithm
341
Multiple-Interrupt Handling
342
Example of Handling an Interrupt Request When an Interrupt Is Already Being Handled
343
Interrupt Request and Macro Service Pending
345
Example of Handling Interrupts that Occur Simultaneously
345
Interrupt and Macro Service Operation Timing
346
Interrupt Request Generation and Acceptance
346
Interrupt Request Acceptance Processing Time
346
Macro Service Processing Time
347
Macro Service Function
348
Macro Service Outline
348
Differences between a Vectored Interrupt and Macro Service
348
Macro Service Types
349
Interrupts that Can Use a Macro Service
349
Macro Service Basic Operation
350
Macro Service Processing Sequence
350
Macro Service Control Register
351
Macro Service Control Word Configuration
351
Macro Service Type a
352
Macro Service Mode Register Format
352
Interrupt Requests that Can Specify Macro Service and Related Sfrs (Type A)
353
Illegal Write Access Conditions and Corresponding Operations
353
Flow of Data Transfer by Macro Service (Type A)
354
Type a Macro Service Channel
355
Type B Macro Service
356
Asynchronous Serial Reception
356
Flow of Data Transfer by Macro Service (Type B)
357
Type B Macro Service Channel
358
Parallel Data Input in Synchronization with an External Interrupt
359
Parallel Data Input Timing
359
Macro Service Type C
360
Interrupt Requests that Can Specify Macro Service and Sfrs (Type C)
360
Illegal Write Access Conditions and Corresponding Operations
360
Flow of Data Transfer by Macro Service (Type C)
361
Type C Macro Service Channel
363
Open-Loop Control for a Stepper Motor by the Real-Time Output Port
365
Data Transfer Control Timing
366
Four-Phase Stepping Motor with Phase 1 Excitation
367
Four-Phase Stepping Motor with Phases 1 and 2 Excitation
367
Notes
372
Illegal Write Access Conditions and Corresponding Operations
373
Chapter 13 Local Bus Interface Function
374
Memory Expansion Mode Register (MM)
375
Control Registers
375
Format of the Memory Expansion Mode Register (MM)
375
Programmable Wait Control Register (PW)
376
Memory Expansion Function
376
External Memory Expansion Function
376
Format of Programmable Wait Control Register (PW)
376
M-Byte Expansion Function
377
Read Timing
377
Write Timing
377
Accessing Expansion Data Memory
378
Memory Mapping with Expanded Memory
379
Conditions and Operations for Illegal Write Access
379
Data Memory Expansion for Μ PD78212 (When EA = L)
380
Data Memory Expansion for Μ PD78212 (When EA = H)
381
Data Memory Expansion for Μ PD78213 and Μ PD78214 (When EA = L)
382
Data Memory Expansion for Μ PD78214 and Μ PD78P214 (When EA = H)
383
Example of Connecting Memories
384
Example of Connecting Memories to Μ PD78214
385
Internal Rom High-Speed Fetch Function
386
Wait Function
386
Wait Control Space of Μ PD78212 (When EA = L)
387
Wait Control Space of Μ PD78212 (When EA = H)
388
Wait Control Space of Μ PD78213 and Μ PD78214 (When EA = L)
389
Wait Control Space of Μ PD78214 and Μ PD78P214
390
Read Timing of Programmable Wait Function
391
Write Timing of Programmable Wait Function
393
Timing When External Wait Signal Is Used
395
Pseudo Static Ram Refresh Function
396
Refresh Mode Register (RFM)
396
Format of Refresh Mode Register (RFM)
396
Pulse Refresh When Internal Memory Is Accessed
397
Operation
397
System Clock Frequency and Refresh Pulse Output Cycle When Pseudo Static RAM Is Used
397
Pulse Refresh When External Memory Is Accessed
398
Restoration Timing from Self-Refresh
399
Return from Self-Refresh
400
Example of Connecting Pseudo Static RAM
401
Example of Connecting Pseudo Static RAM to Μ PD78214
401
Notes
401
Conditions and Operations for Illegal Write Access
402
Glitch Observed on Pins A16 to A19 During Emulation
403
Return from Self-Refresh
403
Insufficient Address Hold Time During Emulation
403
Preventing Problems that May Occur During Emulation
404
Function Overview
406
Chapter 14 Standby Function
406
Transition Diagram for the Standby Modes
406
Standby Control Register (Stbc)
408
Halt Mode
408
Specifying HALT Mode and Operation States in HALT Mode
408
Configuration of the Standby Control Register (STBC)
408
Releasing HALT Mode
409
Sources for Releasing HALT Mode and Operations Performed after Release
409
Release of HALT Mode by a Maskable Interrupt Request
410
Stop Mode
411
Releasing STOP Mode
411
Specifying STOP Mode and Operation States in STOP Mode
411
Releasing STOP Mode with an NMI Signal
412
Example of Longer Oscillation Settling Time
412
Notes on Using STOP Mode
413
Example of Address Bus Arrangement
414
Example Address/Data Bus Arrangement
414
Example Arrangement for Analog Input Pin
415
Notes
415
Example of Longer Oscillation Settling Time
416
Reset Function
418
Chapter 15 Reset Function
418
Acceptance of the RESET Signal
418
Reset Operation at Power-On
418
Pin States During Reset and after Reset State Is Released
419
Hardware States after Reset
420
Timing Charts for Reset Operation
422
Note
422
Chapter 16 Application Examples
424
Open-Loop Control of Stepper Motors
424
Serial Communication with Multiple Devices
426
Example System Configuration Using the Serial Bus Interface
426
Example of Communication with SBI
427
Serial Bus Communication Timing
427
CHAPTER 17 PROGRAMMING for the Μ PD78P214
428
Operating Mode
428
Procedure for Writing into Prom
428
Operating Modes for PROM Programming
428
Timing Chart for PROM Write and Verify
429
Procedure for Reading from Prom
430
Write Operation Flowchart
430
PROM Read Timing Chart
431
Note
431
Chapter 18 Instruction Operations
432
Legend
432
Operand Field
432
Operation Field
433
Flag Field
434
List of Operations
435
Instruction Lists for each Addressing Type
445
Bit Instructions for each Addressing Type
445
Bit Instructions for each Addressing Type
446
Bit Manipulation Instructions for each Addressing Type
447
Call Instructions and Branch Instructions for each Addressing Type
448
Appendix A 78K/II Series Product List
450
Appendix B Development Tools
458
B.1 Hardware
460
B.2 Software
462
B.2.1 Language Processing Software
462
B.2.2 Software for the In-Circuit Emulator
464
B.2.3 Software for the PROM Programmer
466
B.3 Upgrading Other In-Circuit Emulators to 78K/II Series Level
467
B.3.1 Upgrading to IE-78240-R-A Level
467
B.3.2 Upgrading to IE-78240-R Level
468
B.3.3 Upgrading to IE-78210-R Level
469
Appendix C Software for Embedded Applications
470
C.1 Fuzzy Inference Development Support System
470
Appendix D Register Index
472
D.1 Register Index
472
D.2 Register Symbol Index
474
Appendix E Index
476
E.1 Index
476
E.2 Symbol Index
481
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