NEC V850E/IA4 Manuals

Manuals and User Guides for NEC V850E/IA4. We have 1 NEC V850E/IA4 manual available for free PDF download: User Manual

NEC V850E/IA4 User Manual (835 pages)

32-bit Single-Chip Microcontrollers

Brand: NEC | Category: Microcontrollers | Size: 7.98 MB

Table of Contents
8
Chapter 1 Introduction

16
- Overview
  16
- V850E/Ia3
  18
- Features (V850E/IA3)
  18
- Applications (V850E/IA3)
  20
- Ordering Information (V850E/IA3)
  20
- Pin Configuration (V850E/IA3)
  21
- Function Blocks (V850E/IA3)
  23
- V850E/Ia4
  26
- Features (V850E/IA4)
  26
- Applications (V850E/IA4)
  28
- Ordering Information (V850E/IA4)
  28
- Pin Configuration (V850E/IA4)
  29
- Function Blocks (V850E/IA4)
  32
Chapter 2 Pin Functions

35
Chapter 3 Cpu Function

47
- Features
  47
- CPU Register Set
  48
- Program Register Set
  49
- System Register Set
  50
- Operating Modes
  56
- Operating Mode Specification
  56
- Address Space
  57
- CPU Address Space
  57
- Image
  58
- Wraparound of CPU Address Space
  59
- Memory Map
  60
- Area
  61
- Recommended Use of Address Space
  65
- On-Chip Peripheral I/O Registers
  67
- Special Registers
  76
- System Wait Control Register (VSWC)
  80
- Cautions
  80
Chapter 4 Port Functions

81
- Features
  81
- V850E/Ia3
  81
- V850E/Ia4
  81
- Port Configuration
  82
- V850E/Ia3
  82
- V850E/Ia4
  83
- Port Configuration
  84
- Port 0
  89
- Port 1
  96
- Port 2 (V850E/IA4 Only)
  105
- Port 3
  111
- Port 4
  122
- Port 5 (V850E/IA4 Only)
  129
- Port 7
  134
- Port DL
  137
- Output Data and Port Read Value for each Setting
  141
- Port Register Settings When Alternate Function Is Used
  147
- Noise Eliminator
  153
- Cautions
  157
- Cautions on Setting Port Pins
  157
- Cautions on Bit Manipulation Instruction for Port N Register (Pn)
  158
Chapter 5 Clock Generator

159
- Overview
  159
- Configuration
  160
- Control Registers
  162
- PLL Function
  168
- Overview
  168
- Setting PLL Output Frequency
  168
- PLL Mode
  168
- Clock-Through Mode
  168
- Operation
  169
- Operation of each Clock
  169
- Operation Timing
  170
- Clock Monitor
  173
Chapter 6 16-Bit Timer/Event Counter P (Tmp)

174
Chapter 7 16-Bit Timer/Event Counter Q (Tmq)

274
CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/ GENERAL-PURPOSE TIMER (TIMER Enc1N)

386
- Functions
  386
- Features
  386
- Configuration
  388
- Control Registers
  391
- Operation
  403
- Operation in General-Purpose Timer Mode
  403
- Operation in UDC Mode
  405
- Supplementary Description of Internal Operation
  411
- Clearing of Count Value in UDC Mode B
  411
- Transfer Operation
  412
- Interrupt Request Signal Output Upon Compare Match
  413
- Tm1Ubdn Flag (Bit 0 of Status1N Register) Operation
  413
Chapter 9 16-Bit Interval Timer M (Tmm)

414
- Overview
  414
- Configuration
  415
- Control Register
  416
- Operation
  417
- Interval Timer Mode
  417
- Cautions
  421
Chapter 10 Motor Control Function

422
- Functional Overview
  422
- Configuration
  423
- Control Registers
  427
- Operation
  440
- System Outline
  440
- Dead-Time Control (Generation of Negative-Phase Wave Signal)
  445
- Interrupt Culling Function
  452
- Operation to Rewrite Register with Transfer Function
  459
- Tmpn Tuning Operation for A/D Conversion Start Trigger Signal Output
  477
- A/D Conversion Start Trigger Output Function
  481
Chapter 11 Watchdog Timer Functions

486
- Functions
  486
- Configuration
  486
- Control Registers
  487
- Operation
  488
- Caution
  488
Chapter 12 A/D Converters 0 and 1

489
Chapter 13 A/D Converter 2

548
- Features
  548
- Configuration
  549
- Control Registers
  552
- Operation
  561
- Basic Operation
  561
- Buffer Mode and Operation Mode
  562
- Operation Timing
  564
- Internal Equivalent Circuit
  568
- How to Read A/D Converter Characteristics Table
  568
- R> 13.7 Cautions
  569
- Writing to the ADA2CTL1 and ADA2CTL3 Registers During Conversion
  569
- Conflict with Timing of Storing Data in the Conversion Result Register
  569
Chapter 14 Asynchronous Serial Interface a (Uarta)

571
- Mode Switching between UARTA1 and CSIB1
  571
- Features
  572
- Configuration
  573
- Control Registers
  575
- Interrupt Request Signals
  580
- Operation
  581
- Data Format
  581
- UART Transmission
  583
- Continuous Transmission Procedure
  584
- UART Reception
  586
- Reception Errors
  587
- Parity Types and Operations
  588
- Receive Data Noise Filter
  589
- Dedicated Baud Rate Generator
  590
- Cautions
  597
Chapter 15 Clocked Serial Interface B (Csib)

598
Chapter 16 Dma Functions (Dma Controller)

643
- Features
  643
- Configuration
  644
- Control Registers
  645
- DMA Source Address Registers 0 to 3 (DSA0 to DSA3)
  645
- DMA Destination Address Registers 0 to 3 (DDA0 to DDA3)
  647
- DMA Transfer Count Registers 0 to 3 (DBC0 to DBC3)
  649
- DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3)
  650
- DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3)
  652
- DMA Trigger Factor Registers 0 to 3 (DTFR0 to DTFR3)
  654
- Transfer Modes
  658
- Single Transfer Mode
  658
- Single-Step Transfer Mode
  660
- Block Transfer Mode
  661
- Transfer Types
  662
- 2-Cycle Transfer
  662
- Transfer Target
  662
- Transfer Type and Transfer Target
  662
- DMA Channel Priorities
  662
- Next Address Setting Function
  663
- DMA Transfer Start Factors
  664
- Forcible Termination
  665
- Times Related to DMA Transfer
  666
- Cautions
  666
- DMA Transfer End
  667
Chapter 17 Interrupt/Exception Processing Function

668
- Features
  668
- Non-Maskable Interrupts
  672
- Operation
  673
- Restore
  675
- Non-Maskable Interrupt Status Flag (NP)
  676
- Maskable Interrupts
  677
- Operation
  677
- Restore
  679
- Priorities of Maskable Interrupts
  680
- Interrupt Control Registers (Xxicn)
  684
- Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
  688
- In-Service Priority Register (ISPR)
  690
- Maskable Interrupt Status Flag (ID)
  691
- External Interrupt Request Input Pins (INTP0 to INTP7)
  692
- Noise Elimination
  692
- Edge Detection
  693
- Software Exception
  695
- Operation
  695
- Restore
  696
- Exception Status Flag (EP)
  697
- Exception Trap
  698
- Illegal Opcode Definition
  698
- Debug Trap
  700
- Multiple Interrupt Servicing Control
  702
- Interrupt Response Time of CPU
  704
- Periods in Which CPU Does Not Acknowledge Interrupts
  705
- Caution
  705
Chapter 18 Standby Function

706
- Overview
  706
- Control Registers
  708
- HALT Mode
  710
- Setting and Operation Status
  710
- Releasing HALT Mode
  710
- IDLE Mode
  712
- Setting and Operation Status
  712
- Releasing IDLE Mode
  712
- STOP Mode
  714
- Setting and Operation Status
  714
- Releasing STOP Mode
  714
- Securing Oscillation Stabilization Time
  716
Chapter 19 Reset Functions

717
- Overview
  717
- Configuration
  717
- Control Register
  718
- Operation
  719
Chapter 20 Rom Correction Function

722
- Overview
  722
- Control Registers
  723
- ROM Correction Operation and Program Flow
  725
Chapter 21 On-Chip Debug Function (On-Chip Debug Unit)

727
- Functional Overview
  727
- On-Chip Debug Unit Type
  727
- Debug Function
  727
- ROM Security Function
  729
- Selecting On-Chip Debug Function and Port Function (Including Alternate Functions)731
  731
- Connection with On-Chip Debug Emulator
  732
- KEL Connector
  733
- Cautions
  737
Chapter 22 Flash Memory

738
- Features
  738
- Memory Configuration
  739
- Functional Overview
  740
- Rewriting by Dedicated Flash Memory Programmer
  744
- Programming Environment
  744
- Communication Mode
  745
- Flash Memory Control
  749
- Selection of Communication Mode
  750
- Communication Commands
  751
- Pin Connection
  752
- Rewriting by Self Programming
  759
- Overview
  759
- Features
  760
- Standard Self Programming Flow
  761
- Flash Functions
  762
- Pin Processing
  762
- Internal Resources Used
  763
Chapter 23 Electrical Specifications (V850E/Ia3)

764
Chapter 24 Electrical Specifications (V850E/Ia4)

782
Chapter 25 Package Drawings

801
Chapter 26 Recommended Soldering Conditions

804
Appendix A Cautions

805
Appendix B Register Index

806
Appendix C Instruction Set List

815
- Conventions
  815
- Instruction Set (in Alphabetical Order)
  818
Appendix D Revision History

825
- Major Revisions in this Edition
  825
- Revision History up to Previous Edition
  828

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NEC V850E/IA4 Manuals

NEC V850E/IA4 User Manual (835 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Function

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 16-Bit Timer/Event Counter P (Tmp)

Chapter 7 16-Bit Timer/Event Counter Q (Tmq)

CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/ GENERAL-PURPOSE TIMER (TIMER Enc1N)

Chapter 9 16-Bit Interval Timer M (Tmm)

Chapter 10 Motor Control Function

Chapter 11 Watchdog Timer Functions

Chapter 12 A/D Converters 0 and 1

Chapter 13 A/D Converter 2

Chapter 14 Asynchronous Serial Interface a (Uarta)

Chapter 15 Clocked Serial Interface B (Csib)

Chapter 16 Dma Functions (Dma Controller)

Chapter 17 Interrupt/Exception Processing Function

Chapter 18 Standby Function

Chapter 19 Reset Functions

Chapter 20 Rom Correction Function

Chapter 21 On-Chip Debug Function (On-Chip Debug Unit)

Chapter 22 Flash Memory

Chapter 23 Electrical Specifications (V850E/Ia3)

Chapter 24 Electrical Specifications (V850E/Ia4)

Chapter 25 Package Drawings

Chapter 26 Recommended Soldering Conditions

Appendix A Cautions

Appendix B Register Index

Appendix C Instruction Set List

Appendix D Revision History

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