NEC V850ES/SG2 mPD703263Y Manuals

Manuals and User Guides for NEC V850ES/SG2 mPD703263Y. We have 1 NEC V850ES/SG2 mPD703263Y manual available for free PDF download: Preliminary User's Manual

NEC V850ES/SG2 mPD703263Y Preliminary User's Manual (827 pages)

32-Bit Single-Chip Microcontroller

Brand: NEC | Category: Microcontrollers | Size: 3.79 MB

Table of Contents
8
Chapter 1 Introduction

32
- General
  32
- Features
  35
- Application Fields
  36
- Ordering Information
  37
- Pin Configuration (Top View)
  39
- Function Block Configuration
  44
- Internal Block Diagram
  44
- Internal Units
  45
Chapter 2 Pin Functions

48
Chapter 3 Cpu Function

70
- Features
  70
- CPU Register Set
  71
- Program Register Set
  72
- System Register Set
  73
- Operation Modes
  79
- Address Space
  80
- CPU Address Space
  80
- Image
  81
- Wraparound of CPU Address Space
  82
- Memory Map
  83
- Areas
  85
- Recommended Use of Address Space
  93
- Peripheral I/O Registers
  96
- Programmable Peripheral I/O Registers
  107
- Special Registers
  108
- Notes
  112
Chapter 4 Port Functions

114
- Features
  114
- Basic Port Configuration
  114
- Port Configuration
  115
- Notes on Setting Port Pins
  115
- Port 0
  116
- Port 1
  121
- Port 3
  123
- Port 4
  131
- Port 5
  135
- Port 7
  140
- Port 9
  143
- Port CM
  153
- Port CT
  156
- Port DH
  159
- Port DL
  162
- Port Function Operation
  176
- Write to I/O Ports
  176
- Read from I/O Port
  176
- I/O Port Calculation
  176
Chapter 5 Bus Control Function

177
- Features
  177
- Bus Control Pins
  178
- Pin Status When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
  178
- Pin Status in each Operation Mode
  178
- Memory Block Function
  179
- External Bus Interface Mode Control Function
  180
- Bus Access
  181
- Number of Clocks for Access
  181
- Bus Size Setting Function
  181
- Access by Bus Size
  182
- Wait Function
  188
- Programmable Wait Function
  188
- External Wait Function
  189
- Relationship between Programmable Wait and External Wait
  190
- Programmable Address Wait Function
  191
- Idle State Insertion Function
  192
- Bus Hold Function
  193
- Functional Outline
  193
- Bus Hold Procedure
  194
- Operation in Power Save Mode
  194
- Bus Priority
  195
- Boundary Operation Conditions
  195
- Program Space
  195
- Data Space
  195
- Bus Timing
  196
- Multiplexed Bus
  196
- Separate Bus
  205
Chapter 6 Clock Generation Function

214
- Overview
  214
- Configuration
  215
- Control Registers
  217
- Operation
  222
- Operation of each Clock
  222
- Clock Output Function
  222
- PLL Function
  223
- Overview
  223
- Control Registers
  223
- Usage
  227
Chapter 7 16-Bit Timer/Event Counter P

228
- Features
  228
- Function Outline
  228
- Configuration
  229
- Control Registers
  233
- Operation
  239
- Anytime Write and Reload
  239
- Interval Timer Mode (Tpnmd2 to Tpnmd0 = 000)
  244
- External Event Count Mode (Tpnmd2 to Tpnmd0 = 001)
  247
- External Trigger Pulse Mode (Tpnmd2 to Tpnmd0 = 010)
  251
- One-Shot Pulse Mode (Tpnmd2 to Tpnmd0 = 011)
  254
- PWM Mode (Tpnmd2 to Tpnmd0 = 110)
  257
- Free-Running Mode (Tpnmd2 to Tpnmd0 = 101)
  262
- Pulse Width Measurement Mode (Tpnmd2 to Tpnmd0 = 110)
  268
Chapter 8 16-Bit Timer/Event Counter Q

270
- Features
  270
- Function Outline
  270
- Configuration
  271
- Control Registers
  276
- Operation
  282
- Anytime Write and Reload
  282
- Interval Timer Mode (TQ0MD2 to TQ0MD0 = 000)
  287
- External Event Count Mode (TQ0MD2 to TQ0MD0 = 001)
  290
- External Trigger Pulse Mode (TQ0MD2 to TQ0MD0 = 010)
  294
- One-Shot Pulse Mode (TQ0MD2 to TQ0MD0 = 011)
  297
- PWM Mode (TQ0MD2 to TQ0MD0 = 110)
  300
- Free-Running Mode (TQ0MD2 to TQ0MD0 = 101)
  305
- Pulse Width Measurement Mode (TQ0MD2 to TQ0MD0 = 110)
  312
Chapter 9 16-Bit Interval Timer M

314
- Outline
  314
- Configuration
  315
- Control Register
  316
- Operation
  317
- Interval Timer Mode
  317
- Clock Generator and Clock Enable Timing
  317
Chapter 10 Real-Time Output Function (Rto)

318
- Function
  318
- Configuration
  319
- Control Registers
  320
- Operation
  322
- Usage
  323
- Cautions
  323
Chapter 11 Watch Timer Functions

324
- Functions
  324
- Configuration
  326
- Control Registers
  327
- Operation
  329
- Operation as Watch Timer
  329
- Operation as Interval Timer
  329
- Cautions
  330
- Prescaler 3
  331
- Control Register
  331
- Generation of Watch Timer Count Clock
  332
Chapter 12 Functions of Watchdog Timer 2

333
- Functions
  333
- Configuration
  334
- Control Registers
  334
- Operation
  338
Chapter 13 A/D Converter

340
- Functions
  340
- Configuration
  342
- Control Registers
  344
- Operation
  352
- Basic Operation
  352
- Trigger Mode
  354
- Operation Mode
  356
- Power-Fail Compare Mode
  362
- Cautions
  368
- How to Read A/D Converter Characteristics Table
  371
Chapter 14 D/A Converter

375
- Functions
  375
- Configuration
  375
- Control Registers
  376
- Operation
  378
- Operation in Normal Mode
  378
- Operation in Real-Time Output Mode
  378
- Cautions
  379
Chapter 15 Asynchronous Serial Interface a (Uarta)

380
- Mode Switching of UARTA and Other Serial Interfaces
  380
- CSIB4 and UARTA0 Mode Switching
  380
- UARTA2 and I 2 C00 Mode Switching
  381
- UARTA1 and I 2 C02 Mode Switching
  382
- Features
  383
- Configuration
  384
- Control Registers
  386
- Interrupt Request Signals
  393
- Operation
  394
- Data Format
  394
- SBF Transmission/Reception Format
  396
- SBF Transmission
  398
- SBF Reception
  399
- UART Transmission
  400
- Continuous Transmission Procedure
  401
- UART Reception
  403
- Reception Error
  404
- Parity Types and Operations
  405
- Receive Data Noise Filter
  406
- Dedicated Baud Rate Generator
  407
Chapter 16 3-Wire Variable-Length Serial I/O (Csib)

415
- Mode Switching of CSIB and Other Serial Interfaces
  415
- CSIB4 and UARTA0 Mode Switching
  415
- CSIB0 and I 2 C01 Mode Switching
  417
- Features
  418
- Configuration
  418
- Control Registers
  421
- Operation
  427
- Single Transfer (Master Mode, Transmission/Reception Mode)
  427
- Single Transfer Mode (Master Mode, Reception Mode)
  428
- Continuous Mode (Master Mode, Transmission/Reception Mode)
  429
- Continuous Mode (Master Mode, Reception Mode)
  430
- Continuous Reception Mode (Error)
  431
- Continuous Mode (Slave Mode, Transmission/Reception Mode)
  432
- Continuous Mode (Slave Mode, Reception Mode)
  433
- Clock Timing
  434
- Output Pins
  436
- Operation Flow
  437
- Baud Rate Generator
  443
- Baud Rate Generation
  444
Chapter 17 I C Bus

445
- Mode Switching of I
  445
- C Bus and Other Serial Interfaces
  445
- UARTA2 and I 2 C00 Mode Switching
  445
- CSIB0 and I C01 Mode Switching
  446
- UARTA1 and I C02 Mode Switching
  447
- Features
  448
- Configuration
  451
- Control Registers
  453
- I C Bus Mode Functions
  468
- Pin Configuration
  468
- I C Bus Definitions and Control Methods
  469
- Start Condition
  469
- Addresses
  470
- Transfer Direction Specification
  471
- Acknowledge Signal (ACK)
  472
- Stop Condition
  473
- Wait Signal (WAIT)
  474
- I C Interrupt Request Signals (Intiicn)
  476
- Master Device Operation
  476
- Slave Device Operation (When Receiving Slave Address Data (Matches with Address))
  479
- Slave Device Operation (When Receiving Extension Code)
  483
- Operation Without Communication
  487
- Arbitration Loss Operation (Operation as Slave after Arbitration Loss)
  487
- Operation When Arbitration Loss Occurs (no Communication after Arbitration Loss)
  489
- Interrupt Request Signal (Intiicn) Generation Timing and Wait Control
  494
- Address Match Detection Method
  495
- Error Detection
  495
- Extension Code
  495
- Arbitration
  496
- Wakeup Function
  497
- Communication Reservation
  498
- When Communication Reservation Function Is Enabled (Iicrsvn Bit of Iicfn Register = 0)
  498
- When Communication Reservation Function Is Disabled (Iicrsvn Bit of Iicfn Register = 1)
  502
- Cautions
  503
- Communication Operations
  504
- Master Operation 1
  504
- Master Operation 2
  506
- Slave Operation
  507
- Timing of Data Communication
  508
CHAPTER 18 Iebus CONTROLLER

515
- Functions
  515
- Communication Protocol of Iebus
  515
- Determination of Bus Mastership (Arbitration)
  516
- Communication Mode
  516
- Communication Address
  516
- Broadcast Communication
  517
- Transfer Format of Iebus
  517
- Transfer Data
  527
- Bit Format
  529
- Configuration
  530
- Control Registers
  532
- Interrupt Operations of Iebus Controller
  562
- Interrupt Control Block
  562
- Example of Identifying Interrupt
  564
- Interrupt Source List
  567
- Communication Error Source Processing List
  568
- Interrupt Request Signal Generation Timing and Main CPU Processing
  570
- Master Transmission
  570
- Master Reception
  572
- Slave Transmission
  574
- Slave Reception
  576
- Interval of Occurrence of Interrupt Request Signal for Iebus Control
  578
Chapter 19 Can Controller

582
- Outline
  582
- Features
  582
- Overview of Functions
  583
- Configuration
  584
- CAN Protocol
  585
- Frame Format
  585
- Frame Types
  586
- Data Frame and Remote Frame
  586
- Error Frame
  594
- Overload Frame
  595
- Functions
  596
- Arbitration
  596
- Bit Stuffing
  597
- Multi Masters
  597
- Multi Cast
  597
- Sleep Mode/Stop Function
  597
- Error Control Function
  598
- Baud Rate Control Function
  601
- State Transition Chart
  604
- Connection with Target System
  607
- Internal Registers of CAN Controller
  608
- CAN Controller Configuration
  608
- Register Access Type
  609
- Control Bits of Message Buffers
  626
- Control Registers
  629
- Bit Set/Clear Function
  663
- CAN Controller Initialization
  665
- Initialization of CAN Module
  665
- Initialization of Message Buffer
  665
- Transition from INIT Mode in Operational Mode
  666
- Resetting of CAN Module Error Counter C0ERC in INIT Mode
  667
- Message Reception
  668
- Receive History List Function
  668
- Mask Function
  672
- Multi Buffer Receive Block Function
  673
- Remote Frame Reception
  673
- Message Transmission
  675
- Transmit History List Function
  677
- Automatic Block Transmission (ABT)
  680
- Transmission Request Abort Process
  680
- Power Saving Modes
  682
- CAN Sleep Mode
  682
- CAN Stop Mode
  682
- Interrupt Function
  684
- Interrupts Generated by CAN Module
  684
- Diagnosis Functions and Special Operational Modes
  685
- Receive-Only Mode
  685
- Single-Shot Mode
  686
- Self-Test Mode
  687
- Time Stamp Function
  688
- Basic Time Stamp Function
  688
- Rules for Setting Baud Rate
  689
- Operation of CAN Controller
  693
Chapter 20 Dma Functions (Dma Controller)

715
- Features
  715
- Configuration
  716
- Control Registers
  717
- DMA Source Address Registers 0 to 3 (DSA0 to DSA3)
  717
- DMA Destination Address Registers 0 to 3 (DDA0 to DDA3)
  718
- DMA Byte Count Registers 0 to 3 (DBC0 to DBC3)
  719
- DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3)
  720
- DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3)
  721
- DMA Trigger Factor Registers 0 to 3 (DTFR0 to DTFR3)
  722
- DMA Bus States
  725
- Types of Bus States
  725
- DMAC Bus Cycle State Transition
  726
- Transfer Mode
  727
- Single Transfer Mode
  727
- Transfer Types
  727
- Two-Cycle Transfer
  727
- Transfer Object
  728
- External Bus Cycles During DMA Transfer (Two-Cycle Transfer)
  728
- DMA Channel Priorities
  729
- DMA Transfer Start Factors
  729
- DMA Transfer End
  729
- DMA Transfer End Interrupt
  729
- Terminal Count Output Upon DMA Transfer End
  729
- Precautions
  730
- Interrupt Factors
  731
Chapter 21 Crc Function

732
- Functions
  732
- Configuration
  732
- Control Registers
  733
- Operation
  734
- CRC Operation Circuit Operation Example
  734
- Operation Circuit Configuration
  735
- Usage Method
  736
Chapter 22 Interrupt/Exception Processing Function

738
- Features
  738
- Non-Maskable Interrupts
  742
- Operation
  744
- Restore
  745
- NP Flag
  746
- Eliminating Noise on NMI Pin
  746
- Function to Detect Edge of NMI Pin
  746
- Maskable Interrupts
  748
- Operation
  748
- Restore
  750
- Priorities of Maskable Interrupts
  751
- Interrupt Control Register (Xxicn)
  755
- Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
  758
- In-Service Priority Register (ISPR)
  759
- ID Flag
  760
- Watchdog Timer Mode Register 2 (WDTM2)
  761
- Eliminating Noise on INTP0 to INTP7 Pins
  761
- Function to Detect Edge of INTP0 to INTP7 Pins
  761
- Software Exception
  766
- Operation
  766
- Restore
  767
- EP Flag
  768
- Exception Trap
  769
- Illegal Opcode Definition
  769
- Debug Trap
  771
- Interrupt Acknowledge Time of CPU
  773
- Periods in Which Interrupts Are Not Acknowledged by CPU
  774
Chapter 23 Key Interrupt Function

775
- Function
  775
- Control Register
  776
Chapter 24 Standby Function

777
- Overview
  777
- HALT Mode
  780
- Setting and Operation Status
  780
- Releasing HALT Mode
  780
- IDLE1 Mode
  782
- Setting and Operation Status
  782
- Releasing IDLE1 Mode
  782
- IDLE2 Mode
  784
- Setting and Operation Status
  784
- Releasing IDLE2 Mode
  784
- Securing Setup Time When Releasing IDLE2 Mode
  786
- Software STOP Mode
  787
- Setting and Operation Status
  787
- Releasing Software STOP Mode
  787
- Securing Oscillation Stabilization Time When Releasing Software STOP Mode
  789
- Subclock Operation Mode
  790
- Setting and Operation Status
  790
- Releasing Subclock Operation Mode
  790
- Sub-IDLE Mode
  792
- Setting and Operation Status
  792
- Releasing Sub-IDLE Mode
  792
- Control Registers
  794
Chapter 25 Reset Functions

795
- Overview
  795
- Registers to Check Reset Source
  795
- Operation
  796
- Reset Operation Via RESET Pin
  796
- Reset Operation by WDT2RES Signal
  798
- Reset Operation by Low-Voltage Detector
  800
- Clock Monitor
  804
Chapter 26 Regulator

807
- Outline
  807
- Operation
  808
Chapter 27 Rom Correction Function

809
- Overview
  809
- Control Registers
  810
- ROM Correction Operation and Program Flow
  812
Chapter 28 Flash Memory

814
- Features
  815
- Erasure Unit
  815
- Writing with Flash Programmer
  816
- Programming Environment
  816
- Communication Mode
  817
- Pin Connection
  819
- FLMD0 Pin
  819
- FLMD1 Pin
  820
- Serial Interface Pin
  821
- RESET Pin
  823
- Port Pins (Including NMI)
  823
- Other Signal Pins
  823
- Power Supply
  823
- Programming Method
  824
- Flash Memory Control
  824
- Flash Memory Programming Mode
  825
- Selection of Communication Mode
  826
- Communication Command
  827

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NEC V850ES/SG2 mPD703263Y Manuals

NEC V850ES/SG2 mPD703263Y Preliminary User's Manual (827 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Function

Chapter 4 Port Functions

Chapter 5 Bus Control Function

Chapter 6 Clock Generation Function

Chapter 7 16-Bit Timer/Event Counter P

Chapter 8 16-Bit Timer/Event Counter Q

Chapter 9 16-Bit Interval Timer M

Chapter 10 Real-Time Output Function (Rto)

Chapter 11 Watch Timer Functions

Chapter 12 Functions of Watchdog Timer 2

Chapter 13 A/D Converter

Chapter 14 D/A Converter

Chapter 15 Asynchronous Serial Interface a (Uarta)

Chapter 16 3-Wire Variable-Length Serial I/O (Csib)

Chapter 17 I C Bus

CHAPTER 18 Iebus CONTROLLER

Chapter 19 Can Controller

Chapter 20 Dma Functions (Dma Controller)

Chapter 21 Crc Function

Chapter 22 Interrupt/Exception Processing Function

Chapter 23 Key Interrupt Function

Chapter 24 Standby Function

Chapter 25 Reset Functions

Chapter 26 Regulator

Chapter 27 Rom Correction Function

Chapter 28 Flash Memory

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