Page 1 Preliminary User’s Manual V850/SA1 32-/16-Bit Single-Chip Microcontrollers Hardware µ µ µ µ PD703015 µ µ µ µ PD703015Y µ µ µ µ PD70F3017 µ µ µ µ PD70F3017Y Document No. U12768EJ2V0UM00 (2nd edition) Date Published June 1998 N CP(K) © 1997 Printed in Japan...
Page 2 [MEMO]...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. V850 Family, V850/SA1 is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries.
Page 4 The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability •...
Page 6 Major Revisions in This Edition p.23 121-pin fine pitch BGA has been added to 1.4 Ordering Information p.24 121-pin fine pitch BGA has been added to 1.5 Pin Configuration (Top View). p.57 The explanation of EP bit has been modified in 3.2.2 (2) Program status word (PSW). p.71 The description has been modified in 3.4.6 (2) memory address output mode register (MAM).
Page 7 INTRODUCTION This manual is intended for users who wish to understand the functions of the V850/SA1 ( µ PD703015, Readers 703015Y, 70F3017, 70F3017Y) and design application systems using these products. Purpose This manual is intended to help users understand the hardware functions described following the organization below.
Page 8 Related documents The related documents indicted in this publication may included preliminary versions. However, preliminary versions are not marked as such. Related documents for V850/SA1 Document Name Document No. V850 Family Architecture User’s Manual U10243E V850 Family Instruction Table U10229E µ...
Page 9: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION ......................General..............................Features ..............................Application Fields ..........................Ordering Information ........................... Pin Configuration (Top View) ......................Function Blocks ........................... 1.6.1 Internal Block Diagram........................ 1.6.2 On-chip units ..........................CHAPTER 2 PIN FUNCTIONS......................List of Pin Functions..........................Pin States.............................. Description of Pin Functions ......................
Page 10 4.3.2 Bus width............................. Memory Block Function........................Wait Function............................4.5.1 Programmable wait function ......................4.5.2 External wait function ........................4.5.3 Relations between programmable wait and external wait ............Idle State Insertion Function ....................... Bus Hold Function..........................4.7.1 Outline of function ........................4.7.2 Bus hold procedure ........................
Page 11 Periods Where Interrupt is Not Acknowledged ................. 130 CHAPTER 6 CLOCK GENERATION FUNCTION ................131 General..............................131 Composition ............................131 Clock Output Function......................... 132 6.3.1 Control registers.......................... 132 Power Saving Functions........................135 6.4.1 General ............................135 6.4.2 HALT mode ..........................136 6.4.3 IDLE mode ..........................
Page 12 8.4.2 Operation as interval timer ......................199 CHAPTER 9 WATCHDOG TIMER ...................... 201 Functions .............................. 201 Configuration ............................203 Watchdog Timer Control Register ...................... 203 Operation .............................. 206 9.4.1 Operating as watchdog timer ...................... 206 9.4.2 Operating as interval timer ......................207 Standby Function Control Register ....................
Page 13 11.4.1 Basic operation ......................... 308 11.4.2 Input voltage and conversion result ..................310 11.4.3 A/D converter operation mode ....................311 11.5 Notes on Using A/D Converter......................314 CHAPTER 12 DMA FUNCTIONS ....................... 317 12.1 Functions .............................. 317 12.2 Transfer Completion Interrupt Request ..................... 317 12.3 Control Registers ..........................
Page 14 16.5.1 V pin ............................362 16.5.2 Serial interface pin........................362 16.5.3 RESET pin..........................364 16.5.4 Port pin ............................364 16.5.5 Other signal pins ........................364 16.5.6 Power supply..........................364 16.6 Programming Method .......................... 365 16.6.1 Flash memory control........................ 365 16.6.2 Flash memory programming mode.................... 365 16.6.3 Selection of communication mode ....................
Page 15 LIST OF FIGURES (1/5) Fig. No. Title Page CPU Address Space..........................Image on Address Space ........................Memory Map............................Internal ROM Area (with Mask ROM Internal Version) ................External Memory Area (when expanded to 64 K, 256 K, or 1 Mbytes)........... External Memory Area (when expanded to 4 Mbytes)................
Page 16 LIST OF FIGURES (2/5) Fig. No. Title Page 7-11 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register ................7-12 Configuration for Pulse Width Measurement with Free Running Counter ..........7-13 Timing of Pulse Width Measurement with Free Running Counter and One Capture Register (with both edges specified) ................
Page 17 LIST OF FIGURES (3/5) Fig. No. Title Page Format of Oscillation Stabilization Time Selection Register (OSTS) ............Format of Watchdog Timer Clock Selection Register (WDCS)............... Format of Watchdog Timer Mode Register (WDTM) ................Format of Oscillation Stabilization Time Selection Register (OSTS) ............10-1 Block Diagram of 3-wire Serial I/O......................
Page 18 LIST OF FIGURES (4/5) Fig. No. Title Page 11-1 Block Diagram of A/D Converter......................11-2 Format of A/D Converter Mode Register (ADM) ..................11-3 Format of Analog Input Channel Specification Register (ADS) ............. 11-4 Basic Operation of A/D Converter......................11-5 Relation between Analog Input Voltage and A/D Conversion Result ............
Page 19 LIST OF FIGURES (5/5) Fig. No. Title Page 14-23 Format of Port 9 Mode Register (PM9)....................14-24 Format of Port 10 (P10) .......................... 14-25 Format of Port 10 Mode Register (PM10)....................14-26 Format of Pull-up Resistance Option Register 10 (PU10) ..............14-27 Format of Port 10 Function Register (PF10)...................
Page 20 LIST OF TABLES Table. No. Title Page Program Registers ..........................System Register Numbers ........................Interrupt/Exception Table........................Bus Priority............................. Interrupt Source List..........................Operating Statuses during HALT Mode ....................Operating Statuses during IDLE Mode ....................Operating States during Software STOP Mode ..................Configuration of Timer 0 ........................
Page 21: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850/SA1 is a product in NEC’s V850 Family of single-chip microcontrollers designed for real-time control operations. This chapter presents a brief overview of the V850/SA1. 1.1 General The V850/SA1 is a 32-/16-bit single-chip microcontroller that includes the V850 Family’s CPU core, and peripheral functions such as ROM/RAM, a timer/counter, a serial interface, an A/D converter, a timer, and DMA, controller.
Page 22 CHAPTER 1 INTRODUCTION { External bus interface 16-bit data bus (address/data multiplex) Address bus: separate output enabled Bus hold function External wait function µ PD703015, 703015Y (ROM: 128 Kbytes, RAM: 4 Kbytes) { On-chip memory µ PD70F3017, 70F3017Y (Flash memory: 256 Kbytes, RAM: 8 Kbytes) { Interrupts and exceptions External interrupts: 8 (including NMIs) Internal interrupts: 30 sources...
Page 23: Application Fields
CHAPTER 1 INTRODUCTION 1.3 Application Fields Low-power portable equipment, for example, cellular phones, PHSs, and camcorders. 1.4 Ordering Information Part Number Package On-chip ROM µ PD703015GC-×××-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) Mask ROM µ PD703015S1-×××-YJC 121-pin fine pitch BGA (12 × 12 mm) Mask ROM µ...
Page 24: Pin Configuration (Top View)
CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) • µ PD703015GC-×××-8EU • µ PD703015YGC-×××-8EU • µ PD70F3017GC-8EU • µ PD70F3017YGC-8EU P21/SO2 P71/ANI1 P22/SCK2 P70/ANI0 P23/RXD1 P24/TXD1 P25/ASCK1 P65/A21 P64/A20 P26/TI2/TO2 P63/A19 P27/TI3/TO3 P62/A18 P30/TI00...
Page 25 CHAPTER 1 INTRODUCTION 121-pin fine pitch BGA (12 × 12 mm) • µ PD703015S1-×××-YJC • µ PD703015YS1-×××-YJC • µ PD70F3017S1-YJC • µ PD70F3017YS1-YJC Top View Bottom View B C D E F G H L M N N M L H G F E D C B Pin Name...
Page 26 CHAPTER 1 INTRODUCTION Pin Identification A1-A21 : Address Bus P90-P96 : Port9 AD0-AD15 : Address/Data Bus P100-P107 : Port10 ADTRG : AD Trigger Input P110-P114 : Port11 ANI0-ANI11 : Analog Input P120 : Port12 ASCK0, ASCK1 : Asynchronous Serial Clock : Read ASTB : Address Strobe...
Page 27: Function Blocks
CHAPTER 1 INTRODUCTION 1.6 Function Blocks 1.6.1 Internal Block Diagram Instruction INTC HLDRQ (P96) INTP0-INTP6 queue HLDAK (P95) 32-bit Note 1 barrel Multiplier TI00, TI01 ASTB (P94) shifter 16 ×16– 32 Timer/counter TI10, TI11 DSTB/RD (P93) System 16-bit timer: TO0, TO1 R/W/WRH (P92) register TM0, TM1...
Page 28: On-Chip Units
CHAPTER 1 INTRODUCTION 1.6.2 On-chip units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions.
Page 29 CHAPTER 1 INTRODUCTION (7) Timer/counter A two-channel 16-bit timer/event counter and a four-channel 8-bit timer/event counter are both on chip, which enables measurement of pulse intervals and frequency as well as programmable pulse output. The two-channel 8-bit timer/event counter can be connected via a cascade connection to enable use as a 16-bit timer.
Page 30 CHAPTER 1 INTRODUCTION (14) Ports As shown below, following ports have general port functions and control pin functions. Port Port Function Control Function 8-bit I/O General port NMI, external interrupt, A/D converter trigger, RTP trigger 6-bit I/O Serial interface 8-bit I/O Serial interface, timer output 8-bit I/O Timer I/O, external address bus...
Page 31: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions The names and functions of this product’s pins are listed below. These pins can be divided into port pins and non- port pins according to their functions. (1) Port pins (1/3) Pin Name PULL Function...
Page 32 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name PULL Function Alternate Function Port 3 TI00 8-bit I/O port TI01 Input/output mode can be specified bitwise TI10 TI11 TO0/A13 TO1/A14 TI4/TO4/A15 TI5/TO5 Port 4 8-bit I/O port Input/output mode can be specified bitwise Port 5 8-bit I/O port Input/output mode can be specified bitwise...
Page 33 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name PULL Function Alternate Function Input ANI0 Port 7 8-bit input port ANI1 Input mode can be specified bitwise ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Input Port 8 ANI8 4-bit input port ANI9 Input mode can be specified bitwise ANI10 ANI11 LBEN/WRL...
Page 34 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/3) Pin Name PULL Function Alternate Function A1-A4 Output Low-order address bus used for external memory expansion P110-P113 A5-A12 P100/RTP0- P107/RTP7 P34/TO0 P35/TI1 P36/TI4/TO4 A16-A21 Output High-order address bus used for external memory expansion P60-P65 AD0-AD7 16-bit multiplexed address/data bus used for external memory...
Page 35 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name PULL Function Alternate Function RTPTRG Input RTP external trigger input P06/INTP5 Output External read/write status output P92/WRH RXD0 Input Serial receive data input for UART0 and UART1 P13/SI1 RXD1 SCK0 Serial clock I/O (3-wire type) for CSI0 to CSI2 P12/SCL SCK1 P15/ASCK0...
Page 36 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name PULL Function Alternate Function WAIT Input Control signal input for inserting wait in bus cycle P120 Output High-order byte write strobe signal output for external data bus P92/R/W Low-order byte write strobe signal output for external data bus P90/LBEN −...
Page 37: Pin States
CHAPTER 2 PIN FUNCTIONS 2.2 Pin States The operating states of various pins are described below with reference to their operating states. Operating State Reset STOP Mode IDLE Mode HALT Mode Bus Hold Idle State AD0-AD15 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z A1-A15...
Page 38: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P00 to P07 (Port 0) ··· 3-state I/O Port 0 is an 8-bit I/O port that can be set bitwise for input or output. P00 to P07 can function as I/O port pins and can also function as NMI inputs, external interrupt request inputs, external triggers for the A/D converter, or external triggers for the real-time output port.
Page 39 CHAPTER 2 PIN FUNCTIONS (2) P10 to P15 (Port 1) ··· 3-state I/O Port 1 is a 6-bit I/O port in which input and output pins can be specified bitwise. P10 to P15 can function as I/O port pins and can also operate as input or output pins for the serial interface. These pins can be set bitwise to port mode or a control mode.
Page 40 CHAPTER 2 PIN FUNCTIONS (3) P20 to P27 (Port 2) ··· 3-state I/O Port 2 is an 8-bit I/O port in which input and output pins can be specified bitwise. P20 to P27 can function as I/O port pins and can also operate as input or output pins for the serial interface. These pins can be set bitwise to port mode or a control mode.
Page 41 CHAPTER 2 PIN FUNCTIONS (4) P30 to P37 (Port 3) ··· 3-state I/O Port 3 is an 8-bit I/O port in which input and output pins can be specified bitwise. P30 to P37 can function as I/O port pins and can also operate as input or output pins for the timer/counter. These pins can be set bitwise to port mode or a control mode.
Page 42 CHAPTER 2 PIN FUNCTIONS (b) Control mode (external expansion mode) P40 to P47 can be set as AD0 to AD7 according to the contents of the memory expansion register (MM). AD0 to AD7 (Address/Data 0 to 7) ··· 3-state I/O These are multiplexed address/data bus that is used for external access.
Page 43 CHAPTER 2 PIN FUNCTIONS (a) Port mode P60 to P65 can be set bitwise as input or output pins according to the contents of port 6 mode register (PM6). (b) Control mode (external expansion mode) P60 to P65 can be set as A16 to A21 according to the contents of the memory expansion register (MM). A16 to A21 (Address 16 to 21) ···...
Page 44 CHAPTER 2 PIN FUNCTIONS (9) P90 to P96 (Port 9) ··· 3-state I/O Port 9 is a 7-bit I/O port in which input and output pins can be specified bitwise. P90 to P96 can function as I/O port pins and can also operate as control signal output pins and bus hold control signal output pins when using external memory expansion.
Page 45 CHAPTER 2 PIN FUNCTIONS (iii) R/W (Read/Write Status) ··· output In this mode, this pin is output for the status signal that indicates whether the bus cycle is a read cycle or write cycle during external access. High level is set during the read cycle and low level is set during the write cycle.
Page 46 CHAPTER 2 PIN FUNCTIONS (ix) WRH (Write Strobe High Level Data) ··· output In this mode, this is write strobe signal output pin for the high-order data in an external 16-bit data bus. Output occurs during the write cycle, similar to DSTB. (x) RD (Read) ···...
Page 47 CHAPTER 2 PIN FUNCTIONS A1 to A4 (Address 1 to 4) ···output These are address bus that is used for external access. These pins operate as the low-order 4-bit address output pins within a 22-bit address. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle.
Page 48 CHAPTER 2 PIN FUNCTIONS (16) AV (Analog V This is the analog power supply pin for the A/D converter. (17) AV (Analog V This the ground pin for the A/D converter. (18) AV (Analog Reference Voltage) … input This is the reference voltage supply pin for the A/D converter. (19) BV (Power Supply for Bus Interface) This is the positive power supply pin for the bus interface.
Page 49: Pins' I/O Circuit Types And Handling When Not Used
CHAPTER 2 PIN FUNCTIONS 2.4 Pins’ I/O Circuit Types and Handling When Not Used (1/2) Alternate Function I/O Circuit Type Recommended Connection Method During input : connect to V P01 to P04 INTP0 to INTP3 During output : leave open INTP4/ADTRG INTP5/RTPTRG INTP6...
Page 50 CHAPTER 2 PIN FUNCTIONS (2/2) Alternate Function I/O Circuit Type Recommended Connection Method LBEN/WRL During input : connect to BV or BV During output : leave open UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ P100 to P107 RTP0/A5 to RTP7/A12 During input : connect to V or V During output : leave open...
Page 51: Pins' I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.5 Pins’ I/O Circuits (1/2) Type 2 Type 5-A pullup P-ch enable data P-ch IN/OUT Schmitt trigger input having hysteresis characteristics output N-ch disable input enable Type 4 Type 8-A pullup data P-ch P-ch enable data P-ch IN/OUT output...
Page 52 CHAPTER 2 PIN FUNCTIONS (2/2) Type 10-A Type 26 pullup pullup P-ch P-ch enable enable data data P-ch P-ch IN/OUT IN/OUT open-drain open-drain N-ch output disable N-ch output disable Type 16 feedback cut-off P-ch...
Page 53: Chapter 3 Cpu Functions
CHAPTER 3 CPU FUNCTIONS The CPU of the V850/SA1 is based on the RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 Features • Minimum instruction execution time: 58 ns (at 17 MHz) •...
Page 54: Cpu Register Set
CHAPTER 3 CPU FUNCTIONS 3.2 CPU Register Set The CPU registers of the V850/SA1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers are 32 bits width. For details, refer to V850 Family User’s Manual Architecture.
Page 55: Program Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.1 Program register set The program register set includes general registers and a program counter. (1) General registers Thirty-two general registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable.
Page 56: System Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Table 3-2. System Register Numbers System Register Name Usage Operation EIPC Status saving registers during These registers save the PC and PSW when an interrupt exception or interrupt occurs.
Page 57 CHAPTER 3 CPU FUNCTIONS (2) Program Status Word (PSW) After reset: 00000020H Symbol Reserved field (fixed to 0). Indicates that NMI processing is in progress. This flag is set when NMI is accepted, and disables multiple interrupts. Indicates that an exception processing is in progress. This flag is set at the generation of exception.
Page 58: Operation Modes
CHAPTER 3 CPU FUNCTIONS 3.3 Operation Modes The V850/SA1 has the following operations modes. (1) Normal operation mode (Single-chip mode) After the system has been released from the reset status, the pins related to the bus interface are set for port mode, execution branches to the reset entry address of the internal ROM, and instruction processing written in the internal ROM is started.
Page 59: Address Space
CHAPTER 3 CPU FUNCTIONS 3.4 Address Space 3.4.1 CPU address space The CPU of the V850/SA1 is of 32-bit architecture and supports up to 4 Gbytes of linear address space (data space) during operand addressing (data access). When referencing instruction addresses, a linear address space (program space) of up to 16 Mbytes is supported.
Page 60: Image (Virtual Address Space)
CHAPTER 3 CPU FUNCTIONS 3.4.2 Image (virtual address space) The core CPU supports 4 Gbytes of “virtual” addressing space, or 256 memory blocks, each containing 16-Mbyte memory locations. In actuality, the same 16-Mbyte block is accessed regardless of the values of bits 31 to 24 of the CPU address.
Page 61: Wrap-Around Of Cpu Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are set to “0”, and only the lower 24 bits are valid. Even if a carry or borrow occurs from bit 23 to 24 as a result of branch address calculation, the higher 8 bits ignore the carry or borrow and remain “0”.
Page 62: Memory Map
CHAPTER 3 CPU FUNCTIONS 3.4.4 Memory map The V850/SA1 reserves areas as shown below. Figure 3-3. Memory Map Single-chip mode Single-chip mode Mask ROM Flash memory (external expansion mode) internal version internal version xxFFFFFFH xxFFFFFFH On-chip peripheral On-chip peripheral 4 KB I/O area I/O area xxFFF000H...
Page 63: Area
CHAPTER 3 CPU FUNCTIONS 3.4.5 Area (1) Internal ROM area A 1-Mbyte area corresponding to addresses 000000H to 0FFFFFH is reserved for the internal ROM area. The V850/SA1 is provided with physical internal ROM as follows: Physical internal ROM: 000000H to 01FFFFH (128 Kbytes) − Mask ROM internal version 000000H to 03FFFFH (256 Kbytes) −...
Page 64: Interrupt/Exception Table
CHAPTER 3 CPU FUNCTIONS Table 3-3. Interrupt/Exception Table Start Address of Interrupt/Exception Table Interrupt/Exception Source 00000000H RESET 00000010H 00000020H INTWDT 0000004nH TRAP0n (n = 0 to F) 0000005nH TRAP1n (n = 0 to F) 00000060H ILGOP 00000080H INTWDTM 00000090H INTP0 000000A0H INTP1 000000B0H...
Page 65 CHAPTER 3 CPU FUNCTIONS (2) Internal RAM area The internal RAM is incorporated in the following area. Physical internal RAM: FFE000H to FFEFFFH (4 Kbytes) … Mask ROM internal version FFD000H to FFEFFFH (8 Kbytes) … Flash memory internal version In the flash memory internal version, 12 Kbytes of FFC000H to FFEFFFH is reserved as an internal RAM area.
Page 66 CHAPTER 3 CPU FUNCTIONS (3) On-chip peripheral I/O area A 4-Kbyte area of addresses FFF000H to FFFFFFH is reserved as an on-chip peripheral I/O area. The V850/SA1 is provided with a 1-Kbyte area of addresses FFF000H to FFF3FFH as a physical on-chip peripheral I/O area, and its image can be seen on the rest of the area (FFF400H to FFFFFFH).
Page 67: External Memory Area (When Expanded To 64 K, 256 K, Or 1 Mbytes)
CHAPTER 3 CPU FUNCTIONS (4) External memory area The V850/SA1 can use an area of up to 100000H to FFBFFFH (16 Mbytes) for external memory accesses. 64 K, 256 K, 1 M, or 4 Mbytes of physical external memory can be allocated when the external expansion mode is specified.
Page 68: External Memory Area (When Expanded To 4 Mbytes)
CHAPTER 3 CPU FUNCTIONS Figure 3-6. External Memory Area (when expanded to 4 Mbytes) Mask ROM Flash memory internal version internal version xxFFFFFFH xxFFFFFFH On-chip peripheral I/O Internal RAM xxFFDFFFH xxFFBFFFH Image Physical external memory 3FFFFFH External memory Image 000000H Image xx100000H xx100000H...
Page 69: External Expansion Mode
CHAPTER 3 CPU FUNCTIONS 3.4.6 External expansion mode The V850/SA1 allows external devices to be connected to the external memory space by using the pins of ports 4, 5, 6, and 9. To connect an external device, the port pins must be set in the external expansion mode by using the memory expansion mode register (MM).
Page 70: Memory Expansion Mode Register (Mm) Format
CHAPTER 3 CPU FUNCTIONS Figure 3-7. Memory Expansion Mode Register (MM) Format After reset: 00H Address: FFFFF04CH Symbol P95 and P96 Operation Modes Port mode External expansion mode (HLDAK: P95, HLDRQ: P96) Address Space Port 4 Port 5 Port 6 Port 9 −...
Page 71: Memory Address Output Mode Register (Mam) Format
CHAPTER 3 CPU FUNCTIONS (2) Memory address output mode register (MAM) Sets the mode of ports 3, 10, and 11. Separate output can be set for the address bus (A1 to A15) in the external expansion mode. Only writing in 8-bit units is available for the MAM register. If read is performed, undefined values will be read. Bits 3 to 7 are fixed to 0.
Page 72: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.7 Recommended use of address space The architecture of the V850/SA1 requires that a register that serves as a pointer be secured for address generation in operand data accessing for data space. The address in this pointer register ±32 Kbytes can be accessed directly from instruction.
Page 73 CHAPTER 3 CPU FUNCTIONS Application of wrap-around For example, when R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, an addressing range of 00000000H ± 32 Kbytes can be referenced with the sign-extended, 16-bit displacement value. By mapping the external memory in the 24-Kbyte area in the figure, all resources including on-chip hardware can be accessed with one pointer.
Page 74: Recommended Memory Map (Flash Memory Internal Version)
CHAPTER 3 CPU FUNCTIONS Figure 3-9. Recommended Memory Map (Flash Memory Internal Version) Program space Data space FFFFFFFFH On-chip peripheral I/O FFFFF3C6H FFFFF3C5H FFFFF000H FFFFEFFFH Internal xxFFFFFFH On-chip peripheral I/O FFFFC000H xxFFF3C6H FFFFBFFFH xxFFF3C5H External xxFFF000H memory xxFFEFFFH FF800000H FF7FFFFFH Internal xxFFC000H 01000000H...
Page 75: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTIONS 3.4.8 Peripheral I/O registers (1/5) Bit Units for Address Function Register Name Symbol Manipulation After Reset 1 bit 8 bits 16 bits Note FFFFF000H Port 0 FFFFF002H Port 1 FFFFF004H Port 2 FFFFF006H Port 3 FFFFF008H Port 4 FFFFF00AH Port 5...
Page 76 CHAPTER 3 CPU FUNCTIONS (2/5) Bit Units for Address Function Register Name Symbol Manipulation After Reset 1 bit 8 bits 16 bits FFFFF080H Pull-up resistor option register 0 FFFFF082H Pull-up resistor option register 1 FFFFF084H Pull-up resistor option register 2 FFFFF086H Pull-up resistor option register 3 FFFFF094H...
Page 77 CHAPTER 3 CPU FUNCTIONS (3/5) Bit Units for Address Function Register Name Symbol Manipulation After Reset 1 bit 8 bits 16 bits FFFFF130H Interrupt control register STIC1 FFFFF132H Interrupt control register ADIC FFFFF134H Interrupt control register DMAIC0 FFFFF136H Interrupt control register DMAIC1 FFFFF138H Interrupt control register...
Page 78 CHAPTER 3 CPU FUNCTIONS (4/5) Bit Units for Address Function Register Name Symbol Manipulation After Reset 1 bit 8 bits 16 bits FFFFF240H 8-bit counter 2 FFFFF242H 8-bit compare register 2 CR20 FFFFF244H Timer clock selection register 2 TCL2 FFFFF246H 8-bit timer mode control register 2 TMC2 FFFFF24AH...
Page 79 CHAPTER 3 CPU FUNCTIONS (5/5) Bit Units for Address Function Register Name Symbol Manipulation After Reset 1 bit 8 bits 16 bits FFFFF310H Asynchronous serial interface mode register 1 ASIM1 FFFFF312H Asynchronous serial interface status register 1 ASIS1 FFFFF314H Baud rate generator control register 1 BRGC1 FFFFF316H Transmission shift register 1...
Page 80: Specific Registers
CHAPTER 3 CPU FUNCTIONS 3.4.9 Specific registers Specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, it is notified by the system status register (SYS).
Page 81 CHAPTER 3 CPU FUNCTIONS A description example is given below. [Description example]: In case of PSC register LDSR rX,5 ; NP bit = 1 ST.B r0,PRCMD [r0] ; Write to PRCMD ST.B rD,PSC [r0] ; PSC register setting LDSR rY,5 ;...
Page 82 CHAPTER 3 CPU FUNCTIONS (1) Command register (PRCMD) The command register (PRCMD) is a register used when write-accessing the specific register to prevent incorrect writing to the specific registers due to the erroneous program execution. This register can be written in 8-bit units. It becomes undefined values in a read cycle. Occurrence of illegal store operations can be checked by the PRERR bit of the SYS register.
Page 83: Chapter 4 Bus Control Function
CHAPTER 4 BUS CONTROL FUNCTION The V850/SA1 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 4.1 Features • 16-bit data bus • External devices connected through multiplexed I/O port pins •...
Page 84: Control Register
CHAPTER 4 BUS CONTROL FUNCTION 4.2.2 Control register (1) System control register (SYC) This register switches control signals for bus interface. The system control register can be read/written in 8- or 1-bit units. After reset: 00H Address: FFFFF064H Symbol Bus Interface Control DSTB, R/W, UBEN, LBEN signal outputs RD, WRL, WRH, UBEN signal outputs 4.3 Bus Access...
Page 85: Bus Width
CHAPTER 4 BUS CONTROL FUNCTION 4.3.2 Bus width CPU carries out peripheral I/O access and external memory access in 8-, 16-, or 32-bit. The following shows the operation for each access. (1) Byte access (8 bits) Byte access is divided into two types, the access to even address and the access to odd address. (a) Access to even address (b) Access to odd address Byte data...
Page 86: Memory Block Function
CHAPTER 4 BUS CONTROL FUNCTION 4.4 Memory Block Function The 16-Mbyte memory space is divided into memory blocks of 1-Mbyte units. The programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. FFFFFFH Block 15 Peripheral I/O area F00000H...
Page 87: Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5 Wait Function 4.5.1 Programmable wait function To facilitate interfacing with low-speed memories and I/O devices, up to 3 data wait states can be inserted in a bus cycle for two memory blocks. The number of wait states can be programmed by using data wait control register (DWC).
Page 88: External Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be in- serted in a bus cycle by sampling the external wait pin (WAIT) to synchronize with the external device. The external WAIT signal does not affect the access times of the internal ROM, internal RAM, and on-chip periph- eral I/O areas.
Page 89: Idle State Insertion Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6 Idle State Insertion Function To facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory read accesses, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The bus cycle follow- ing continuous bus cycles starts after one idle state.
Page 90: Bus Hold Function
CHAPTER 4 BUS CONTROL FUNCTION 4.7 Bus Hold Function 4.7.1 Outline of function MM3 bit of the memory expansion register (MM) is set (1), the HLDRQ and HLDAK pin functions of P95 and P96 become valid. When the HLDRQ pin becomes active (low) indicating that another bus master is requesting acquisition of the bus, Note the external address/data bus and strobe pins go into a high-impedance state , and the bus is released (bus hold...
Page 91: Bus Hold Procedure
CHAPTER 4 BUS CONTROL FUNCTION 4.7.2 Bus hold procedure The procedure of the bus hold function is illustrated below. <1>HLDRQ = 0 accepted Nomal status <2>All bus cycle start request pending <3>End of current bus cycle <4>Bus idle status <5>HLDAK = 0 Bus hold status <6>HLDRQ = 1 accepted <7>HLDAK = 1...
Page 92: Bus Timing
CHAPTER 4 BUS CONTROL FUNCTION 4.8 Bus Timing The V850/SA1 can execute the read/write control for an external device by the following two modes. • Mode using DSTB, R/W, LBEN, UBEN, and ASTB signals • Mode using RD, WRL, WRH, and ASTB signals Set these modes by using the BIC bit of the system control register (SYC).
Page 93 CHAPTER 4 BUS CONTROL FUNCTION (2) Memory read (1 wait) CLKOUT (input) Address A16 to A21 (output) A1 to A15 (output) Address AD0 to AD15 Address Data (input/output) ASTB (output) R/W (output) WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input) Remarks 1.
Page 94 CHAPTER 4 BUS CONTROL FUNCTION (3) Memory read (0 wait, idle state) CLKOUT (input) Address A16 to A21 (output) Address A1 to A15 (output) AD0 to AD15 Address Data (input/output) ASTB (output) R/W (output) WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input) Remarks 1.
Page 95 CHAPTER 4 BUS CONTROL FUNCTION (4) Memory read (1 wait, idle state) CLKOUT (input) Address A16 to A21 (output) Address A1 to A15 (output) AD0 to AD15 Address Data (input/output) ASTB (output) R/W (output) WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input) Remarks 1.
Page 96 CHAPTER 4 BUS CONTROL FUNCTION (5) Memory write (0 wait) CLKOUT (input) A16 to A21 (output) Address Address A1 to A15 (output) AD0 to AD15 Note Address Data (input/output) ASTB (output) R/W (output) RD (output) DSTB (output) WRH, WRL (output) UBEN, LBEN (output) WAIT (input) Note...
Page 97 CHAPTER 4 BUS CONTROL FUNCTION (6) Memory write (1 wait) CLKOUT (input) Address A16 to A21 (output) A1 to A15 (output) Address AD0 to AD15 Note Address Data (input/output) ASTB (output) R/W (output) RD (output) DSTB (output) WRH, WRL (output) UBEN, LBEN (output) WAIT (input) Note AD0 to AD7 output invalid data when odd address byte data is accessed.
Page 98 CHAPTER 4 BUS CONTROL FUNCTION (7) Bus hold timing CLKOUT (input) HLDRQ (input) Note1 HLDAK (output) A16 to A21 (output) Address Address A1 to A15 (output) Address AD0 to AD15 Address Data Undefined Address (input/output) ASTB (output) Note2 R/W (output) DSTB, RD, WRH, WRL (output) UBEN, LBEN (output)
Page 99: Bus Priority
CHAPTER 4 BUS CONTROL FUNCTION 4.9 Bus Priority There are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch (continuous). The bus hold cycle is given the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (continuous) in that order.
Page 100 [MEMO]...
Page 101: Chapter 5 Interrupt/Exception Processing Function
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850/SA1 is provided with a dedicated interrupt controller (INTC) for interrupt processing and can process a total of 32 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event that occurs dependently on program execution.
Page 102: Interrupt Source List
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-1. Interrupt Source List (1/2) Interrupt Classifi- Default Genera- Exception Handler Type Name Trigger Control cation Priority ting Unit Code Address stored Register − − − Reset Interrupt RESET Reset input 0000H 00000000H Undefined −...
Page 103 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-1. Interrupt Source List (2/2) Interrupt Classifi- Default Genera- Exception Handler Restored Type Name Trigger Control cation Priority ting Unit Code Address Register Maskable Interrupt INTSR1 UART1 receiving end UART 01F0H 000001F0H nextPC SRIC1 INTST1 UART1 transmit end UART...
Page 104: Non-Maskable Interrupt
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2 Non-Maskable Interrupt The non-maskable interrupt is accepted unconditionally, even when interrupts are disabled (DI states) in the inter- rupt disabled (DI) status. The NMI is not subject to priority control and takes precedence over all the other interrupts. Non-maskable interrupt of the V850/SA1 are available for the following two requests: •...
Page 105: Accepting Operation
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.1 Accepting operation If the non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception code 0010H to the higher half-word (FECC) of ECR.
Page 106: Accepting Non-Maskable Interrupt Request
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-2. Accepting Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service routine is executing: Main routine (PSW. NP = 1) NMI request NMI request NMI request pending because PSW. NP = 1 Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service routine is executing: Main routine...
Page 107: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.2 Restore Execution is restored from the non-maskable interrupt processing by the RETI instruction. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC.
Page 108: Np Flag
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execution. This flag is set when the NMI interrupt has been accepted, and masks all interrupt requests to prohibit multiple interrupts from being acknowledged.
Page 109: Edge Detection Function Of Nmi Pin
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.5 Edge detection function of NMI pin This function specifies the valid edge of the non-maskable interrupt (NMI) by the rising edge specification register (EGP0) and falling edge specification register (EGN0). Read/write is available in 8- or 1-bit unit. Figure 5-4.
Page 110: Maskable Interrupts
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850/SA1 has 30 maskable inter- rupt sources. If two or more maskable interrupt requests are generated at the same time, they are accepted according to the default priority.
Page 111: Maskable Interrupt Processing
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-6. Maskable Interrupt Processing INT input INTC accepted Mask? PSW. ID = 0 Interrupt enable mode? Priority higher than that of interrupt currently processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with the same priority? Maskable interrupt request...
Page 112: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.2 Restore To restore execution from the maskable interrupt processing, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC.
Page 113: Priorities Of Maskable Interrupts
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.3 Priorities of maskable interrupts The V850/SA1 provides multiple interrupt service which accepts an interrupt while servicing another interrupt. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels which are specified by interrupt priority level specification bit (xxPRn).
Page 114: Example Of Interrupt Nesting Process
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-8. Example of Interrupt Nesting Process (1/2) Main routine Processing of a Processing of b Interrupt Interrupt request a request b Interrupt request b is accepted because the priority of (level 3) (level 2) b is higher than that of a and interrupts are enabled.
Page 115 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-8. Example of Interrupt Nesting Process (2/2) Main routine Processing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is kept pending because its Interrupt request k priority is lower than that of i.
Page 116: Example Of Processing Interrupt Requests Simultaneously Generated
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-9. Example of Processing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Processing of interrupt request b • Interrupt request b and c are accepted Interrupt request c (level 1) first according to their priorities.
Page 117: Interrupt Control Register (Xxicn)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each mas- kable interrupt request. The interrupt control register can be read/written in 8- or 1-bit units. Figure 5-10.
Page 118 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Address and bit of each interrupt control register is as follows: Address Register FFFFF100H WDTIC WDTIF WDTMK WDTPR2 WDTPR1 WDTPR0 FFFFF102H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF104H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF106H PIC2 PIF2 PMK2...
Page 119: In-Service Priority Register (Ispr)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.5 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently accepted. When an interrupt request is ac- cepted, the bit of this register corresponding to the priority level of that interrupt is set to 1 and remains set while the interrupt is serviced.
Page 120: Watchdog Timer Mode Register (Wdtm)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.7 Watchdog timer mode register (WDTM) Read/write is available in 8- or 1-bit units. Figure 5-12. Watchdog Timer Mode Register (WDTM) Format After reset: 00H Address: FFFFF384H Symbol WDTM WDTM4 Watchdog Timer Operation Control Count operation stop Count start after clearing WDTM4 Timer Mode Selection/Interrupt Control by WDT...
Page 121: Edge Detection Function
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.9 Edge detection function A valid edge of INTP0 to INTP6 pins can be selected every pin from the following four types: Rising edge, falling edge, both rising and falling edges, and neither rising nor falling edge detected. The rising edge specification register (EGP0) controls the validity of a rising edge.
Page 122: Software Exception
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always accepted. • TRAP instruction format: TRAP vector (where vector is 0 to 1FH) For details of the instruction function, refer to the V850 Family User’s Manual-Architecture. 5.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine:...
Page 123: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4.2 Restore To restore or return execution from the software exception service routine, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC.
Page 124: Ep Flag
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4.3 EP flag The EP flag in PSW is a status flag used to indicate that trap processing is in progress. It is set when a trap oc- curs, and the interrupt is disabled. After reset: 00000020H Symbol NP EP ID SAT CY OV NMI Processing...
Page 125: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-15 illustrates how the exception trap is processed. Figure 5-15. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing EIPC restored PC EIPSW ECR.EICC exception code PSW.EP PSW.ID 00000060H Exception processing 5.5.3 Restore To restore or return execution from the exception trap, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC.
Page 126: Reti Instruction Processing
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-16. RETI Instruction Processing RETI instruction PSW. EP PSW. NP EIPC FEPC EIPSW FEPSW Jump to PC Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the ex- ception trap process, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set PSW.EP back to 1 using the LDSR instruction immediately be- fore the RETI instruction.
Page 127: Priority Control
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.6 Priority Control 5.6.1 Priorities of interrupts and exceptions RESET TRAP ILGOP RESET × ← ← ← × ↑ ← ← × ↑ ↑ ← TRAP × ↑ ↑ ↑ ILGOP RESET : reset : non-maskable interrupt : maskable interrupt TRAP : software exception ILGOP : illegal op code exception...
Page 128 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) To accept maskable interrupts in service program Service program of maskable interrupt or exception • Saves EIPC to memory or register • Saves EIPSW to memory or register • EI instruction (enables interrupt acceptance) ←Accepts interrupt such as INTP input •...
Page 129 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Priorities 0 to 7 (0 is the highest) can be programmed for each maskable interrupt request for multiple interrupt processing control. To set a priority level, write values to the xxPRn0 to xxPRn2 bits of the interrupt request control register (xxICn) corresponding to each maskable interrupt request.
Page 130: Interrupt Latency Time
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.7 Interrupt Latency Time The following table describes the V850/SA1 interrupt latency time (from interrupt request generation to start of in- terrupt processing). Figure 5-17. Pipeline Operation at Interrupt Request Acknowledge 7 to 14 system clocks 4 system clocks System clock Interrupt request...
Page 131: Chapter 6 Clock Generation Function
CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 General The clock generator is a circuit which generates the clock pulses that are supplied to the CPU and peripheral hardware. There are two types of system clock oscillators. (1) Main system clock oscillator This oscillator has an oscillation frequency range of 1 MHz to 17 MHz.
Page 132: Clock Output Function
CHAPTER 6 CLOCK GENERATION FUNCTION 6.3 Clock Output Function This function outputs the CPU clock via the CLKOUT pin. When clock output is enabled, the CPU clock is output via the CLKOUT pin. When it is disabled, a low-level signal is output via the CLKOUT pin.
Page 133 CHAPTER 6 CLOCK GENERATION FUNCTION Figure 6-1. Format of Processor Clock Control Register (PCC) (2/2) Note Selection of CPU Clock (sub clock) Note If manipulating CK2, do so in 1-bit units. In the case of 8-bit manipulation, do not change the values of FLMD, CK1, and CK0.
Page 134: Format Of Power Saving Control Register (Psc)
CHAPTER 6 CLOCK GENERATION FUNCTION (2) Power saving control register (PSC) This is a specific register. It can be written to only when a specified combination of sequences is used. For details, see 3.4.9 Specific registers. This register can be read/written in 8- or 1-bit units. Figure 6-2.
Page 135: Power Saving Functions
CHAPTER 6 CLOCK GENERATION FUNCTION (3) Oscillation stabilization time select register (OSTS) This register can be read/written in 8-bit units. Figure 6-3. Format of Oscillation Stabilization Time Select Register (OSTS) After reset: Address : FFFFF380H OSTS OSTS2 OSTS1 OSTS0 Note Selection of Oscillation Stabilization Time OSTS2 OSTS1...
Page 136: Halt Mode
CHAPTER 6 CLOCK GENERATION FUNCTION (2) IDLE mode This mode stops the entire system by stopping the CPU’s operating clock as well as the operating clock for on- chip peripheral functions while the clock oscillator is still operating. However, the sub clock continues to operate and supplies a clock to the on-chip peripheral functions.
Page 137: Operating Statuses During Halt Mode
CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-1. Operating Statuses during HALT Mode (1/2) HALT Mode Setting When CPU Operates via Main Clock When CPU Operates via Sub Clock When sub clock does When sub clock exist When main clock’s When main clock’s Item not exist oscillation continues...
Page 138 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-1. Operating Statuses during HALT Mode (2/2) HALT Mode Setting When CPU Operates via Main Clock When CPU Operates via Sub Clock When sub clock does When sub clock exist When main clock’s When main clock’s Item not exist oscillation continues...
Page 139: Idle Mode
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4.3 IDLE mode (1) Settings and operating states This mode stops the entire system by stopping the on-chip main clock supply while the clock oscillator is still operating. The sub clock continues to operate. When this mode is canceled, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly.
Page 140 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-2. Operating Statuses during IDLE Mode (2/2) Mode When Sub Clock Exists When Sub Clock Does Not Exist External Operating interrupt INTP0-INTP3 Operating request INTP4-INTP6 Stopped During AD0-AD15 High impedance external A16-A21 expansion LBEN, UBEN mode DSTB, WRL, WRH, RD...
Page 141: Software Stop Mode
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4.4 Software STOP mode (1) Settings and operating states This mode stops the entire system by stopping the clock oscillator (generator) and by stopping the internal main clock. The sub clock oscillator continues operating and the on-chip sub clock supply is continued. When the FRC bit in the processor clock control register (PCC) is set (to “1”), the sub clock oscillator’s on-chip feedback resistance is cut.
Page 142: Oscillation Stabilization Time
CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-3. Operating States during Software STOP Mode (2/2) Mode Settings When Sub Clock Exists When Sub Clock Does Not Exist Item Real-time output Operates when INTTM4 or INTTM5 has been Stopped selected (when TM4 or TM5 is operating) Port function Held External bus interface...
Page 143 CHAPTER 6 CLOCK GENERATION FUNCTION STOP mode is set Oscillation ware Main clock STOP status Interrupt input Oscillator is stopped Count time value of time base counter (2) Use of RESET pin to allocate time (RESET pin input) For allocating time with RESET pin, refer to CHAPTER 15 RESET FUNCTION.
Page 144 [MEMO]...
Page 145: Chapter 7 Timer/Counter Function
CHAPTER 7 TIMER/COUNTER FUNCTION 7.1 16-bit Timer (TM0, TM1) 7.1.1 Overview • 16-bit capture/compare register: 2/each (CRn0, CRn1) • Independent capture/trigger input: 2/each (TIn0, TIn1) • Possible for outputting capture/match interrupt request signal (INTTMn0, INTTMn1) • Event input (shared with TIn0) via digital noise rejection circuit and possible for edge specification •...
Page 146: Block Diagram Of Tm0 And Tm1
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-1. Block Diagram of TM0 and TM1 Internal bus Capture/compare control register n (CRCn) CRCn2 CRCn1 CRCn0 Selector INTTMn0 16-bit capture/compare Noise Selector TIn1 rejection register n0 (CRn0) circuit Coincidence Note Count clock Clear 16-bit timer register (TMn) Output Selector control...
Page 147: Configuration
CHAPTER 7 TIMER/COUNTER FUNCTION (5) Square wave output Can output a square wave of any frequency. (6) One-shot pulse output Can output a one-shot pulse with any output pulse width. 7.1.3 Configuration Timer 0 consists of the following hardware: Table 7-1. Configuration of Timer 0 Item Configuration 16 bits ×...
Page 148: Valid Edge Of Tin0 Pin And Capture Trigger Of Crn0
CHAPTER 7 TIMER/COUNTER FUNCTION (2) Capture/compare register n0 (CR00, CR10) CRn0 is a 16-bit register that functions as a capture register and as a compare register. Whether this register functions as a capture or compare register is specified by using bit 0 (CRCn0) of the CRCn register. (a) When using CRn0 as compare register The value set to CRn0 is always compared with the count value of the TMn register.
Page 149 CHAPTER 7 TIMER/COUNTER FUNCTION (3) Capture/compare register n1 (CR01, CR11) This is a 16-bit register that can be used as a capture register and a compare register. Whether it is used as a capture register or compare register is specified by bit 2 (CRCn2) of the CRCn register. (a) When using CRn1 as compare register The value set to CRn1 is always compared with the count value of TMn.
Page 150: Timer 0, 1 Control Register
CHAPTER 7 TIMER/COUNTER FUNCTION 7.1.4 Timer 0, 1 Control Register The following four types of registers control timer 0, 1. • 16-bit timer mode control register n (TMCn) • Capture/compare control register n (CRCn) • 16-bit timer output control register n (TOCn) •...
Page 151: Format Of 16-Bit Timer Mode Control Register 0, 1 (Tmc0, Tmc1)
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-2. Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1) (1/2) After reset: 00H Address: FFFFF208H, FFFFF218H TMCn TMCn3 TMCn2 TMCn1 OVFn (n = 0, 1) Selects Operation Selects TOn Output TMCn3 TMCn2 TMCn1 Generation of Interrupt Mode and Clear Mode...
Page 152 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-2. Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1) (2/2) OVFn Detection of Overflow of 16-bit Timer Register n Overflows. Does not overflow. Cautions 1. Write operation to bits other than OVFn flag must be performed after halting the timer operation.
Page 153: Format Of Capture/Compare Control Register 0, 1 (Crc0, Crc1)
CHAPTER 7 TIMER/COUNTER FUNCTION (2) Capture/compare control register 0, 1 (CRC0, CRC1) This register controls the operation of the capture/compare register n (CRn0 and CRn1). CRCn is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC0 and CRC1 to 00H. Figure 7-3.
Page 154 CHAPTER 7 TIMER/COUNTER FUNCTION (3) 16-bit timer output control register 0, 1 (TOC0, TOC1) This register controls the operation of the timer n output control circuit by setting or resetting the R-S flip-flop (LV0), enabling or disabling reverse output, enabling or disabling output of timer n, enabling or disabling one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software.
Page 155: Format Of 16-Bit Timer Output Control Register 0, 1 (Toc0, Toc1)
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-4. Format of 16-Bit Timer Output Control Register 0, 1 (TOC0, TOC1) At reset: 00H Address: FFFFF20CH, FFFFF21CH TOCn OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn (n = 0, 1) OSPTn Controls Output Trigger of One-shot Pulse by Software No one-shot pulse trigger Uses one-shot pulse trigger.
Page 156: Format Of Prescaler Mode Register 0 (Prm0)
CHAPTER 7 TIMER/COUNTER FUNCTION (4) Prescaler mode register 0 (PRM0) This register selects a count clock of the 16-bit timer (TM0) and the valid edge of TI0n input. PRM0 is set by an 8-bit memory manipulation instruction. RESET input clears PRM0 to 00H. Figure 7-5.
Page 157: Format Of Prescaler Mode Register 1 (Prm1)
CHAPTER 7 TIMER/COUNTER FUNCTION (5) Prescaler mode register 1 (PRM1) This register selects a count clock of the 16-bit timer (TM1) and the valid edge of TI1n input. PRM1 is set by an 8-bit memory manipulation instruction. RESET input clears PRM1 to 00H. Figure 7-6.
Page 158: Operation
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2 Operation 7.2.1 Operation as interval timer (16 bits) Timer 0 operates as an interval timer when the 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) are set as shown in Figure 7-7. In this case, timer 0 repeatedly generates an interrupt at the time interval specified by the count value set in advance to the 16-bit capture/compare register n (CRn0, CRn1).
Page 159: Configuration Of Interval Timer
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-8. Configuration of Interval Timer 16-bit capture/compare register n0 (CRn0) INTTMn0 Note Count clock Selector 16-bit timer register n (TMn) OVFn TIn0 Clear circuit Note Count clock is set by the PRMn register. Remarks 1. “ ”...
Page 160: Ppg Output Operation
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.2 PPG output operation Timer 0 can be used for PPG (Programmable Pulse Generator) output by setting the 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) as shown in Figure 7-10. The PPG output function outputs a square wave with a cycle specified by the count value set in advance to the 16-bit capture/compare register n0 (CRn0) and a pulse width specified by the count value set in advance to the 16-bit capture/compare register n1 (CRn1).
Page 161: Pulse Width Measurement
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.3 Pulse width measurement The 16-bit timer register n (TMn) can be used to measure the pulse widths of the signals input to the TIn0 and TIn1 pins. Measurement can be carried out with TMn used as a free running counter or by restarting the timer in synchronization with the edge of the signal input to the TIn0 pin.
Page 162: Configuration For Pulse Width Measurement With Free Running Counter
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-12. Configuration for Pulse Width Measurement with Free Running Counter Note Count clock OVFn Selector 16-bit timer register n (TMn) 16-bit capture/compare register n1 TIn0 (CRn1) INTTMn1 Internal bus Note Set by the PRMn register. Remarks 1.
Page 163: Control Register Settings For Measurement Of Two Pulse Widths With Free Running Counter
CHAPTER 7 TIMER/COUNTER FUNCTION (2) Measurement of two pulse widths with free running counter The pulse widths of the two signals respectively input to the TIn0 and TIn1 pins can be measured when the 16- bit timer register n (TMn) is used as a free running counter (refer to Figure 7-14). When the edge specified by bits 4 and 5 (ESn00 and ESn01) of the prescaler mode register n (PRMn) is input to the TIn0 pin, the value of the TMn is loaded to the 16-bit capture/compare register n1 (CRn1) and an external interrupt request signal (INTTMn1) is set.
Page 164: Crn1 Capture Operation With Rising Edge Specified
CHAPTER 7 TIMER/COUNTER FUNCTION • Capture operation (free running mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 7-15. CRn1 Capture Operation with Rising Edge Specified Count clock n − 3 n −...
Page 165 CHAPTER 7 TIMER/COUNTER FUNCTION (3) Pulse width measurement with free running counter and two capture registers When the 16-bit timer register n (TMn) is used as a free running counter (refer to Figure 7-17), the pulse width of the signal input to the TIn0 pin can be measured. When the edge specified by bits 4 and 5 (ESn00 and ESn01) of the prescaler mode register n (PRMn) is input to the TIn0 pin, the value of TMn is loaded to the 16-bit capture/compare register n1 (CRn1), and an external interrupt request signal (INTTMn1) is set.
Page 166 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-18. Timing of Pulse Width Measurement with Free Running Counter and Two Capture Registers (with rising edge specified) Count clock TMn count 0000H 0001H D0+1 D1+1 FFFFH 0000H D2+1 value TIn0 pin input Value loaded to CRn1 Value loaded to CRn0...
Page 167: Control Register Settings For Pulse Width Measurement By Restarting
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-19. Control Register Settings for Pulse Width Measurement by Restarting (a) 16-bit timer mode control register 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts at valid edge of TIn0 pin. (b) Capture/compare control register 0, 1 (CRC0, CRC1) CRCn2 CRCn1 CRCn0...
Page 168: Operation As External Event Counter
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.4 Operation as external event counter Timer 0 can be used as an external event counter which counts the number of clock pulses input to the TIn0 pin from an external source by using the 16-bit timer register n (TMn). Each time the valid edge specified by the prescaler mode register n (PRMn) has been input, TMn is incremented.
Page 169: Operation To Output Square Wave
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-22. Configuration of External Event Counter 16-bit capture/compare register n (CRn0) Coincidence INTTMn0 Clear Note Count clock OVFn Selector 16-bit timer/counter n (TMn) Noise rejection 16-bit capture/compare Valid edge of TIn0 register n (CRn1) Internal bus Note Set by the PRMn register.
Page 170: Control Register Settings In Square Wave Output Mode
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-24. Control Register Settings in Square Wave Output Mode (a) 16-bit timer mode control register 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts on coincidence between TMn and CRn0. (b) Capture/compare control register 0, 1 (CRC0, CRC1) CRCn2 CRCn1 CRCn0...
Page 171: Operation To Output One-Shot Pulse
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-25. Timing of Square Wave Output Operation Count clock N − 1 N − 1 TMn count value 0000H 0001H 0002H 0000H 0001H 0002H 0000H CRn0 INTTMn0 TOn0 pin output 7.2.6 Operation to output one-shot pulse Timer 0 can output a one-shot pulse in synchronization with a software trigger and an external trigger (TIn0 pin input).
Page 172: Control Register Settings For One-Shot Pulse Output With Software Trigger
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-26. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts on coincidence between TMn and CRn0. (b) Capture/compare control register 0, 1 (CRC0, CRC1) CRCn2 CRCn1...
Page 173: Timing Of One-Shot Pulse Output Operation With Software Trigger
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-27. Timing of One-Shot Pulse Output Operation with Software Trigger Sets 0CH to TMCn (TMn count starts) Count clock TMn count value N − 1 M − 1 0000H 0001H N + 1 0000H 0000H 0001H CRn1 set value CRn0 set value...
Page 174: Control Register Settings For One-Shot Pulse Output With External Trigger
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-28. Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control register 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts at valid edge of TIn0 pin. (b) Capture/compare control register 0, 1 (CRC0, CRC1) CRCn2 CRCn1...
Page 175: Cautions
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-29. Timing of One-Shot Pulse Output Operation with External Trigger (with rising edge specified) Sets TMCn to 08H. (TMn count starts) Count clock M − 2 M − 1 TMn count value 0000H 0001H 0000H N + 1 N + 2 M + 1...
Page 176: Timing After Changing Compare Register During Timer Count Operation
CHAPTER 7 TIMER/COUNTER FUNCTION (2) Setting compare register during timer count operation If the value to which the current value of the 16-bit capture/compare register n0 (CRn0) has been changed is less than the value of the 16-bit timer register n (TMn), TMn continues counting, overflows, and starts counting again from 0.
Page 177: Operation Timing Of Ovfn Flag
CHAPTER 7 TIMER/COUNTER FUNCTION (4) Setting valid edge Before setting the valid edge of the TIn0 pin, stop the timer operation by resetting bits 2 and 3 (TMCn2 and TMCn3) of the 16-bit timer mode control register n to 0, 0. Set the valid edge by using bits 4 and 5 (ESn00 and ESn01) of the prescaler mode register n (PRMn).
Page 178: 8-Bit Timer (Tm2-Tm5)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.3 8-bit Timer (TM2-TM5) 7.3.1 Functions 8-bit timer n has the following two modes. • Mode using timer alone (individual mode) • Mode using the cascade connection (16-bit resolution: cascade connection mode) These two modes are described next. (1) Mode using timer alone (individual mode) The timer operates as an 8-bit timer/event counter.
Page 179: Configuration
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-34. Block Diagram of TM2-TM5 Internal bus 8-bit compare Selector register n (CRn0) INTTMn Mask circuit Match 8-bit counter n Selector Selector (TMn) Note Count clock Clear Invert level Selector TCEn TMCn6 TMCn4 LVSn LVRn TMCn1 TOEn TCLn2 TCLn1 TCLn0 Timer mode control register n...
Page 180 CHAPTER 7 TIMER/COUNTER FUNCTION (1) 8-bit counter 2-5 (TM2-TM5) TMn is an 8-bit read-only register that counts the count pulses. The counter is incremented synchronous to the rising edge of the count clock. When the count is read out during operation, the count clock input temporarily stops and the count is read at that time.
Page 181: Timer N Control Register
CHAPTER 7 TIMER/COUNTER FUNCTION 7.3.3 Timer n control register The following two registers control timer n. • Timer clock selection register n (TCLn) • 8-bit timer mode control register n (TMCn) (1) Timer clock selection register 2-5 (TCL2-TCL5) This register sets the count clock of timer n. TCLn is set by an 8-bit memory manipulation instruction.
Page 182: Format Of Tm4, Tm5 Timer Clock Selection Register 4 And 5 (Tcl4, Tcl5)
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-36. Format of TM4, TM5 Timer Clock Selection Register 4 and 5 (TCL4, TCL5) After reset: 00H Address: FFFFF264H, FFFFF274H TCLn TCLn2 TCLn1 TCLn0 (n = 4, 5) TCLn2 TCLn1 TCLn0 Count Clock Selection Falling edge of TIn Rising edge of TIn /4 (4.25 MHz) /8 (2.13 MHz)
Page 183: Format Of 8-Bit Timer Mode Control Register 2-5 (Tmc2-Tmc5)
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-37. Format of 8-Bit Timer Mode Control Register 2-5 (TMC2-TMC5) (1/2) After reset: 04H Address: TMC2 FFFFF246H TMC3 FFFFF256H TMC4 FFFFF266H TMC5 FFFFF276H TMCn TCEn TMCn6 TMCn4 LVSn LVRn TMCn1 TOEn (n = 2-5) TCEn TMn Count Control Counting is disabled after the counter is cleared to 0 (prescaler disabled).
Page 184 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-37. Format of 8-Bit Timer Mode Control Register 2-5 (TMC2-TMC5) (2/2) TOEn Timer Output Control Disable output (port mode) Enable output Cautions 1. When using as the timer output (TOn) pin, set the port value to “0” (port mode output). An ORed value of the timer output value is output.
Page 185: Operation
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4 Operation 7.4.1 Operating as an interval timer (8-bit operation) The timer operates as an interval timer that repeatedly generates interrupts at the interval of the preset count in the 8-bit compare register n (CRn0). If the count in the 8-bit counter n (TMn) matches the value set in CRn0, simultaneous to clearing the value of TMn to 0 and continuing the count, the interrupt request signal (INTTMn) is generated.
Page 186 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-38. Timing of Interval Timer Operation (2/3) When CRn0 = 00H Count clock TMn 00H CRn0 TCEn INTTMn Interval time Remark n = 2 to 5 When CRn0 = FFH Count clock CRn0 TCEn INTTMn Interrupt Interrupt received received...
Page 187: Operating As External Event Counter
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-38. Timing of Interval Timer Operation (3/3) Operated by CRn0 transition (M < N) Count clock CRn0 TCEn INTTMn ↑ ↑ CRn0 transition TMn overflows since M < N. Operated by CRn0 transition (M > N) Count clock N−1 M−1...
Page 188: Operating As Square Wave Output (8-Bit Resolution)
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-39. Timing of External Event Counter Operation (when rising edge is set) TMn count N−1 0000 0001 0002 0003 0004 0005 0000 0001 0002 0003 value CRn0 INTTMn Remark n = 2 to 5 7.4.3 Operating as square wave output (8-bit resolution) A square wave having any frequency is output at the interval preset in the 8-bit compare register n (CRn0).
Page 189: Operating As 8-Bit Pwm Output
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.4 Operating as 8-bit PWM output By setting bit 6 (TMCn6) of the 8-bit timer mode control register n (TMCn) to 1, the timer operates as a PWM output. Pulses with the duty cycle determined by the value set in the 8-bit compare register n (CRn0) is output from TOn. Set the width of the active level of the PWM pulse in CRn0.
Page 190: Timing Of Pwm Output
CHAPTER 7 TIMER/COUNTER FUNCTION Basic operation of PWM output Figure 7-40. Timing of PWM Output Basic operation (active level = H) Count clock CRn0 TCEn INTTMn ↑ ↑ ↑ Active level Inactive level Active level When CRn0 = 0 Count clock FFH 00H 01H 02H FFH 00H 01H 02H CRn0...
Page 191: Timing Of Operation Based On Crn0 Transitions
CHAPTER 7 TIMER/COUNTER FUNCTION (ii) Operation based on CRn0 transitions Figure 7-41. Timing of Operation Based on CRn0 Transitions When the CRn0 value changes from N to M before TMn overflows Count clock FFH 00H FFH 00H 01H 02H M+1 M+2 CRn0 TCEn INTTMn...
Page 192 CHAPTER 7 TIMER/COUNTER FUNCTION (2) Cascade connection (16-bit timer) mode The V850/SA1 provides a 16-bit register that can be used when connecting in cascade. Available registers are as follows. TM2-TM3 cascade connection: 16-bit counter TM23 (Address: FFFFF24AH) 16-bit compare register CR23 (Address: FFFFF24CH) TM4-TM5 cascade connection: 16-bit counter TM45 (Address: FFFFF26AH) 16-bit compare register CR45 (Address: FFFFF26CH) •...
Page 193: Cascade Connection Mode With 16-Bit Resolution
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-42 shows a timing example of the cascade connection mode with 16-bit resolution. Figure 7-42. Cascade Connection Mode with 16-Bit Resolution Count clock FFH 00H FFH 00H 01H 00H 01H FFH 00H TMn+1 M−1 CRn0 CR(n+1)0 TCEn TCEn+1...
Page 194: Cautions
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.5 Cautions (1) Error when the timer starts The time until the coincidence signal is generated after the timer starts has a maximum error of one clock. The reason is the starting of the 8-bit counter n (TMn) is asynchronous with respect to the count pulse. Figure 7-43.
Page 195: Chapter 8 Watch Timer
CHAPTER 8 WATCH TIMER 8.1 Function The watch timer has the following functions: • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. Figure 8-1 shows the block diagram of the watch timer. Figure 8-1.
Page 196: Configuration
CHAPTER 8 WATCH TIMER (1) Watch timer The watch timer generates an interrupt request (INTWT) at time intervals of 0.5 seconds by using the main system clock or subsystem clock. (2) Interval timer The watch timer generates an interrupt request (INTWTI) at time intervals specified in advance. Table 8-1.
Page 197: Watch Timer Control Register
CHAPTER 8 WATCH TIMER 8.3 Watch Timer Control Register The watch timer mode control register (WTM) controls the watch timer. • Watch timer mode control register (WTM) This register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag.
Page 198: Operation
CHAPTER 8 WATCH TIMER Figure 8-2. Format of Watch Timer Mode Control Register (WTM) (2/2) WTM0 Enables Operation of Watch Timer Stops operation (clears both prescaler and timer). Enables operation. Remarks 1. f : Watch timer clock frequency (f or f 2.
Page 199: Operation As Interval Timer
CHAPTER 8 WATCH TIMER 8.4.2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance. The interval time can be selected by bits 4 through 6 (WTM4 through WTM6) of the watch timer mode control register (WTM).
Page 200 [MEMO]...
Page 201: Chapter 9 Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.1 Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer • Selecting the oscillation stabilization time Caution Use the watchdog timer mode register (WDTM) to select the watchdog timer mode or the interval timer mode.
Page 202: Runaway Detection Time For Watchdog Timer
CHAPTER 9 WATCHDOG TIMER (1) Watchdog timer mode This mode detects program runaway. When runaway is detected, a nonmaskable interrupt can be generated. Table 9-1. Runaway Detection Time for Watchdog Timer Note Runaway Detection Time /fxx (964 µ s) /fxx (1.928 ms) /fxx (3.855 ms) /fxx (7.710 ms) /fxx (15.42 ms)
Page 203: Configuration
CHAPTER 9 WATCHDOG TIMER 9.2 Configuration The watchdog timer consists of the following hardware. Table 9-3. Watchdog Timer Configuration Item Configuration Control registers Oscillation stabilization time selection register (OSTS) Watchdog timer clock selection register (WDCS) Watchdog timer mode register (WDTM) 9.3 Watchdog Timer Control Register Three registers control the watchdog timer.
Page 204: Format Of Watchdog Timer Clock Selection Register (Wdcs)
CHAPTER 9 WATCHDOG TIMER (2) Watchdog timer clock selection register (WDCS) This register selects the overflow times of the watchdog timer and the interval timer. WDCS is set by an 8-bit memory manipulation instruction. RESET input sets WDCS to 00H. Figure 9-3.
Page 205: Format Of Watchdog Timer Mode Register (Wdtm)
CHAPTER 9 WATCHDOG TIMER (3) Watchdog timer mode register (WDTM) This register sets the operating mode of the watchdog timer, and enables and disables counting. WDTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-4.
Page 206: Operation
CHAPTER 9 WATCHDOG TIMER 9.4 Operation 9.4.1 Operating as watchdog timer Set bit 4 (WDTM4) of the watchdog timer mode register (WDTM) to 1 to operate as a watchdog timer to detect program runaway. Setting bit 7 (RUN) of WDTM to 1 starts the count. After counting starts, if RUN is set to 1 again within the set time interval for runaway detection, the watchdog timer is cleared and counting starts again.
Page 207: Operating As Interval Timer
CHAPTER 9 WATCHDOG TIMER 9.4.2 Operating as interval timer Set bit 4 (WDTM4) to 0 in the watchdog timer mode register (WDTM) to operate the watchdog timer as an interval timer that repeatedly generates interrupts with a preset count value as the interval. When operating as an interval timer, the interrupt mask flag (WDTMK) of the WDTIC register and the priority setting flag (WDTPR0 to WDTPR2) become valid, and a maskable interrupt (INTWDTM) can be generated.
Page 208: Standby Function Control Register
CHAPTER 9 WATCHDOG TIMER 9.5 Standby Function Control Register The wait time from releasing the stop mode until the oscillation stabilizes is controlled by the oscillation stabilization time selection register (OSTS). OSTS is set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 209: Chapter 10 Serial Interface Function
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.1 Overview The V850/SA1 supports the following on-chip serial interfaces. • Channel 0: 3-wire serial I/O (CSI0)/I Either 3-wire serial I/O or I C can be used. C supports multimaster ( µ PD703015Y and 703017Y only). •...
Page 210: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.1 Configuration The CSIn includes the following hardware. Table 10-1. Configuration of CSIn Item Configuration Registers Serial I/O shift register 0-2 (SIO0-SIO2) Control registers Serial operation mode register 0-2 (CSIM0-CSIM2) Serial clock selection register 0-2 (CSIS0-CSIS2) Figure 10-1.
Page 211: Csin Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.2 CSIn control registers The CSIn uses the following type of register for control functions. • Serial operation mode register n (CSIMn) • Serial clock selection register n (CSISn) (1) Serial operation mode register 0-2 (CSIM0-CSIM2) This register is used to enable or disable serial interface channel n’s serial clock, operation modes, and specific operations.
Page 212: Format Of Serial Clock Selection Registers 0-2 (Csis0-Csis2)
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-2. Format of Serial Operation Mode Registers 0-2 (CSIM0-CSIM2) (2/2) Transfer Operation Mode Flag MODEn Operation mode Transfer start trigger SOn output Transmit/receive mode SIOn write Normal output Receive-only mode SIOn read Low level fixed SCLn2 SCLn1 SCLn0...
Page 213: Operations
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.3 Operations The CSIn has the following two operation modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode does not perform serial transfers and can therefore reduce power consumption. If SIn, SOn, and the serial clock pin are selected as I/O ports in operation stop mode, they can be used as normal I/O ports as well.
Page 214: Format Of Serial Operation Mode Registers 0-2 (Csim0-Csim2)
CHAPTER 10 SERIAL INTERFACE FUNCTION (2) 3-wire serial I/O mode 3-wire serial I/O mode is useful when connecting to a peripheral I/O device that includes a clock-synchronous serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line, serial output line (SOn), and serial input line (SIn).
Page 215: Timing Of 3-Wire Serial I/O Mode
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-5. Format of Serial Operation Mode Registers 0-2 (CSIM0-CSIM2) (2/2) SCLn2 SCLn1 SCLn0 Clock Selection External clock input (SCKn) when n = 0 : TO2 when n = 1, 2 : TO3 fxx/8 (2.125 MHz) fxx/16 (1.0626 MHz) fxx/32 (531.3 kHz) fxx/64 (265.6 kHz)
Page 216 CHAPTER 10 SERIAL INTERFACE FUNCTION (iii) Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial I/O shift register n (SIOn). • The SIOn operation control bit (CSIEn) = 1 •...
Page 217: I C Bus ( Μ Μ Μ Μ Pd703015Y, 70F3017Y)
CHAPTER 10 SERIAL INTERFACE FUNCTION C Bus ( µ µ µ µ PD703015Y, 70F3017Y) 10.3 I To use the I C bus function, set the P10/SDA and P12/SCL pins to N-ch open drain output. The I C has the following two modes. •...
Page 218 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-7. Block Diagram of I Internal bus IIC status register (IICS0) MSTS ACKD IIC control register (IICC0) Slave address register (SVA0) IICE LREL WREL SPIE WTIM ACKE Coincidence CLEAR signal Noise elimination circuit SO latch IIC shift register (IIC0) CL1,...
Page 219 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-8 shows a serial bus configuration example. Figure 10-8. Serial Bus Configuration Example Using I C Bus Master CPU2 Serial data bus Master CPU1 Slave CPU2 Serial clock Slave CPU1 Address 1 Slave CPU3 Address 2 Slave IC Address 3...
Page 220: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.1 Configuration The I C includes the following hardware. Table 10-2. Configuration of I Item Configuration Registers IIC shift register (IIC0) Slave address register (SVA0) Control registers IIC control register (IICC0) IIC status register (IICS0) IIC clock select register (IICCL0) IIC shift register (IIC0) IIC0 is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data.
Page 221 CHAPTER 10 SERIAL INTERFACE FUNCTION Serial clock counter This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was sent and/or received. Interrupt request signal generator This circuit controls the generation of interrupt request signals.
Page 222: I C Control Register
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.2 I C control register C is controlled via three types of registers. • IIC control register (IICC0) • IIC status register (IICS0) • IIC clock select register (IICCL0) The following registers are also used. •...
Page 223: Format Of Iic Control Register (Iicc0)
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-9. Format of IIC Control Register (IICC0) (1/4) After reset : 00H Address: FFFFF340H IICC0 IICE LREL WREL SPIE WTIM ACKE IICE C Operation Enable Stops operation. Presets expansion register (IICS). Stops internal operation. Enables operation.
Page 224 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-9. Format of IIC Control Register (IICC0) (2/4) WREL Cancel Wait Does not cancel wait Cancels wait. This setting is automatically cleared after wait is canceled. Note Condition for clearing (WREL = 0) Condition for setting (WREL = 1) •...
Page 225 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-9. Format of IIC Control Register (IICC0) (3/4) ACKE Acknowledge Control Disable acknowledge. Enable acknowledge. During the ninth clock period, the SDA line is set to low level. However, the ACK is invalid during address transfers and is valid when EXC = 1. Note Condition for clearing (ACKE = 0) Condition for setting (ACKE = 1)
Page 226 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-9. Format of IIC Control Register (IICC0) (4/4) Stop Condition Trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA line goes to low level, either set the SCL line to high level or wait until it goes to high level. Next, after the rated amount of time has elapsed, the SDA line is changed from low level to high level and a stop condition is generated.
Page 227: Format Of Iic Status Register (Iics0)
CHAPTER 10 SERIAL INTERFACE FUNCTION (2) IIC status register (IICS0) This register indicates the status of the I C bus. IICS0 can be set by a 1-bit or 8-bit memory manipulation instruction. IICS0 is a read-only register. RESET input sets IICS0 to 00H. Figure 10-10.
Page 228 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-10. Format of IIC Status Register (IICS0) (2/3) Detection of Extension Code Reception Extension code was not received. Extension code was received. Condition for clearing (EXC = 0) Condition for setting (EXC = 1) •...
Page 229 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-10. Format of IIC Status Register (IICS0) (3/3) ACKD Detection of ACK ACK was not detected. ACK was detected. Condition for clearing (ACKD = 0) Condition for setting (ACKD = 1) • When a stop condition is detected •...
Page 230: Format Of Iic Clock Select Register (Iiccl0)
CHAPTER 10 SERIAL INTERFACE FUNCTION (3) IIC clock select register (IICCL0) This register is used to set the transfer clock for the I C bus. IICCL0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets IICCL0 to 00H. Figure 10-11.
Page 231 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-11. Format of IIC Clock Select Register (IICCL0) (2/2) Note Operation Mode Switching × fxx/24 × fxx/24 × fxx/48 × TM2 output/18 fxx/44 fxx/86 fxx/172 TM2 output/66 fxx/46 fxx/88 fxx/176 TM2 output/68 Note The digital filter (DFC) can be used when in high-speed mode. Response time is slower when the digital filter is used.
Page 232: I C Bus Mode Functions
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.3 I C bus mode functions Pin configuration The serial clock pin (SCL) and serial data bus pin (SDA) are configured as follows. SCL ....This pin is used for serial clock input and output. This pin is an N-ch open drain output for both master and slave devices.
Page 233: I C Bus Definitions And Control Methods
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.4 I C bus definitions and control methods The following section describes the I C bus’s serial data communication format and the signals used by the I bus. Figure 10-13 shows the transfer timing for the “start condition”, “data”, and “stop condition” output via the I bus’s serial data bus.
Page 234: Address
CHAPTER 10 SERIAL INTERFACE FUNCTION A start condition is output when the IIC control register (IICC0)’s bit 1 (STT) is set (to “1”) after a stop condition has been detected (SPD: Bit 0 = 1 in the IIC status register (IICS0)). When a start condition is detected, IICS0’s bit 1 (STD) is set (to “1”).
Page 235: Transfer Direction Specification
CHAPTER 10 SERIAL INTERFACE FUNCTION Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting data to a slave device.
Page 236: Ack Signal
CHAPTER 10 SERIAL INTERFACE FUNCTION Acknowledge (ACK) signal The acknowledge (ACK) signal is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data.
Page 237: Stop Condition
CHAPTER 10 SERIAL INTERFACE FUNCTION When the local address is received, an ACK signal is automatically output in synchronization with the falling edge of the SCL’s eighth clock regardless of the ACKE value. No ACK signal is output if the received address is not a local address.
Page 238: Wait Signal
CHAPTER 10 SERIAL INTERFACE FUNCTION Wait signal The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL pin to low level notifies the communication partner of the wait status. When wait status has been canceled for both the master and slave devices, the next data transfer can begin.
Page 239 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-19. Wait Signal (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKE = 1) Master and slave both wait Master after output of ninth clock. IIC0 data write (cancel wait) IIC0 Slave...
Page 240: I C Interrupt Requests (Intiic0)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.5 I C interrupt requests (INTIIC0) The INTIIC0 interrupt request timing and the IIC status register (IICS0) settings corresponding to that timing are described below. (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ ~ Stop (normal transmission/reception) <1>...
Page 241 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIM = 0 AD6-AD0 D7-D0 AD6-AD0 D7-D0 ∆5 1 : IICS0 = 10XXX110B 2 : IICS0 = 10XXX000B 3 : IICS0 = 10XXX110B 4 : IICS0 = 10XXX000B ∆...
Page 242 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIM = 0 AD6-AD0 D7-D0 D7-D0 ∆4 1 : IICS0 = 1010X110B 2 : IICS0 = 1010X000B 3 : IICS0 = 1010X000B ∆...
Page 243 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Slave device operation (when receiving slave address data (matches with SVA0)) (a) Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIM = 0 AD6-AD0 D7-D0 D7-D0 ∆4 1 : IICS0 = 0001X110B 2 : IICS0 = 0001X000B 3 : IICS0 = 0001X000B ∆...
Page 244 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM = 0 (after restart, matches with SVA0) AD6-AD0 D7-D0 AD6-AD0 D7-D0 ∆5 1 : IICS0 = 0001X110B 2 : IICS0 = 0001X000B 3 : IICS0 = 0001X110B 4 : IICS0 = 0001X000B ∆...
Page 245 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIM = 0 (after restart, extension code reception) AD6-AD0 D7-D0 AD6-AD0 D7-D0 ∆5 1 : IICS0 = 0001X110B 2 : IICS0 = 0001X000B 3 : IICS0 = 0010X010B 4 : IICS0 = 0010X000B ∆...
Page 246 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM = 0 (after restart, does not match with address (= not extension code)) AD6-AD0 D7-D0 AD6-AD0 D7-D0 ∆4 1 : IICS0 = 0001X110B 2 : IICS0 = 0001X000B 3 : IICS0 = 0000XX10B...
Page 247 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Slave device operation (when receiving extension code) (a) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIM = 0 AD6-AD0 D7-D0 D7-D0 ∆4 1 : IICS0 = 0010X010B 2 : IICS0 = 0010X000B 3 : IICS0 = 0010X000B ∆...
Page 248 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM = 0 (after restart, matches with SVA0) AD6-AD0 D7-D0 AD6-AD0 D7-D0 ∆5 1 : IICS0 = 0010X010B 2 : IICS0 = 0010X000B 3 : IICS0 = 0001X110B 4 : IICS0 = 0001X000B ∆...
Page 249 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIM = 0 (after restart, extension code reception) AD6-AD0 D7-D0 AD6-AD0 D7-D0 ∆5 1 : IICS0 = 0010X010B 2 : IICS0 = 0010X000B 3 : IICS0 = 0010X010B 4 : IICS0 = 0010X000B ∆...
Page 250 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM = 0 (after restart, does not match with address (= not extension code)) AD6-AD0 D7-D0 AD6-AD0 D7-D0 ∆4 1 : IICS0 = 0010X010B 2 : IICS0 = 0010X000B 3 : IICS0 = 00000X10B...
Page 251 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6-AD0 D7-D0 D7-D0 ∆1 ∆ 1 : IICS0 = 00000001B ∆ : Generated only when SPIE = 1 Remark (5) Arbitration loss operation (operation as slave after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data <1>...
Page 252 CHAPTER 10 SERIAL INTERFACE FUNCTION <2> When WTIM = 1 AD6-AD0 D7-D0 D7-D0 ∆4 1 : IICS0 = 0101X110B (Example: when ALD is read during interrupt servicing) 2 : IICS0 = 0001X100B 3 : IICS0 = 0001XX00B ∆ 4 : IICS0 = 00000001B Remarks : Always generated ∆...
Page 253 CHAPTER 10 SERIAL INTERFACE FUNCTION <2> When WTIM = 1 AD6-AD0 D7-D0 D7-D0 ∆5 1 : IICS0 = 0110X010B (Example: when ALD is read during interrupt servicing) 2 : IICS0 = 0010X110B 3 : IICS0 = 0010X100B 4 : IICS0 = 0010XX00B ∆...
Page 254 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) When arbitration loss occurs during data transfer <1> When WTIM = 0 AD6-AD0 D7-D0 D7-D0 ∆3 1 : IICS0 = 10001110B 2 : IICS0 = 01000000B (Example: when ALD is read during interrupt servicing) ∆...
Page 255 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) When loss occurs due to restart condition during data transfer <1> Not extension code (Example: matches with SVA0) AD6-AD0 D7-Dn AD6-AD0 D7-D0 ∆3 1 : IICS0 = 1000X110B 2 : IICS0 = 01000110B (Example: when ALD is read during interrupt servicing) ∆...
Page 256 CHAPTER 10 SERIAL INTERFACE FUNCTION (e) When loss occurs due to stop condition during data transfer AD6-AD0 D7-Dn ∆2 1 : IICS0 = 1000X110B ∆ 2 : IICS0 = 01000001B Remarks : Always generated ∆ : Generated only when SPIE = 1 X : don’t care Dn = D6-D0 (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition...
Page 257 CHAPTER 10 SERIAL INTERFACE FUNCTION <2> When WTIM = 1 STT = 1 ↓ AD6-AD0 D7-D0 D7-D0 D7-D0 ∆4 1 : IICS0 = 1000X110B 2 : IICS0 = 1000XX00B 3 : IICS0 = 01000100B (Example: when ALD is read during interrupt servicing) ∆...
Page 258 CHAPTER 10 SERIAL INTERFACE FUNCTION <2> When WTIM = 1 STT = 1 ↓ AD6-AD0 D7-D0 ∆3 1 : IICS0 = 1000X110B 2 : IICS0 = 1000XX00B ∆ 3 : IICS0 = 01000001B Remarks : Always generated ∆ : Generated only when SPIE = 1 X : don’t care (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition <1>...
Page 259 CHAPTER 10 SERIAL INTERFACE FUNCTION <2> When WTIM = 1 SPT = 1 ↓ AD6-AD0 D7-D0 D7-D0 D7-D0 ∆4 1 : IICS0 = 1000X110B 2 : IICS0 = 1000XX00B 3 : IICS0 = 01000000B (Example: when ALD is read during interrupt servicing) ∆...
Page 260: Interrupt Request (Intiic0) Generation Timing And Wait Control
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.6 Interrupt request (INTIIC0) generation timing and wait control The setting of bit 3 (WTIM) in the IIC control register (IICC0) determines the timing by which INTIIC0 is generated and the corresponding wait control, as shown in Table 10-3. Table 10-3.
Page 261: Address Match Detection Method
CHAPTER 10 SERIAL INTERFACE FUNCTION (1) During address transmission/reception • Slave device operation : Interrupt and wait timing are determined regardless of the WTIM bit. • Master device operation : Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the WTIM bit.
Page 262: Error Detection
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.8 Error detection During I C bus mode, the status of the serial data bus (SDA) during data transmission is captured by the IIC shift register (IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0 data to enable detection of transmission errors.
Page 263: Arbitration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.10 Arbitration When several master devices simultaneously output a start condition (when STT is set to 1 before STD is set to Note ), communication among the master devices is performed as the number of clocks are adjusted until the data differs.
Page 264: Arbitration Timing Example
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-20. Arbitration Timing Example Master 1 Hi-Z Hi-Z Master 1 loses arbitration Master 2 Transfer lines Table 10-5. Status during Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 During address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission...
Page 265: Wake Up Function
CHAPTER 10 SERIAL INTERFACE FUNCTION Notes 1. When WTIM (bit 3 of the IIC control register IICC0) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIM = 0 and the extension code’s slave address is received, an interrupt request occurs at the falling edge of the eighth clock.
Page 266: Communication Reservation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.12 Communication reservation To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
Page 267: Communication Reservation Timing
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21 shows the communication reservation timing. Figure 10-21. Communication Reservation Timing Write to Program processing IIC0 Set SPD Communication Hardware processing reservation and INTIIC0 Output by master with bus access IIC0 : IIC shift register STT : Bit 1 of IIC control register (IICC0) STD : Bit 1 of IIC status register (IICS0) SPD : Bit 0 of IIC status register (IICS0)
Page 268: Timing For Accepting Communication Reservations
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Timing for Accepting Communication Reservations Standby mode...
Page 269: Communication Reservation Flow Chart
CHAPTER 10 SERIAL INTERFACE FUNCTION The communication reservation flow chart is illustrated in Figure 10-23. Figure 10-23. Communication Reservation Flow Chart Sets STT flag (communication reservation). SET1 STT Define communication Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM). Gets wait period set by software (see Table 10-6).
Page 270: Other Cautions
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.13 Other cautions After a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.
Page 271: Communication Operations
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.14 Communication operations Master operations The following is a flow chart of the master operations. Figure 10-24. Master Operation Flow Chart START IICCL0 ← ××H Select transfer clock. IICC0 ← ××H IICE=SPIE=WTIM=1 INTIIC0=1? Stop condition detection Start IIC0 write transfer.
Page 272: Slave Operation Flow Chart
CHAPTER 10 SERIAL INTERFACE FUNCTION Slave operation An example of slave operation is shown below. Figure 10-25. Slave Operation Flow Chart START IICC0 ← ××H IICE=1 INTIIC0=1? EXC=1? Communicate? COI=1? LREL=1 TRC=1? WTIM=0 ACKE=1 WTIM=1 Start IIC0 write transfer. WREL=1 Start reception.
Page 273: Timing Of Data Communication
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.15 Timing of data communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC bit (bit 3 of the IIC status register (IICS0)) that specifies the data transfer direction and then starts serial communication with the slave device.
Page 274 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-26. Example of Master to Slave Communication (when 9-clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device IIC0 ← address IIC0 ← data IIC0 ACKD WTIM ACKE...
Page 275 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-26. Example of Master to Slave Communication (when 9-clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IIC0 ← data IIC0 ← data IIC0 ACKD WTIM ACKE MSTS WREL INTIIC0...
Page 276 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-26. Example of Master to Slave Communication (when 9-clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device IIC0 ← data IIC0 ← address IIC0 ACKD WTIM ACKE MSTS WREL...
Page 277 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-27. Example of Slave to Master Communication (when 9-clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device IIC0 ← address IIC0 ← FFH Note IIC0 ACKD WTIM...
Page 278 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-27. Example of Slave to Master Communication (when 9-clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IIC0 ← FFH Note IIC0 ← FFH Note IIC0 ACKD WTIM ACKE MSTS...
Page 279 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-27. Example of Slave to Master Communication (when 9-clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device IIC0 ← address IIC0 IIC0← FFH Note ACKD WTIM ACKE MSTS Note...
Page 280: Asynchronous Serial Interface (Uart0, Uart1)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4 Asynchronous Serial Interface (UART0, UART1) The UARTn (n = 0, 1) has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
Page 281: Block Diagram Of Uartn
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-28. Block Diagram of UARTn Internal Bus Receive buffer register 0, 1 (RXB0, RXB1) Receive shift register RXD0, RXD1 0, 1 (RX0, RX1) Transmit shift register TXD0, TXD1 0, 1 (TXS0, TXS1) Receive control INTSR0, parity check INTSR1...
Page 282: Uartn Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Receive buffer register 0, 1 (RXB0, RXB1) This register is used to hold receive data. When one byte of data is received, one byte of new receive data is transferred. When the data length is set as 7 bits, receive data is sent to bit 0 to bit 6 of RXBn. In RXBn, the MSB must be set to “0”.
Page 283: Format Of Asynchronous Serial Interface Mode Register 0, 1 (Asim0, Asim1)
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-29. Format of Asynchronous Serial Interface Mode Register 0, 1 (ASIM0, ASIM1) After reset: Address: FFFFF300H, FFFFF310H ASIMn TXEn RXEn PS1n PS0n UCLn ISRMn (n = 0, 1) RxDn/PXX Pin TxDn/PXX Pin TXEn RXEn Operation Mode Function Function...
Page 284: Format Of Asynchronous Serial Interface Status Registers 0, 1 (Asis0, Asis1)
CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1) When a receive error occurs during UARTn mode, these registers indicate the type of error. ASISn can be read using a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to 00H.
Page 285: Format Of Baud Rate Generator Control Registers 0, 1 (Brgc0, Brgc1)
CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Baud rate generator control registers 0, 1 (BRGC0, BRGC1) These registers set the serial clock for UARTn. BRGCn can be set by an 8-bit memory manipulation instruction. RESET input sets these registers to 00H. Figure 10-31 shows the format of BRGCn.
Page 286: Format Of Baud Rate Generator Mode Control Registers 0, 1 (Brgmc0, Brgmc1)
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-32. Format of Baud Rate Generator Mode Control Registers 0, 1 (BRGMC0, BRGMC1) After reset: 00H Address: FFFFF30EH, FFFFF31EH BRGMCn TPSn2 TPSn1 TPSn0 (n = 0, 1) TPSn2 TPSn1 TPSn0 8-bit Counter Source Clock Selection −...
Page 287: Operations
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.3 Operations The UARTn has the following two operation modes. • Operation stop mode • Asynchronous serial interface (UARTn) mode (1) Operation stop mode This mode does not perform serial transfers and can therefore be used to reduce power consumption. When in operation stop mode, pins can be used as ordinary ports.
Page 288: Asynchronous Serial Interface (Uartn) Mode
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.4 Asynchronous serial interface (UARTn) mode This mode enables full-duplex operation which transmits and receives one byte of data after the start bit. The on-chip dedicated UARTn baud rate generator enables communications using a wide range of selectable baud rates.
Page 289 CHAPTER 10 SERIAL INTERFACE FUNCTION (i) Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1) ASIMn can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to 00H. After reset: 00H Address: FFFFF300H, FFFFF310H ASIMn TXEn RXEn...
Page 290 CHAPTER 10 SERIAL INTERFACE FUNCTION (ii) Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1) ASISn can be read using a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to 00H. After reset: 00H Address: FFFFF302H, FFFFF312H ASISn OVEn (n = 0, 1)
Page 291 CHAPTER 10 SERIAL INTERFACE FUNCTION (iii) Baud rate generator control registers 0, 1 (BRGC0, BRGC1) BRGCn can be set by an 8-bit memory manipulation instruction. RESET input sets these registers to 00H. After reset: 00H Address: FFFFF304H, FFFFF314H BRGCn MDLn7 MDLn6 MDLn5 MDLn4...
Page 292 CHAPTER 10 SERIAL INTERFACE FUNCTION (iv) Baud rate generator mode control registers 0, 1 (BRGMC0, BRGMC1) BRGMCn is set by 8-bit memory manipulation instruction. RESET input sets these registers to 00H. After reset: 00H Address: FFFFF30EH, FFFFF31EH BRGMCn TPSn2 TPSn1 TPSn0 (n = 0, 1) TPSn2...
Page 293: Relation Between Main Clock And Baud Rate
CHAPTER 10 SERIAL INTERFACE FUNCTION The baud rate transmit/receive clock that is generated is obtained by dividing the main clock. • Generation of baud rate transmit/receive clock using main clock The transmit/receive clock is obtained by dividing the main clock. The following equation is used to obtain the baud rate from the main clock.
Page 294: Error Tolerance (When K = 0), Including Sampling Errors
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-33. Error Tolerance (when k = 0), including Sampling Errors Ideal sampling point 256T 288T 320T 352T 304T 336T Basic timing START STOP (clock cycle T) 15.5T High-speed clock (clock cycle T’) START STOP enabling normal Sampling error reception...
Page 295: Format Of Transmit/Receive Data In Asynchronous Serial Interface
CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Communication operations (i) Data format As shown in Figure 10-34, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. The asynchronous serial interface mode register (ASIMn) is used to set the character bit length, parity selection, and stop bit length within each data frame (n = 0, 1).
Page 296 CHAPTER 10 SERIAL INTERFACE FUNCTION (ii) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd- number bit) can be detected.
Page 297: Timing Of Asynchronous Serial Interface Transmit Completion Interrupt
CHAPTER 10 SERIAL INTERFACE FUNCTION No parity No parity bit is added to the transmit data. During reception, receive data is regarded as having no parity bit. Since there is no parity bit, no parity errors will be generated. (iii) Transmission The transmit operation is started when transmit data is written to the transmit shift register (TXSn).
Page 298: Timing Of Asynchronous Serial Interface Receive Completion Interrupt
CHAPTER 10 SERIAL INTERFACE FUNCTION (iv) Reception The receive operation is enabled when “1” is set to bit 6 (RXEn) of the asynchronous serial interface mode register (ASIMn), and input via the RxDn pin is sampled. The serial clock specified by ASIMn is used when sampling the RxDn pin. When the RxDn pin goes low, the 5-bit counter begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed.
Page 299: Receive Error Timing
CHAPTER 10 SERIAL INTERFACE FUNCTION (v) Receive error There are three types of error during the receive operation, pariy error, framing error, and overrun error. When, as the result of data receive, an error flag is set in the asynchronous serial interface status register (ASISn), the receive error interrupt request (INTSERn) is generated.
Page 300: Standby Function
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.5.5 Standby function (1) Operation in HALT mode Serial transmission is performed normally. (2) Operation in STOP and IDLE modes (a) When internal clock is selected as serial clock The operations of asynchronous serial interface mode register n (ASIMn), transmit shift register n (TXSn), and receive buffer register n (RXBn) are stopped and their values immediately before the clock stopped are hold.
Page 301: Chapter 11 A/D Converter
CHAPTER 11 A/D CONVERTER 11.1 Function The A/D converter converts analog input signals into digital values with a resolution of 10 bits, and can handle 12 channels of analog input signals (ANI0 through ANI11). The V850/SA1 supports the low-power-dissipation mode by low-speed conversion. (1) Hardware start Conversion is started by trigger input (ADTRG) (rising edge, falling edge, or both rising and falling edges can be specified).
Page 302: Block Diagram Of A/D Converter
CHAPTER 11 A/D CONVERTER Figure 11-1 shows the block diagram. Figure 11-1. Block Diagram of A/D Converter ANI0 ANI1 ANI2 Sample & hold circuit ANI3 ANI4 Voltage comparator ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 Successive ANI11 approximation register (SAR) Edge Control ADTRG detection...
Page 303: Configuration
CHAPTER 11 A/D CONVERTER 11.2 Configuration The A/D converter consists of the following hardware units. Table 11-1. Configuration of A/D Converter Item Configuration Analog input 12 channels (ANI0 through ANI11) Register Successive approximation register (SAR) A/D conversion result register (ADCR) A/D conversion result register H (ADCRH): only high-order 8 bits can be read Control register...
Page 304 CHAPTER 11 A/D CONVERTER (6) ANI0 through ANI11 pins These are analog input pins for the 12 channels of the A/D converter, and are used to input analog signals to be converted into digital signals. Pins other than ones selected as analog input with the analog input channel specification register (ADS) can be used as input ports.
Page 305: Control Registers
CHAPTER 11 A/D CONVERTER 11.3 Control Registers The A/D converter is controlled by the following two registers: • A/D converter mode register (ADM) • Analog input channel specification register (ADS) (1) A/D converter mode register (ADM) This register specifies the conversion time of the input analog signal to be converted into a digital signal, starting or stopping the conversion, and an external trigger.
Page 306 CHAPTER 11 A/D CONVERTER Figure 11-2. Format of A/D Converter Mode Register (ADM) (2/2) ADPS Conversion Time Selection Clock number at fxx = 17 MHz at fxx = 8 MHz 16.9 µ s 36.0 µ s 288/fxx 12.7 µ s 27.0 µ...
Page 307: Format Of Analog Input Channel Specification Register (Ads)
CHAPTER 11 A/D CONVERTER (2) Analog input channel specification register (ADS) ADS specifies the port for inputting an analog voltage to be converted into a digital signal. ADS is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADS to 00H. Figure 11-3.
Page 308: Operation
CHAPTER 11 A/D CONVERTER 11.4 Operation 11.4.1 Basic operation <1> Select one channel whose analog signal is to be converted into a digital signal by using the analog input channel specification register (ADS). <2> The sample & hold circuit samples the voltage input to the selected analog input channel. <3>...
Page 309: Basic Operation Of A/D Converter
CHAPTER 11 A/D CONVERTER Figure 11-4. Basic Operation of A/D Converter Conversion time Sampling time Operation of Sampling A/D conversion A/D converter Conversion Undefined result Conversion ADCR result INTAD A/D conversion is successively executed until the bit 7 (ADCS) of the A/D converter mode register (ADM) is reset to 0 by software.
Page 310: Input Voltage And Conversion Result
CHAPTER 11 A/D CONVERTER 11.4.2 Input voltage and conversion result The analog voltages input to the analog input pins (ANI0 through ANI11) and the result of the A/D conversion (contents of the A/D conversion result register (ADCR)) are related as follows: ×...
Page 311: A/D Converter Operation Mode
CHAPTER 11 A/D CONVERTER 11.4.3 A/D converter operation mode In this mode one of the analog input channels ANI0 through ANI11 is selected by the analog input channel specification register (ADS) and A/D conversion is executed. The A/D conversion can be started in the following two ways: •...
Page 312: A/D Conversion By Hardware Start (With Falling Edge Specified)
CHAPTER 11 A/D CONVERTER (1) A/D conversion by hardware start A/D conversion is on standby if bit 6 (TRG) and bit 7 (ADCS) of the A/D converter mode register (ADM) are set to 1. When an external trigger signal is input, the A/D converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) into a digital signal.
Page 313: A/D Conversion By Software Start
CHAPTER 11 A/D CONVERTER (2) A/D conversion by software start If bit 6 (TRG) and bit 7 (ADCS) of the A/D converter mode register (ADM) are set to 1, the A/D converter starts converting the voltage applied to an analog input pin specified by the analog input channel specification register (ADS) into a digital signal.
Page 314: Notes On Using A/D Converter
CHAPTER 11 A/D CONVERTER 11.5 Notes on Using A/D Converter (1) Current consumption in standby mode The A/D converter stops operation in the STOP and IDLE mode (operable at the HALT mode). At this time, the current consumption of the A/D converter can be reduced by stopping the conversion (by resetting the bit 7 (ADCS) of the A/D converter mode register (ADM) to 0).
Page 315: Processing Of Analog Input Pin
CHAPTER 11 A/D CONVERTER (4) Countermeasures against noise To keep the resolution of 10 bits, prevent noise from being superimposed on the AV and ANI0 through ANI11 pins. The higher the output impedance of the analog input source, the heavier the influence of noise. To lower noise, connecting an external capacitor as shown in Figure 11-8 is recommended.
Page 316: A/D Conversion End Interrupt Generation Timing
CHAPTER 11 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the analog input channel specification register (ADS) are changed. If the analog input pin is changed during conversion, therefore, the result of the A/D conversion of the preceding analog input signal and the conversion end interrupt request flag may be set immediately before ADS is rewritten.
Page 317: Chapter 12 Dma Functions
CHAPTER 12 DMA FUNCTIONS 12.1 Functions The DMA (Direct Memory Access) controller transfers data between memory and peripheral I/Os based on DMA requests sent from on-chip peripheral hardware (such as the serial interface, timer, or A/D converter). This product includes three independent DMA channels that can transfer data in 8-bit and 16-bit units. The maximum number of transfers is 256 and transfers are enabled only in single transfer mode.
Page 318: Format Of Dma On-Chip Ram Address Registers 0 To 2 (Dra0 To Dra2)
CHAPTER 12 DMA FUNCTIONS (2) DMA on-chip RAM address registers 0 to 2 (DRA0 to DRA2) These registers are used to set the on-chip RAM address for DMA channel n. An incrementation function is provided. The incrementation value is “1” during 8-bit transfers and “2” during 16-bit transfers. The following DMA transfer addresses are retained during DMA transfers.
Page 319: Format Of Dma Channel Control Registers 0 To 2 (Dchc0 To Dchc2)
CHAPTER 12 DMA FUNCTIONS (4) DMA channel control registers 0 to 2 (DCHC0 to DCHC2) These registers are used to control the DMA transfer operation mode for DMA channel n. Read and write in 8-bit units and bitwise are enabled. Figure 12-4.
Page 320 CHAPTER 12 DMA FUNCTIONS Figure 12-4. Format of DMA Channel Control Registers 0 to 2 (DCHC0 to DCHC2) (2/2) Note TDIRn Transfer Direction Control Between Peripheral I/Os and On-Chip RAM From on-chip RAM to peripheral I/Os From peripheral I/Os to on-chip RAM Note Control of Transfer Data Size for DMA Transfer 8-bit transfer...
Page 321: Chapter 13 Real-Time Output Function (Rto)
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.1 Function A function to transfer data set in advance to a real-time output buffer to an output latch by hardware to output the data to an external device as soon as an external interrupt or external trigger have occurred is called a real-time output function.
Page 322: Configuration
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.2 Configuration RTO consists of the following hardware. Table 13-1. Configuration of RTO Item Configuration Register Real-time output buffer register (RTBL, RTBH) Control register Real-time output port mode register (RTPM) Real-time output port control register (RTPC) (1) Real-time output buffer registers (RTBL, RTBH) RTBL and RTBH are 4-bit registers that hold output data in advance.
Page 323: Rto Control Registers
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) Table 13-2. Operation When Real-Time Output Buffer Registers Are Manipulated Note 1 Note 2 Read Write Operation Mode Register to Be Manipulated High-order 4 Low-order 4 bits High-order 4 Low-order 4 bits bits bits 4 bits ×...
Page 324: Format Of Real-Time Output Port Mode Register (Rtpm)
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (1) Real-time output port mode register (RTPM) This register selects real-time output port mode or port mode in 1-bit units. RTPM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears RTPM to 00H. Figure 13-3.
Page 325: Format Of Real-Time Output Port Control Register (Rtpc)
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register (RTPC) This register sets the operation mode and output trigger of the real-time output port. The relation between the operation mode and output trigger of the real-time output port is as shown in Table 13-3. RTPC is set by a 1-bit or 8-bit memory manipulation instruction.
Page 326: Operation
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.4 Operation If the real-time output operation is enabled by setting the bit 7 (RTPOE) of the real-time output port control register (RTPC) to 1, the data of the real-time output buffer registers (RTBH and RTBL) is transferred to the output latch in Note synchronization with the generation of the selected trigger (set by EXTR and BYTE ).
Page 327: Usage
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.5 Usage (1) Disable the real-time output operation. Clear bit 7 (RTPOE) of the real-time output port control register (RTPC) to 0. (2) Initialization • Set the initial value to the output latch. • Specify the real-time output port mode or port mode in 1-bit units. Set the real-time output port mode register (RTPM).
Page 328 [MEMO]...
Page 329: Chapter 14 Port Function
CHAPTER 14 PORT FUNCTION 14.1 Port Configuration V850/SA1 incorporates 85 I/O ports in total from port 0 to 12 (13 out of 85 are input-only port). 14.2 Port Pin Function 14.2.1 Port 0 Port 0 is an 8-bit I/O port for which I/O settings can be controlled bitwise. A pull-up resistance can be connected bitwise (software pull-up function).
Page 330 CHAPTER 14 PORT FUNCTION (1) Function of P0 pins Port 0 is an 8-bit I/O port for which I/O settings can be controlled bitwise. I/O settings are controlled via the port 0 mode register (PM0). During output mode, the values set to each bit are output to the port register (P0). When using this port in output mode, either the valid edge of each interrupt request should be made invalid or each interrupt request should be masked (except for NMI requests).
Page 331: Format Of Port 0 Mode Register (Pm0)
CHAPTER 14 PORT FUNCTION (3) Control registers (a) Port 0 mode register (PM0) Read and write in 8-bit units and bitwise are enabled. Figure 14-2. Format of Port 0 Mode Register (PM0) After reset: Address: FFFFF020H PM07 PM06 PM05 PM04 PM03 PM02 PM01...
Page 332: Format Of Rising Edge Enable Register (Egp0)
CHAPTER 14 PORT FUNCTION (c) Rising edge enable register (EGP0) Read and write in 8-bit units and bitwise are enabled. Figure 14-4. Format of Rising Edge Enable Register (EGP0) After reset: Address: FFFFF0C0H EGP0 EGP07 EGP06 EGP05 EGP04 EGP03 EGP02 EGP01 EGP00 EGP0n...
Page 333: Port 1
CHAPTER 14 PORT FUNCTION 14.2.2 Port 1 Port 1 is a 6-bit I/O port for which I/O settings can be controlled bitwise. A pull-up resistance can be connected bitwise (software pull-up function). Bits 0, 1, 2, 4, and 5 are selectable as normal outputs or N-ch open drain outputs. Figure 14-6.
Page 334: Format Of Port 1 Mode Register (Pm1)
CHAPTER 14 PORT FUNCTION (1) Function of P1 pins Port 1 is a 6-bit I/O port for which I/O settings can be controlled bitwise. I/O settings are controlled via the port 1 mode register (PM1). During output mode, the values set to each bit are output to the port register (P1). The port 1 function register (PF1) can be used to specify whether P10 to P12, P14, and P15 are normal outputs or N-ch open-drain outputs.
Page 335: Format Of Pull-Up Resistance Option Register 1 (Pu1)
CHAPTER 14 PORT FUNCTION (b) Pull-up resistance option register 1 (PU1) Read and write in 8-bit units and bitwise are enabled. Figure 14-8. Format of Pull-up Resistance Option Register 1 (PU1) After reset: Address: FFFFF082H PU15 PU14 PU13 PU12 PU11 PU10 PU1n Control of On-Chip Pull-Up Resistance Connection...
Page 336: Port 2
CHAPTER 14 PORT FUNCTION 14.2.3 Port 2 Port 2 is an 8-bit I/O port for which I/O settings can be controlled bitwise. A pull-up resistance can be connected bitwise (software pull-up function). P21 and P22 are selectable as normal outputs or N-ch open drain outputs. When P26 and P27 are used as TI2/TI3 pins, noise is eliminated from these pins by a digital noise elimination circuit.
Page 337: Format Of Port 2 Mode Register (Pm2)
CHAPTER 14 PORT FUNCTION (1) Function of P2 pins Port 2 is an 8-bit I/O port for which I/O settings can be controlled bitwise. I/O settings are controlled via the port 2 mode register (PM2). During output mode, the values set to each bit are output to the port 2 register (P2). The port function register (PF2) can be used to specify whether P21 and P22 are normal outputs or N-ch open-drain outputs.
Page 338: Format Of Pull-Up Resistance Option Register 2 (Pu2)
CHAPTER 14 PORT FUNCTION (b) Pull-up resistance option register 2 (PU2) Read and write in 8-bit units and bitwise are enabled. Figure 14-12. Format of Pull-up Resistance Option Register 2 (PU2) After reset: Address: FFFFF084H PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20...
Page 339: Port 3
CHAPTER 14 PORT FUNCTION 14.2.4 Port 3 Port 3 is an 8-bit I/O port for which I/O settings can be controlled bitwise. A pull-up resistance can be connected bitwise (software pull-up function). Figure 14-14. Format of Port 3 (P3) After reset: Address: FFFFF006H Control of Output Data (During Output Mode) Output “0”...
Page 340: Format Of Port 3 Mode Register (Pm3)
CHAPTER 14 PORT FUNCTION (1) Function of P3 pins Port 3 is an 8-bit I/O port for which I/O settings can be controlled bitwise. I/O settings are controlled via the port 3 mode register (PM3). During output mode, the values set to each bit are output to the port register (P3). When using this port in input mode, the pin statuses can be read by reading the P3 register.
Page 341: Ports 4 And 5
CHAPTER 14 PORT FUNCTION (b) Pull-up resistance option register 3 (PU3) Read and write in 8-bit units and bitwise are enabled. Figure 14-16. Format of Pull-up Resistance Option Register 3 (PU3) After reset: Address: FFFFF086H PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30...
Page 342 CHAPTER 14 PORT FUNCTION Note Pin Name Alternate Function PULL Remark − Port 4 − Port 5 AD10 AD11 AD12 AD13 AD14 AD15 Note Software pull-up function (1) Functions of P4 and P5 pins Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled bitwise. I/O settings are controlled via port 4 mode register (PM4) and port 5 mode register (PM5).
Page 343: Port 6
CHAPTER 14 PORT FUNCTION (2) Control registers (a) Port 4 mode register and port 5 mode register (PM4 and PM5) Read and write in 8-bit units and bitwise are enabled. Figure 14-18. Format of Port 4 Mode Register, Port 5 Mode Register (PM4, PM5) After reset: Address: FFFFF028H, FFFFF02AH PMn7...
Page 344: Format Of Port 6 Mode Register (Pm6)
CHAPTER 14 PORT FUNCTION Note Pin Name Alternate Function PULL Remark Port 6 Note Software pull-up function (1) Function of P6 pins Port 6 is a 6-bit I/O port for which I/O settings can be controlled bitwise. I/O settings are controlled via the port 6 mode register (PM6).
Page 345: Ports 7 And 8
CHAPTER 14 PORT FUNCTION 14.2.7 Ports 7 and 8 Port 7 is an 8-bit input port and port 8 is a 4-bit input port. Both ports are read-only and are accessible in 8-bit units or bitwise. Figure 14-21. Format of Ports 7 and 8 (P7 and P8) After reset: undefined Address: FFFFF00EH...
Page 346: Port 9
CHAPTER 14 PORT FUNCTION (1) Functions of P7 and P8 pins Port 7 is an 8-bit input-only port and port 8 is a 4-bit input-only port. The pin statuses can be read by reading the port registers (P7 and P8). Data cannot be written to P7 or P8. A software pull-up function is not implemented.
Page 347: Format Of Port 9 Mode Register (Pm9)
CHAPTER 14 PORT FUNCTION (1) Function of P9 pins Port 9 is a 7-bit I/O port for which I/O settings can be controlled bitwise. I/O settings are controlled via the port 9 mode register (PM9). During output mode, the values set to each bit are output to the port register (P9). When using this port in input mode, the pin statuses can be read by reading the P9 register.
Page 348: Port 10
CHAPTER 14 PORT FUNCTION 14.2.9 Port 10 Port 10 is an 8-bit I/O port for which I/O settings can be controlled bitwise. A pull-up resistance can be connected bitwise (software pull-up function). The pins in this port are selectable as normal outputs or N-ch open drain outputs. Figure 14-24.
Page 349: Format Of Port 10 Mode Register (Pm10)
CHAPTER 14 PORT FUNCTION (1) Function of P10 pins Port 10 is an 8-bit I/O port for which I/O settings can be controlled bitwise. I/O settings are controlled via the port 10 mode register (PM10). During output mode, the values set to each bit are output to the port register (P10). The port 10 function register (PF10) can be used to specify whether outputs are normal outputs or N-ch open-drain outputs.
Page 350: Port 11
CHAPTER 14 PORT FUNCTION (b) Pull-up resistance option register 10 (PU10) Read and write in 8-bit units and bitwise are enabled. Figure 14-26. Format of Pull-up Resistance Option Register 10 (PU10) After reset: Address: FFFFF094H PU10 PU107 PU106 PU105 PU104 PU103 PU102 PU101...
Page 351: Format Of Port 11 (P11)
CHAPTER 14 PORT FUNCTION Figure 14-28. Format of Port 11 (P11) After reset: Address: FFFFF016H P114 P113 P112 P111 P110 P11n Control of Output Data (during output mode) Output “0” Output “1” n = 0 − 3 P114 Read Pin Level Read pin level of P114 Remark During input mode : When the P11 register is read, the pin levels at that time are read.
Page 352: Format Of Port 11 Mode Register (Pm11)
CHAPTER 14 PORT FUNCTION A pull-up resistance can be connected bitwise for P110 to P113 when specified via the pull-up resistance option register 11 (PU11). When using the alternate function as A1 to A4 pins, set the pin functions via the memory address output mode register (MAM).
Page 353: Port 12
CHAPTER 14 PORT FUNCTION 14.2.11 Port 12 Port 12 is a 1-bit I/O port. Figure 14-31. Format of Port 12 (P12) After reset: Address: FFFFF018H P120 P120 Control of Output Data (during output mode) Output “0” Output “1” Remark During input mode : When the P12 register is read, the pin level at that time is read. Writing to P12 writes the current pin level to that register.
Page 354: Format Of Port 12 Mode Register (Pm12)
CHAPTER 14 PORT FUNCTION (1) Function of P12 pins Port 12 is a 1-bit I/O port for which the I/O setting can be controlled bitwise. The I/O setting is controlled via the port 12 mode register (PM12). During output mode, the values set to each bit are output to the port register (P12). When using this port in input mode, the pin status can be read by reading the P12 register.
Page 355: Format Of Port 12 Mode Control Register (Pmc12)
CHAPTER 14 PORT FUNCTION (b) Port 12 mode control register (PMC12) Read and write in 8-bit units and bitwise are enabled. Figure 14-33. Format of Port 12 Mode Control Register (PMC12) After reset: Address: FFFFF058H PMC12 PMC120 PMC120 Switching of Alternate Function Use as port mode Use as WAIT pin...
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Page 357: Chapter 15 Reset Function
CHAPTER 15 RESET FUNCTION 15.1 General When low-level input occurs at the RESET pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings. In addition, oscillation of the main clock is stopped during the reset period, although oscillation of the sub clock continues.
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Page 359: Chapter 16 Flash Memory ( Μ Μ Μ Μ Pd70F3017, 70F3017Y)
FLASH MEMORY ( µ µ µ µ PD70F3017, 70F3017Y) CHAPTER 16 The µ PD70F3017 and 70F3017Y of the V850/SA1 are provided with a 256-Kbyte flash memory. In the instruction fetch to this flash memory, 4 bytes can be accessed by a single clock as well as the mask ROM version. Writing to a flash memory can be performed with memory mounted on the target system (on board).
Page 360: Programming Environment
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3017 AND 70F3017Y ONLY) 16.3 Programming Environment The following shows the environment required for writing programs to the flash memory of the V850/SA1. RS-232-C RESET UART0/CSI0 V850/SA1 Dedicated flash writer Host machine A host machine is required for controlling the dedicated flash writer.
Page 361 CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3017 AND 70F3017Y ONLY) (2) CSI0 Transfer rate: up to 1 MHz (MSB first) RESET V850/SA1 Dedicated flash writer SCK0 Clock The dedicated flash writer outputs the transfer clock, and the V850/SA1 operates as a slave. When Flashpro II is used as the dedicated flash writer, it generates the following signals to the V850/SA1.
Page 362: Pin Connection
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3017 AND 70F3017Y ONLY) 16.5 Pin Connection When performing on-board writing, install a connector on the target system to connect to the dedicated flash writer. Also, install the function on-board to switch from the normal operation mode to the flash memory programming mode.
Page 363 CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3017 AND 70F3017Y ONLY) (1) Conflict of signals When connecting a dedicated flash writer (output) to a serial interface pin (input) which is connected to another device (output), conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status.
Page 364: Reset Pin
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3017 AND 70F3017Y ONLY) 16.5.3 RESET pin When connecting the reset signals of the dedicated flash writer to the RESET pin which is connected to the reset signal generation circuit on-board, conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generation circuit.
Page 365: Programming Method
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3017 AND 70F3017Y ONLY) 16.6 Programming Method 16.6.1 Flash memory control The following shows the procedure for manipulating the flash memory. Starts Supplies RESET pulse Switches to flash memory programming mode Selects communication system Manipulates flash memory Ends?
Page 366: Selection Of Communication Mode
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3017 AND 70F3017Y ONLY) Operation Mode Normal operation mode 7.8 V Flash memory programming mode Flash memory programming mode … … … … 7.8 V RESET 16.6.3 Selection of communication mode In the V850/SA1, a communication system is selected by inputting pulse (16 pulses max.) to V pin after switching to the flash memory programming mode.
Page 367: Resources Used
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3017 AND 70F3017Y ONLY) The following shows the command for flash memory control of the V850/SA1. All of these commands are issued from the dedicated flash writer, and the V850/SA1 performs the various processings corresponding to the commands. Category Command Name Function...
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Page 369: Appendix Aregister Index
APPENDIX A REGISTER INDEX (1/5) Symbol Name Unit Page ADCR A/D conversion result register ADCRH A/D conversion result register H ADIC Interrupt control register INTC A/D converter mode register Analogue converter channel specification register ASIM0 Asynchronous serial interface mode register 0 UART ASIM1 Asynchronous serial interface mode register 1...
Page 370 APPENDIX A REGISTER INDEX (2/5) Symbol Name Unit Page DBC0 DMA byte counter register 0 DMAC DBC1 DMA byte counter register 1 DMAC DBC2 DMA byte counter register 2 DMAC DCHC0 DMA channel control register 0 DMAC DCHC1 DMA channel control register 1 DMAC DCHC2 DMA channel control register 2...
Page 371 APPENDIX A REGISTER INDEX (3/5) Symbol Name Unit Page Port 6 Port Port 7 Port Port 8 Port Port 9 Port Port 10 Port Port 11 Port Port 12 Port Processor clock control register Port 1 function register Port Port 2 function register Port PF10 Port 10 function register...
Page 372 APPENDIX A REGISTER INDEX (4/5) Symbol Name Unit Page Pull-up resister option register 2 Port Pull-up resister option register 3 Port PU10 Pull-up resister option register 10 Port PU11 Pull-up resister option register 11 Port RTBH Real time output buffer register H RTBL Real time output buffer register L RTPC...
Page 373 APPENDIX A REGISTER INDEX (5/5) Symbol Name Unit Page TMC1 16-bit timer mode control register 1 TMC2 8-bit timer mode control register 2 TMC3 8-bit timer mode control register 3 TMC4 8-bit timer mode control register 4 TMC5 8-bit timer mode control register 5 TMIC00 Interrupt control register INTC...
Page 374 [MEMO]...
Page 375: Appendix Blist Of Instrution Set
APPENDIX B LIST OF INSTRUTION SET Legend (1) used for operand description Symbol Description reg1 General register (r0 to r31) : Used as source register reg2 General register (r0 to r31) : Mainly used as destination register ×-bit immediate Imm× ×-bit displacement disp×...
Page 376 APPENDIX B LIST OF INSTRUCTION (3) Symbol used for operation (2/2) Symbol Description result Reflects result to a flag. Byte Byte (8 bits) Halfword Half-word (16 bits) Word Word (32 bits) − Subtract Bit concatenation × Multiply ÷ Divide Logical product Logical sum Exclusive logical sum Logical negate...
Page 377 APPENDIX B LIST OF INSTRUCTION SET Condition Code Condition Name Condition Code Conditional Expression Description (cond) (cccc) 0000 OV = 1 Overflow 1000 OV = 0 No overflow 0001 CY = 1 Carry Lower (Less than) NC/NL 1001 CY = 0 No carry No lower (Greater than or equal) 0010...
Page 378 APPENDIX B LIST OF INSTRUCTION Instruction Set (alphabetical order) (1/4) Execution Flag Mnemonic Operand Op Code Operation Clock CY OV GR [reg2] ← GR [reg2] + GR [reg1] × × × × reg1, reg2 rrrrr001110RRRRR GR [reg2] ← GR [reg2] + sign-extend ×...
Page 379 APPENDIX B LIST OF INSTRUCTION SET Instruction Set (alphabetical order) (2/4) Execution Flag Mnemonic Operand Op Code Operation Clock CY OV adr ← GR [reg1] + sign-extend (disp16) LD.W disp16 rrrrr111001RRRRR GR [reg2] ← Load-memory (adr, Wortd)) [reg1], reg2 ddddddddddddddd1 Note 1 LDSR reg2, regID...
Page 380 APPENDIX B LIST OF INSTRUCTION Instruction Set (alphabetical order) (3/4) Execution Flag Mnemonic Operand Op Code Operation Clock CY OV GR [reg2] ← GR [reg2] arithmetically shift × × × reg1, reg2 rrrrr111111RRRRR 0000000010100000 right by GR [reg1] GR [reg2] ← GR [reg2] arithmetically shift ×...
Page 381 APPENDIX B LIST OF INSTRUCTION SET Instruction Set (alphabetical order) (4/4) Execution Flag Mnemonic Operand Op Code Operation Clock CY OV adr ← ep + zero-extend (disp7) SST.B reg2, rrrrr0111ddddddd disp7 [ep] Store-memory (adr, GR [reg2], Byte) adr ← ep + zero-extend (disp8) SST.H reg2, rrrrr1001ddddddd...
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Page 383: Appendix Cindex
APPENDIX C INDEX [Figure] Capture/compare register n1 ----------------------------149 16-bit Timer -------------------------------------------------- 145 Cascade connection (16-bit timer) mode -------------192 16-bit timer mode control register 0, 1 ---------------- 150 CLOCK GENERATION FUNCTION------------------131 16-bit timer output control register 0, 1 --------------- 154 Clock generator (CG) --------------------------------------- 27 16-bit timer register 0, 1 ---------------------------------- 147 Clock Output Function -------------------------------------132 3-wire Serial I/O--------------------------------------------- 209...
Page 384 APPENDIX C INDEX External memory area ---------------------------------------67 Maskable Interrupts---------------------------------------- 110 External wait function ----------------------------------------88 Memory address output mode register ----------------- 71 Memory Block Function------------------------------------- 86 Memory Boundary Operation Condition ---------------- 99 Falling edge enable register ----------------------------- 332 Memory expansion mode register ----------------------- 69 FLASH MEMORY------------------------------------------ 359 Memory map--------------------------------------------------- 62 Flash memory control-------------------------------------- 365...
Page 385 APPENDIX C INDEX Port 1 mode register --------------------------------------- 334 Port 10 -------------------------------------------------------- 348 RAM ------------------------------------------------------------- 27 Port 10 function register ---------------------------------- 350 REAL-TIME OUTPUT FUNCTION--------------------327 Port 10 mode register ------------------------------------- 349 Real-time output buffer registers------------------------322 Port 11 -------------------------------------------------------- 350 Real-time output port control register------------------325 Port 11 mode register ------------------------------------- 352 Real-time output port mode register -------------------324 Port 12 -------------------------------------------------------- 353...
Page 386 APPENDIX C INDEX TM0------------------------------------------------------------- 145 TM1------------------------------------------------------------- 145 Wait signal --------------------------------------------------- 238 TM2-TM5----------------------------------------------- 178, 180 Wake-up control circuit ----------------------------------- 220 TMC0 ---------------------------------------------------------- 150 Wake up function------------------------------------------- 265 TMC1 ---------------------------------------------------------- 150 WATCH TIMER -------------------------------------------- 195 TOC0----------------------------------------------------------- 154 Watch timer --------------------------------------------196, 198 TOC1----------------------------------------------------------- 154 Watch timer mode control register --------------------- 197 Transfer Completion Interrupt Request --------------- 317 WATCHDOG TIMER ------------------------------------- 201...
Page 387 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

This manual is also suitable for:

V850/sa1 mpd70f3017y V850/sa1 mpd703015y V850/sa1 mpd70f3017

NEC V850/SA1 mPD703015 Preliminary User's Manual

Chapter 1 Introduction

General

Features

Application Fields

Ordering Information

Pin Configuration (Top View)

Function Blocks

Chapter 2 Pin Functions

List of Pin Functions

Pin States

Description of Pin Functions

Pins' I/O Circuit Types and Handling When Not Used

Pins' I/O Circuits

Chapter 3 Cpu Functions

Features

CPU Register Set

Operation Modes

Address Space

Chapter 4 Bus Control Function

Features

Bus Control Pins and Control Register

Bus Access

Memory Block Function

Wait Function

Idle State Insertion Function

Bus Hold Function

Bus Timing

Bus Priority

Memory Boundary Operation Condition

Chapter 5 Interrupt/Exception Processing Function

Features

Non-Maskable Interrupt

Maskable Interrupts

Software Exception

Exception Trap

Priority Control

Periods Where Interrupt Is Not Acknowledged

Interrupt Latency Time

Chapter 6 Clock Generation Function

General

Composition

Clock Output Function

Power Saving Functions

Oscillation Stabilization Time

Chapter 7 Timer/Counter Function

16-Bit Timer (TM0, TM1)

Operation

8-Bit Timer (TM2-TM5)

Operation

Chapter 8 Watch Timer

Function

Configuration

Watch Timer Control Register

Operation

Chapter 9 Watchdog Timer

Functions

Configuration

Watchdog Timer Control Register

Operation

Standby Function Control Register

Chapter 10 Serial Interface Function

Overview

3-Wire Serial I/O (CSI0-CSI2)

I C Bus ( Μ Μ Μ Μ PD703015Y, 70F3017Y)

Asynchronous Serial Interface (UART0, UART1)

Chapter 11 A/D Converter

Function

Configuration

Control Registers

Operation

Notes on Using A/D Converter

Chapter 12 Dma Functions

Functions

Transfer Completion Interrupt Request

Control Registers

Chapter 13 Real-Time Output Function (Rto)

Function

Configuration

RTO Control Registers