Page 1 User’s Manual µ µ µ µ PD98410 (NEASCOT-X10™) 1.2G ATM SWITCH LSI Document No. S12523EJ2V0UMJ1 (2nd edition) Date Published October 2000 N CP(K) © 1998 Printed in Japan...
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Page 3 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 4 The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 PREFACE Readers This manual is intended for user engineers who wish to understand the functions of the µ PD98410 and design application systems using it. This manual explains the hardware functions of the µ PD98410 in the following Purpose organization. Organization This manual consists of the following chapters.
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Page 7: Table Of Contents
CONTENTS CHAPTER 1 GENERAL ........................Features ..............................Ordering Information ........................... Example of System Configuration (Application)................Block Diagram ............................Pin Configuration ..........................CHAPTER 2 PIN FUNCTIONS......................Pin Configuration (Bottom View) ......................Pin Layout............................. Pin Functions ............................2.3.1 Power supply..........................2.3.2 UTOPIA interface ........................Memory Interface Signals........................
Page 8 ABR Congestion Control ........................3.5.1 EFCI (Explicit Forward Congestion Indicator) ................3.5.2 RM cell CI/NI marking (Resource Management Cell CI/NI Congestion Indication Marking) ..3.5.3 RM cell merge (Resource Management Cell Merge) ..............WFQ (Weighted Fairness Queue)......................3.6.1 General............................3.6.2 Counters and flags used ......................Peak Rate Shaping Function .......................
Page 9 4.3.8 Header translation error discard indication register (0018h) ............142 4.3.9 HEC/CRC error discard indication register (001Ah)..............144 4.3.10 Input port overrun error discard indication register (001Ch) ............. 145 4.3.11 Threshold value exceeding discard cell count enable register (0020h) ........146 4.3.12 Header translation error discard cell count enable register (0024h) .........
Page 10 TAP Controller Operation ........................181 Initializing TAP Controller........................184 Instruction Register..........................184 5.7.1 BYPASS instruction........................185 5.7.2 EXTEST instruction ........................185 Boundary Scan Data Bit Definition ..................... 185 CHAPTER 6 LIMITATIONS........................187 Limitations ............................187 Description of Limitations ........................188 CHAPTER 7 FAQ (Frequently Asked Questions) ................
Page 11 LIST OF FIGURES (1/2) Figure No. Title Page Example of Connecting UTOPIA Receive Interface ................Example of Connecting UTOPIA Transmit Interface ................Functional Blocks of µ PD98410 ......................Clock Relation ............................Single PHY Mode and Multi-PHY Mode ....................Relationship between Polling Control and Basic Operation Cycle (in multi-PHY mode) ......Polling Operation during Cell Output ......................
Page 12 LIST OF FIGURES (2/2) Figure No. Title Page 3-45 Polling Timing (b) ........................... 3-46 Polling Timing (c) ........................... 3-47 I/O Register Mapping ..........................3-48 HTT & Control Memory and Cell Buffer Memory Mapping..............3-49 Access Timing of 32-Bit Multiplexed Synchronous Bus................. 3-50 Access Timing of 16-Bit Separated Asynchronous Bus.................
Page 13 LIST OF TABLES Table. No. Title Page Receive Interface Signals ........................Transmit Interface Signal........................HTT & Control Memory Interface Signals ....................Cell Buffer Memory Interface Signals ..................... Microprocessor Interface ........................32-Bit Multiplexed Synchronous Interface ....................16-Bit Separated Asynchronous Interface ....................JTAG Interface Signals...........................
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Page 15: Chapter 1 General
CHAPTER 1 GENERAL The µ PD98410 (NEASCOT-X10) is an LSI integrating ATM switch functions on a single chip. It has four UTOPIA Level2 interfaces and can switch 24 × 24 circuits by connecting multiple PHY devices. This LSI employs a shared buffer non-blocking type switch and realizes a switch capacity of 1.2G bps by using an externally connected SRAM for buffering cells.
Page 16: Example Of System Configuration (Application)
CHAPTER 1 GENERAL 1.3 Example of System Configuration (Application) The µ PD98410 can be used to realize an ATM layer cell switching function by connecting it to a microprocessor, SRAM for use as a cell buffer, and a header translation table (HTT)/SRAM for storing control information as shown below.
Page 17: Block Diagram
CHAPTER 1 GENERAL 1.4 Block Diagram Cell Buffer Memory Cell buffer interface UTOPIA UTOPIA receive transmit port 0 port 0 UTOPIA UTOPIA receive transmit port 1 port 1 Output Input Queue header header controller selector selector UTOPIA UTOPIA receive transmit port 2 port 2 Output...
Page 18: Pin Configuration
CHAPTER 1 GENERAL 1.5 Pin Configuration HTT & Control Memory Microprocessor Interface Interface Control RDY_B/RDY JTAG HCLK JRST_B HSEL RXDATA3 [7:0] TXDATA2 [7:0] UCLK3 TXENB2_B RXENB3_B TXSOC2 RXSOC3 TXCLAV2 RXCLAV3 TXADDR2 [3:0] RXADDR3 [3:0] UTOPIA UTOPIA Interface 3 RXADDR2 [3:0] Interface 2 TXADDR3 [3:0] RXCLAV2...
Page 19: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Configuration (Bottom View) 580-pin BGA package Note Index mark Note The index mark is shown in Top View.
Page 20 CHAPTER 2 PIN FUNCTIONS Pin name (1) Power (4) CPU Interface : Supply Voltage HSEL : Host Bus Mode Select : Ground IOCS_B : I/O Chip Select MCS_B : Memory Chip Select (2) UTOPIA RDY_B, RDY : I/O Ready, Memory Ready RXADDR*3 - RXADDR*0 : Receive Address : Interrupt Request RXDATA*7 - RXDATA*0 : Receive Data Bus...
Page 21: Pin Layout
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Layout (1/6) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name CBD72 RXDATA05 CBD69 CBD66 CBD63 RXCLAV0 CBD58 TXADDR01 JRST_B CBD56 TXENB0_B RXDATA36 CBD51 TXDATA04 RXDATA32 CBD49 TXDATA00 CBD46 RXDATA26 RXSOC3 CBWE_B RXADDR31 CBA17...
Page 22 CHAPTER 2 PIN FUNCTIONS (2/6) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name AD1/D1 TXDATA36 CBA2 HTA14 TXDATA33 CBD42 TXDATA34 CBD38 HTA9 RXDATA15 CBD33 RXDATA12 CBD28 HTCS1_B CBD26 RXCLAV1 CBD23 HTCS0_B RXADDR11 TXADDR12 HTD29 TXCLAV1 CBD13 HTD26 TXDATA17 CBD12...
Page 23 CHAPTER 2 PIN FUNCTIONS (3/6) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name HCLK MCS_B CBD54 R/W_B/ CBD52 WR_B CBD48 AD31/A15 CBD47 AD28/A12 CBD45 AD27/A11 RXDATA37 CBCS0_B RXDATA33 CBA16 AD25/A9 RXDATA31 CBA12 AD22/A6 RXENB3_B CBA10 AD20/A4 RXADDR32 CBA5 AD16/A0...
Page 24 CHAPTER 2 PIN FUNCTIONS (4/6) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name RXDATA20 HTD9 CBD60 UCLK2 HTD6 CBD55 RXSOC2 RXADDR22 CBD50 TXADDR22 CBD44 TXSOC2 TXDATA26 CBA14 CBA8 HSEL RXDATA35 CBA3 AD30/A14 UCLK3 CBD43 AD29/A13 RXCLAV3 CBD40 AD26/A10 CBD36...
Page 25 CHAPTER 2 PIN FUNCTIONS (5/6) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name RXADDR20 TXDATA27 TXDATA24 TXDATA21 UWE_B/RD_B AD24/A8 AD21/A5 AD17/A1 AD15/D15 AD11/D11 AD5/D5 AD0/D0 HTA16 HTA13 HTA7 HTA0 HTD30 HTD25 HTD22 HTD19 HTP1 HTD12 HTP0 HTD3 HTD1...
Page 26 CHAPTER 2 PIN FUNCTIONS (6/6) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name...
Page 27: Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.3 Pin Functions Although the µ PD98410 is a device operating at 3.3 V, it can be directly connected to a PHY device, CPU, and memory with a 5-V TTL interface. 2.3.1 Power supply Pin Name Pin No.
Page 28: Utopia Interface
CHAPTER 2 PIN FUNCTIONS 2.3.2 UTOPIA interface The µ PD98410 employs a UTOPIA Level2 (cell level transfer) interface between PHY layer and ATM layer. Tables 2-1 and 2-2 lists the interface signals. Table 2-1. Receive Interface Signals (1/2) Symbol Pin No. Function RXADDR03 - 434, 204, 323, 435...
Page 29 CHAPTER 2 PIN FUNCTIONS Table 2-1. Receive Interface Signals (2/2) Symbol Pin No. Function RXADDR23 - 214, 333, 88, 445 Multi-PHY select address of receive interface 2. RXADDR20 RXADDR23 is the MSB. RXDATA27 - 210, 82, 84, 329, 211, 441, Cell data input of receive interface 2.
Page 30 CHAPTER 2 PIN FUNCTIONS Table 2-2. Transmit Interface Signal (1/2) Symbol Pin No. Function TXADDR03 - 205, 324, 78, 325 Multi-PHY select address of transmit interface 0. TXADDR00 TXADDR03 is the MSB. TXDATA07 - 437, 207, 327, 80, 328, 208, Cell data output of transmit interface 0.
Page 31 CHAPTER 2 PIN FUNCTIONS Table 2-2. Transmit Interface Signal (2/2) Symbol Pin No. Function TXADDR23 - 215, 335, 89, 216 Multi-PHY select address of transmit interface 2. TXADDR20 TXADDR23 is the MSB. TXDATA27 - 447, 337, 218, 448, 92, 219, Cell data output of transmit interface 2.
Page 32: Memory Interface Signals
CHAPTER 2 PIN FUNCTIONS 2.4 Memory Interface Signals The µ PD98410 has two types of memory interfaces. One of them is used to store a cell header translation table and an address pointer to the cell buffer to the HTT & control memory, and the other is used to store cell data to the cell buffer memory.
Page 33 CHAPTER 2 PIN FUNCTIONS Table 2-4. Cell Buffer Memory Interface Signals Symbol Pin No. Function CBA17 - 48, 300, 178, 413, 50, 301, 180, 302, Address output CBA0 52, 415, 53, 182, 303, 54, 417, 183, 305, 55 CBD87 - CBD0 397, 29, 283, 30, 398, 161, 399, 31, Data bus (88-bit/word units) 285, 162, 163, 165, 400, 36, 166, 37,...
Page 34: Microprocessor Interface Signals
CHAPTER 2 PIN FUNCTIONS 2.4.1 Microprocessor interface signals The µ PD98410 supports the following two types of microprocessor interfaces: (1) 32-bit address/data multiplexed synchronous bus (2) 16-bit address/data separated asynchronous bus The functions of some pins differ depending on the mode used. Table 2-5.
Page 35 CHAPTER 2 PIN FUNCTIONS Table 2-7. 16-Bit Separated Asynchronous Interface Symbol Pin No. Function HCLK Connect this pin to GND or pull it up to V Connect this pin to GND or pull it up to V A14 - A0 342, 343, 224, 225, 344, 227, 454, 345, Address input 228, 455, 229, 346, 104, 456, 230...
Page 36: Jtag
CHAPTER 2 PIN FUNCTIONS 2.4.2 JTAG Table 2-8. JTAG Interface Signals Symbol Pin No. Function JTAG serial data input JTAG serial data output (normally open) (3-state buffer) JTAG serial clock input JTAG mode select signal JRST_B JTAG reset signal 2.4.3 Others Table 2-9.
Page 37: Recommended Connections Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.5 Recommended Connections of Unused Pins Table 2-10. Recommended Connections of Unused Pins Pin Name Recommended Connections RXDATA07 - RXDATA00 Connect to GND. RXDATA17 - RXDATA10 RXDATA27 - RXDATA20 RXDATA37 - RXDATA30 RXSOC3 - RXSOC0 Connect to GND. RXCLAV3 - RXCLAV0 Connect to GND.
Page 38: Pin Status At Reset
CHAPTER 2 PIN FUNCTIONS 2.6 Pin Status at Reset Table 2-11. Pin Status at Reset Pin Name Pin Status at Reset RXADDR03 - RXADDR00 High level RXADDR13 - RXADDR10 RXADDR23 - RXADDR20 RXADDR33 - RXADDR30 RXENB3_B - RXENB0_B High level TXADDR03 - TXADDR00 High level TXADDR13 - TXADDR10...
Page 39: Chapter 3 Functional Outline
CHAPTER 3 FUNCTIONAL OUTLINE The µ PD98410 is a shared-buffer non-blocking ATM switch which has a header translation function. Its circuit interfaces conform to UTOPIA Level2 and can connect up to 24 circuits of different rates by connecting multiple PHY devices.
Page 40: Input Port Interface
CHAPTER 3 FUNCTIONAL OUTLINE 3.1.1 Input port interface The µ PD98410 has four UTOPIA interfaces and supports multiple PHY device connection allowing up to 24 input ports. Up to 12 ports can be connected to each UTOPIA interface. An input port is mapped to a logical input port number based on the PHY address and UTOPIA interface number, in accordance with the contents of the port configuration register.
Page 41: Output Port Interface
CHAPTER 3 FUNCTIONAL OUTLINE 3.1.2 Output port interface The µ PD98410 has four UTOPIA interfaces and supports multiple PHY device connection allowing up to 24 output ports. Up to 12 output ports can be connected to each UTOPIA interface. An output port is mapped to a logical output port number based on the PHY address and UTOPIA interface number, in accordance with the contents of the port configuration register.
Page 42: Polling
CHAPTER 3 FUNCTIONAL OUTLINE 3.2 Polling Cells are input to the µ PD98410 in the following sequence: The µ PD98410 inquires whether a PHY device has a cell (polling). <1> If the device has a cell, the µ PD98410 inputs the cell. If not, the µ PD98410 makes an inquiry to the next <2>...
Page 43 CHAPTER 3 FUNCTIONAL OUTLINE Basically, cells are input or output as follows: (Input) • The polling control block inquires whether each PHY device is ready to transmit a cell, and determines the logical input port that inputs the cell. • The cell is input to the I-FIFO. (Output) •...
Page 44: Polling During Cell Output
CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-4. Clock Relation Input side Output side I-FIFO O-FIFO I-Poling O-Poling Control Control I-FIFO O-FIFO switch circuit I-FIFO O-FIFO I-FIFO O-FIFO Caution The following relationship between the UTOPIA clock frequency and system clock frequency must be satisfied. System clock frequency ≥...
Page 45 CHAPTER 3 FUNCTIONAL OUTLINE Each mode is explained below. <1> Multi-PHY mode In this mode, two or more PHY devices can be connected to one UTOPIA output port. It is also possible to connect only one PHY device in this mode. Even if only one PHY device is connected, the operation in this mode is different from that in the single PHY mode.
Page 46 CHAPTER 3 FUNCTIONAL OUTLINE <Basic operation> • Polling is performed starting from the second clock in the basic operation cycle. • Inquires are made sequentially, starting from PHY address 0 (2nd, 4th, 6th, ... clock), and the result of the inquiry is returned at the next clock (3rd, 5th, 7th ...
Page 47 CHAPTER 3 FUNCTIONAL OUTLINE The µ PD98410 outputs a cell to the PHY device that is selected at the 54th clock in the basic operation cycle (polling and cell output are performed in parallel). At this time, polling is started from the next PHY address after the PHY device that is currently transferring a cell.
Page 48 CHAPTER 3 FUNCTIONAL OUTLINE (2) Polling in single PHY mode The relationship between polling control and the basic operation cycle is illustrated below. Figure 3-9. Relationship between Polling Control and Basic Operation Cycle (single PHY mode) Basic operation 24 25 26 27 50 51 52 53 54 cycle PHY address...
Page 49 • RP = 1 → Permits successive output of cells to the same PHY device. To output cells successively, the validity of the result detected at the 27th clock must be guaranteed. NEC’s 155M-bps PHY µ PD98404 (P30) satisfies this requirement and cells can be successively output to this device. To...
Page 50: Polling During Cell Input
CHAPTER 3 FUNCTIONAL OUTLINE 3.2.3 Polling during cell input (1) Basic operation Figure 3-11. Basic Operation of Polling during Cell Input Input side Inquiry to determine whether device has cells I-Poling Contorl Response to indicate whether device has cells Cells are input to the µ PD98410 in the following sequence: The µ...
Page 51 CHAPTER 3 FUNCTIONAL OUTLINE (2) Cell input timing If the result of polling is okay (i.e., if the device has cells), the cells are input as follows: Figure 3-13. Basic Cell Input Timing 1 While a cell is being input, While a cell is being input, inquiry is resumed starting inquiry is resumed starting...
Page 52 CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-14. Basic Cell Input Timing 2 Inquiry is resumed from the next PHY address of the device after the one that is inputting a cell. Clock PHY address to be polled (RXADDR) Result (RXCLAV) Inquiry is not made to the PHY Sets address of device that is inputting a cell.
Page 53 CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-16. Control of Successive Input Inquiry is resumed from the next PHY device. Clock PHY address to be polled (RXADDR) Result (RXCLAV) The PHY device that is to input a cell next is not determined during this period.
Page 54 CHAPTER 3 FUNCTIONAL OUTLINE (b) If cell is not input during wait time (i) If the result of polling PHY address n + 1 is OK No inquiry is made. Wait time Clock PHY address to be polled (RXADDR) Result (RXCLAV) Inquiry is resumed.
Page 55 CHAPTER 3 FUNCTIONAL OUTLINE (iii) If result of polling PHY addresses n + 1 and n + 2 is not OK Wait time Clock PHY address to be polled (RXADDR) Result (RXCLAV) The PHY device that is to input a cell is is not determined during this period.
Page 56: Header Translation
CHAPTER 3 FUNCTIONAL OUTLINE 3.3 Header Translation The µ PD98410 translates headers in accordance with the header translation table (HTT) created in the external SRAM. Headers are translated when a cell is input in the single-cast mode, and when a cell is input or output in the multi-cast mode.
Page 57: General
CHAPTER 3 FUNCTIONAL OUTLINE 3.3.2 General This section outlines the processing of cell switching and header translation. First, an example where a cell input from logical input port #1 is output from logical output port #10 is given. Figure 3-18. Example of Single Cast VPI = 2 PHY1 VCI = 40...
Page 58 CHAPTER 3 FUNCTIONAL OUTLINE Information at the output side is stored in the HTT. Information at the input side is used to calculate the addresses of the HTT area in which the information at the output side is stored. Therefore, the information at the output side is obtained based on the information at the input side.
Page 59 CHAPTER 3 FUNCTIONAL OUTLINE Area-B is also used in the multi-cast mode. At this time, a pointer that is used to access Area-B is stored in Area- A, and information at the output side is stored in Area-B. Figures 3-21 and 3-22 show this. Figure 3-21.
Page 60: Format Of Htt
CHAPTER 3 FUNCTIONAL OUTLINE 3.3.3 Format of HTT This section explains the format in which information is stored in Area-A and Area-B. (a) Area-A format The µ PD98410 accesses Area-A by using a logical input port number, VPI, and VCI as pointers when cells are input.
Page 61 CHAPTER 3 FUNCTIONAL OUTLINE Symbol Name Size Description Early Packet 1 bit Makes EPD valid or invalid. When CEN is active, the read value of this bit is not guaranteed because the µ PD98410 rewrites the value. Discard Enable 0: EPD invalid 1: EPD valid Switching Mode 1 bit...
Page 62 CHAPTER 3 FUNCTIONAL OUTLINE (b) Area-B format The µ PD98410 accesses Area-B by using MBP as a pointer when a multi-cast cell is input. The following information is stored in Area-B in 64-byte units. Figure 3-24. HTT Area-B Format Offset address 31 16 15 OVPC for LN22...
Page 63: Accessing Htt
CHAPTER 3 FUNCTIONAL OUTLINE 3.3.4 Accessing HTT Accessing the HTT was mentioned in 3.3.2 General. This section explains that in detail. (1) VP connection and VC connection The µ PD98410 performs two types of switching: VP connection and VC connection. The differences between these two modes of switching are illustrated below.
Page 64 CHAPTER 3 FUNCTIONAL OUTLINE (2) Access to HTT Section 3.3.2 General discussed how to calculate the address to access the HTT by using a logical input port number, VPI , and VCI. In practice, however, the address is calculated in the following procedure, because of the differences between VP connection and VC connection.
Page 65 CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-26. Difference in Access to HTT between VPC and VCC (single cast) HTT & Control memory Control memory Port No., VPI, and VCI at Access with Port No, VPI (value in output side are known. input cell), and VCI (= 20h) Area-B Area-A...
Page 66 CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-27. Calculating HTT Address 16-bit NVPC BASE NVCI c15 c14 c13 c12 c11 c10 c7 c6 c5 c4 c3 c2 c1 c0 HTT Address c7 c6 c5 c4 c3 c2 c1 c0 The valid range of BASE and HTT addresses is dependent upon the size of the HTT & control memory (the value of HMS bit of the mode register).
Page 67 CHAPTER 3 FUNCTIONAL OUTLINE (4) VPI and VCI of output cell The procedure to obtain information on a port number at the output side, and VPI and VCI to be appended to an output cell has been discussed so far. Using this procedure, the information on a logical output port number can be obtained from the following: •...
Page 68: Flow Of Header Translation
CHAPTER 3 FUNCTIONAL OUTLINE 3.3.5 Flow of header translation This section explains the flow of header translation depending on the differences in the switching mode and cast mode. (1) VCC, single cast Figure 3-29. Flow of Header Translation in VCC and Single Cast Modes Area-A Area-B <1>...
Page 69 CHAPTER 3 FUNCTIONAL OUTLINE (2) VCC, multi-cast Figure 3-30. Flow of Header Translation in VCC and Multi-Cast Modes Area-A Area-B <1> <3> <6> <2> <4> <7> Input-VPI, VCI SM (= 0) CM (= 1), OVPC Output Cell Separation Input Cell Combination Combination <8>...
Page 70 CHAPTER 3 FUNCTIONAL OUTLINE (3) VPC, single cast Figure 3-31. Flow of Header Translation in VPC and Single Cast Modes Area-A Area-B <1> <2> Input-VPI, VCI SM (= 1), CM (= 0) , OVPC Output Cell Input Cell Separation Combination Combination <4>...
Page 71 CHAPTER 3 FUNCTIONAL OUTLINE (4) VPC, multi-cast Figure 3-32. Flow of Header Translation in VPC and Multi-Cast Modes Area-A Area-B <1> <4> <2> <5> Input-VPI, VCI SM (= 1), CM (= 1) , OVPC Output Cell Input Cell Separation Combination Combination <6>...
Page 72: Accessing Htt With Rm Cell
CHAPTER 3 FUNCTIONAL OUTLINE 3.3.6 Accessing HTT with RM cell (1) Connection in ABR class In ABR (Available Bit Rate) class, connection of the Backward RM cell that reports congestion information in the transmission terminal direction must be set. Transmission terminal Reception terminal #n: Logical port number Assuming that a cell is transmitted in the combination (A) in the table below, connection in the backward direction...
Page 73 CHAPTER 3 FUNCTIONAL OUTLINE (2) Multi-cast and RM cell merge function Next, the case of multi-cast is considered. Transmission terminal Reception terminal VPI = 2 VPI = 3 VCI = 35 VCI = 40 Reception terminal VPI = 4 VCI = 50 #n: Logical port number In this case, multi-cast connection (a) in the table below must be set in the transmission direction of the cell, and two single cast connections such as in (b) must be set in the backward direction.
Page 74 CHAPTER 3 FUNCTIONAL OUTLINE Because (b) and (a) are completely opposite to each other in terms of input/output, the following values assigned to the HTT in (b) are used to obtain the value in the above table. Logical Input Port Number of (a) VPI of (a) VCI of (a) At VPC...
Page 75: Queue Control
CHAPTER 3 FUNCTIONAL OUTLINE 3.4 Queue Control The µ PD98410 organizes the following queues in the control memory for management of the cell buffer. • The idle queue queues an address pointer that indicates the position of the cell buffer to which the cells can be stored.
Page 76: Multi-Cast
CHAPTER 3 FUNCTIONAL OUTLINE 3.4.2 Multi-cast The µ PD98410 realizes multi-casting by storing input cells in one location in the cell buffer and inputting cell addresses to the output queue of each logical output port. The advantage of this method is that it is not necessary to copy 53-byte cells more than once.
Page 77: Congestion Control
CHAPTER 3 FUNCTIONAL OUTLINE 3.4.3 Congestion control ATM defines service classes based on Cell Loss Ratio/Cell Transfer Delay/Cell Delay Variation that indicate the traffic status of cells and transfer quality. The µ PD98410 divides the service classes into the following four classes for management.
Page 78 CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-35. Queues and Counters by Service Class Used Cell Counter (on cell buffer) UCthRVR UCthNVR UCthAEP UCthUER UCthCBR UCthRM UCthABR UCthUBR ALLmin Total Cell Counter for each class (except each OQminXXX) CBR, Real time VBR TCminCRV RM, Non real time VBR TCminRNV...
Page 79 CHAPTER 3 FUNCTIONAL OUTLINE UC: Threshold values related to Used Cell Counter • UCthCBR CBR cell discard threshold value • UCthRVR rtVBR cell discard threshold value • UCthRM RM cell discard threshold value • UCthNVR nrtVBR cell discard threshold value •...
Page 80 CHAPTER 3 FUNCTIONAL OUTLINE IQ: Minimum queue length related to Idle Queue (none) OQ: Minimum queue length related to Output Queue • OQminCRV Minimum queue length allocated to CBR/rtVBR class of output port • OQminRNV Minimum queue length allocated to RM/nrtVBR class of output port •...
Page 81: Cell Discard By Class
CHAPTER 3 FUNCTIONAL OUTLINE 3.4.4 Cell discard by class The µ PD98410 forcibly discards cells that pass a congestion point if it detects congestion according to the cell discard threshold value for each class. It controls discarding cells, giving them priorities, during the following periods: •...
Page 82: Epd (Early Packet Discard) Control
CHAPTER 3 FUNCTIONAL OUTLINE Table 3-4. Cell Discard Threshold Values Related to Multi-Cast Queue Length Threshold Value Name Control if Threshold Value Is Exceeded (processing during cell input) MQthCRV Discards CBR/rtVBR cell of multi-cast queue MQthRNV Discards RM/nrtVBR cell of multi-cast queue MQthABR Discards ABR cell of multi-cast queue MQthUBR...
Page 83 CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-37 shows the status transition when EOP control is enabled. Figure 3-37. Status Transition When EOP Control Is Enabled <1> Pause Reception <2> <3> <4> Discard <Processing flow and status transition> In the initial status, control is paused. If a cell is input in this status, it is checked whether the total number of current cells and output queue length exceed the EPD threshold value.
Page 84: Ppd (Partial Packet Discard) Control
CHAPTER 3 FUNCTIONAL OUTLINE The following tables list the threshold values used for EPD control. • EPD threshold values related to total number of cells Threshold Value Description UCthAEP EPD threshold value for cell of ABR class UCthUEP EPD threshold value for cell of UBR class •...
Page 85: Minimum Queue Length
CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-39. Status Transition of PPD Control <1> Pause Reception <2> <3> <4> Additional status transition by PPD control Discard 3.4.7 Minimum queue length With the shared buffer method, if the class of a specific logical output port is in the congestion status, the threshold values related to the total number of cells (Used Cell Counter) of that class are exceeded.
Page 86 CHAPTER 3 FUNCTIONAL OUTLINE Table 3-7. Minimum Queue Length Related to Output Queue Length Threshold Value Name Processing during Cell Input OQminCRV Guarantees minimum queue for CBR/rtVBR cell of each output port. OQminRNV Guarantees minimum queue for RM/nrtVBR cell of each output port. OQminABR Guarantees minimum queue for ABR cell of each output port.
Page 87 CHAPTER 3 FUNCTIONAL OUTLINE Table 3-9. Classification and Names of Threshold Values OQ (Output Queue)/ TC (Total Cell Counter Classification MQ (Multicast Queue) for each class) (Used Cell Counter) Discard MAX. threshold (*1) — (*6) threshold value value OQthCBR, OQthRVR UCthCBR, UCthRVR OQthRM, OQthNVR UCthRM, UCthNVR...
Page 88: Abr Congestion Control
CHAPTER 3 FUNCTIONAL OUTLINE 3.5 ABR Congestion Control When the µ PD98410 detects congestion status, it can report the congestion in the receiver terminal direction by using the EFCI bit of the user cell, and in the transmitter terminal direction by using the CI, NI, and BN bits of the Backward RM cell.
Page 89: Rm Cell Merge (Resource Management Cell Merge)
CHAPTER 3 FUNCTIONAL OUTLINE The threshold values to be used are the same as those in 3.5.1 EFCI. CI/NI marking control is performed under the following condition: • The Backward RM cell is identified as follows while the output queue of ABR class of the logical port that has input the Backward RM cell exceeds the EFCI threshold value.
Page 90: Wfq (Weighted Fairness Queue)
CHAPTER 3 FUNCTIONAL OUTLINE 3.6 WFQ (Weighted Fairness Queue) 3.6.1 General When a cell is output from an output queue, which cell is to be output is determined by the following two conditions: <Output cell determining conditions> (1) The logical output port to output the cell has been determined. (2) Of the output queues allocated to the determined logical output port, the service class of the queue from which the cell is taken out has been determined.
Page 91 CHAPTER 3 FUNCTIONAL OUTLINE As shown in Figure 3-41, these queues are assigned priorities, and the cells queued are sequentially output to these queues starting from the one with the highest priority. C , and C are the counters that control these priorities.
Page 92 CHAPTER 3 FUNCTIONAL OUTLINE (3) C (3 bits) • The initial value is loaded to these counters when both the counters reach 0, regardless of the cycle counter. • If congested cells exist in the queues of both ABR and UBR classes, and if both the C and C counters are not 0 (i.e., if output is not prohibited), the two classes are alternately granted output permission.
Page 93: Peak Rate Shaping Function
CHAPTER 3 FUNCTIONAL OUTLINE 3.7 Peak Rate Shaping Function The µ PD98410 has a simple peak rate shaping function for each logical output port. This shaping function takes effect on the transfer throughput per UTOPIA interface that is determined by SWCLK, and not on the transfer rate of the UTOPIA interface that is determined by UCLK3 through UCLK0.
Page 94 CHAPTER 3 FUNCTIONAL OUTLINE As shown in Figure 3-42, each UTOPIA interface is allocated once in one cycle. Assuming that a cell is always output when each UTOPIA interface is allocated, one UTOPIA interface has a transfer capability of 318M bps (where SWCLK Rate is 33 MHz).
Page 95: Details
CHAPTER 3 FUNCTIONAL OUTLINE 3.7.2 Details (1) Shaping rate To control whether the UTOPIA interface is allocated to logical output ports in each cycle, the following counter and register are provided. • Ct counter : Counter for shaping rate control •...
Page 96 CHAPTER 3 FUNCTIONAL OUTLINE (2) Shaping error correction If multiple logical output ports LP0 through LPn are connected to one UTOPIA interface, UP0, the timing of allocating the interface to the output ports overlap as shown below (output conflict occurs), dropping the throughput.
Page 97 CHAPTER 3 FUNCTIONAL OUTLINE This drop in throughput due to the output conflict can be prevented by using the shaping error correction function. The operation is as follows: Basic operation cycle (allocation timing) <2> LP0 (set to 1/3) <1> <3> <3>...
Page 98 CHAPTER 3 FUNCTIONAL OUTLINE At this time, the counter changes as shown below. Basic operation cycle (allocation timing) <2> LP0 (set to 1/3) <1> <3> <3> <1> <2> <4> <5> LP1 (set to 1/2) (Actual output without error correction) <2> <1>...
Page 99: Successive Transmission
PHY device to be connected. The following modes are used depending on the PHY device to be connected: (a) NEC’s 155M bps PHY “ µ PD98404 (P30)” → Successive output mode & multi-PHY mode (b) PHY of more than 1/3 of UTOPIA transfer rate → Single PHY mode (c) PHY of less than 1/3 of UTOPIA transfer rate →...
Page 100 P19 (payload 19) is transferred. Because NEC’s 155M bps PHY “ µ PD98404” has a mode in which the correct result is returned in response to this polling, it can successively output cells to the µ PD98410.
Page 101 CHAPTER 3 FUNCTIONAL OUTLINE (b) Single PHY mode (PHY device of more than 1/3 of UTOPIA transfer rate) In this mode, the maximum transfer rate per PHY device is equivalent to the transfer rate of the UTOPIA interface. This mode is used when a PHY device with a transfer rate of more than 1/3 of the UTOPIA interface is connected.
Page 102 UTOPIA interface. The non-successive output mode is valid even when a PHY device in the successive output mode (such as NEC’s PHY device) exists on the same UTOPIA interface. If the non-successive output mode (PT register RP = “0”) and multi-PHY mode are set, the µ PD98410 does not reflect the result of polling made when P19 (payload 19) is transferred to the PHY device that is transferring a cell on the output arbitration.
Page 103: Interrupt Request
CHAPTER 3 FUNCTIONAL OUTLINE 3.9 Interrupt Request This section explains the interrupt requests made by the µ PD98410 to the microprocessor. 3.9.1 Parity error The µ PD98410 checks the HTT & control memory and cell buffer for parity error. If a parity error is detected, the µ...
Page 104: Cast Count Error
CHAPTER 3 FUNCTIONAL OUTLINE 3.9.4 Cast count error The µ PD98410 issues an interrupt request to the microprocessor if it detects malfunctioning of the idle queue management block or the multi-cast count management block. If a cast count error is detected, it is indicated by the CE bit of the status register, and the subsequent header translation and switching operation cannot be guaranteed.
Page 105: Header Translation Error
CHAPTER 3 FUNCTIONAL OUTLINE 3.9.8 Header translation error If the µ PD98410 detects a header translation error as a result of accessing the header translation table (HTT) by an input cell, it discards the corresponding cell, stores the logical input port number in the monitor register (ERHT) register, and issues an interrupt request to the microprocessor.
Page 106: Monitoring
CHAPTER 3 FUNCTIONAL OUTLINE 3.10 Monitoring 3.10.1 Monitor register The µ PD98410 stores the numbers of ports responsible for errors (except for parity errors) in the monitor registers. A value valid when an error occurs is stored in each register. The values of these registers do not change until the microprocessor clears the status bits.
Page 107: Cell Discard Count Due To Hec Error Or Crc Error
CHAPTER 3 FUNCTIONAL OUTLINE 3.10.4 Cell discard count due to HEC error or CRC error The µ PD98410 discards cells when an HEC error or CRC error occurs. It can monitor the number of discarded cells over any period under any logical input port conditions. (a) Monitor condition The following condition can be assigned to a register.
Page 108: Counting Number Of Received Cells
CHAPTER 3 FUNCTIONAL OUTLINE 3.10.6 Counting number of received cells The µ PD98410 can monitor the number of cells received by the UTOPIA interface port over any period. (a) Monitor condition The following condition can be assigned to a register. •...
Page 109: Microprocessor Interface
CHAPTER 3 FUNCTIONAL OUTLINE 3.11 Microprocessor Interface The microprocessor can access the HTT & control memory and cell buffer memory via the µ PD98410, in addition to the internal I/O registers of the µ PD98410. • I/O registers : Initial setting, command issuance, status check, etc. •...
Page 110: I/O Mapping And Memory Mapping
CHAPTER 3 FUNCTIONAL OUTLINE 3.11.1 I/O mapping and memory mapping When IOCS_B is asserted active, the I/O registers are selected. When MCS_B is asserted active, the external memory is selected. Either the HTT & control memory or cell buffer memory is selected as the external memory by the HC bit of the memory mode register.
Page 111 CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-47. I/O Register Mapping D[31:0] 32-bit A[14:0] 7FFFh NEC’s TEST Area (Never access) 0400h 03FFh Per Port Threshold Total Threshold OQ Threshold min Discarded Cell Count Monitor MPU Register 0000h I/O Mapping for Microprocessor...
Page 112 CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-48. HTT & Control Memory and Cell Buffer Memory Mapping D[31:0] CBD[87:0] 32-bit 128-bit/word A[21:0] CBA[17:0] 3FFFFFh 3FFFFh When memory mode register HC = 0 88-bit Not used CBD[87:64] used CBD[63:32] CBD[31:0] When memory mode register HC = 1 HTD[31:0] 1FFFFFh 1FFFFh...
Page 113: 32-Bit Multiplexed Synchronous Bus (Hsel = Low)
CHAPTER 3 FUNCTIONAL OUTLINE 3.11.2 32-bit multiplexed synchronous bus (HSEL = Low) If the HSEL input pin is low at hardware reset, the 32-bit multiplexed synchronous bus is selected as the bus interface. (1) Endian The microprocessor bus is set to little endian as the default condition after reset. To connect a microprocessor with a big endian interface, set the BL bit of the memory read register to “1”.
Page 114 CHAPTER 3 FUNCTIONAL OUTLINE (2) Access timing Figure 3-49. Access Timing of 32-Bit Multiplexed Synchronous Bus HCLK Write data Read data AD[31:0] Address Address in/out During write operation During read operation IOCS_B, MCS_B UWE_B Read operation R/W_B Write operation (Hi-Z) (Hi-Z) RDY_B When IOCS_B or MCS_B is asserted, AD[31:0], UWE_B, and R/W_B are loaded in synchronization with the...
Page 115: 16-Bit Separated Asynchronous Bus (Hsel = High)
CHAPTER 3 FUNCTIONAL OUTLINE 3.11.3 16-bit separated asynchronous bus (HSEL = High) If the HSEL input pin is high at hardware reset, the 16-bit separated asynchronous bus is selected as the bus interface. (1) Endian The microprocessor bus is set to little endian as the default condition after reset. To connect a microprocessor with a big endian interface, set the BL bit of the mode register to “1”...
Page 116 CHAPTER 3 FUNCTIONAL OUTLINE (2) Access timing Figure 3-50. Access Timing of 16-Bit Separated Asynchronous Bus A14-00 Address  During write operation  Valid  D15-00   During read operation in/out   Valid IOCS_B, MCS_B RD_B Read operation WR_B Write operation (Hi-Z)
Page 117 CHAPTER 3 FUNCTIONAL OUTLINE (3) Bank register The 16-bit separated asynchronous bus access an area of the external memory by using the BANK register. Figure 3-51. Memory Map of 16-Bit Separated Asynchronous Bus BANK[6:0] 16-bit EA[21:0] 3FFFFFh Cell buffer memory (when memory mode register HC = 0) Little endian Big endian 3F8000h...
Page 118: External Memory Interface
CHAPTER 3 FUNCTIONAL OUTLINE 3.12 External Memory Interface 3.12.1 HTT & control memory interface A memory with 1 word being 36 bits wide (32 bits + 4-bit parity) and a depth of 64K words is connected as the HTT & control memory. This memory can be expanded along with the cell buffer, and 128K word and 256K word memories can be connected.
Page 119: Cell Buffer Interface
CHAPTER 3 FUNCTIONAL OUTLINE If the HTT & control memory is configured to its maximum size, two memories of 256K words × 18 bits, or three or four 256K word × 16 bit memories are used. If 256K word × 16 bit memories that can control byte data (e.g., µ...
Page 120 CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-54. Cell Buffer Storage Format 88 87 Parity ILPN VC switching SM = 0 : Cast counter (5 bits) Rsv. OVPC Single cast CM = 0 : Cast counter parity (1 bit) : Switching mode (1 bit) VC switching SM = 0 : Casting mode (1 bit)
Page 121 CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-55. Example of Connecting Cell Buffer Memory µ PD98410 Minimum configuration 1M-bit 1M-bit 1M-bit 1M-bit 1M-bit µ PD98410 Maximum configuration 4M-bit 4M-bit 4M-bit 4M-bit 4M-bit 4M-bit...
Page 122 [MEMO]...
Page 123: Chapter 4 Internal Registers
CHAPTER 4 INTERNAL REGISTERS 4.1 Register List (1/2) Section Address Register Name Function 0000h Command 4.2.1 0004h BANK Memory bank 4.2.2 0006h MODE Memory mode 4.2.3 0008h INTMASK Interrupt mask 4.2.4 000Ch STATUS Status 4.2.5 0010h EXTHMS Threshold value exceeding discard indication mask 4.2.6 0014h EXTH...
Page 124 CHAPTER 4 INTERNAL REGISTERS (2/2) Section Address Register Name Function 0080h OQthCBR CBR class output queue maximum threshold value 4.2.25 0082h OQthRVR rtVBR class output queue maximum threshold value 4.2.25 0086h OQthCCL CLP threshold value of CBR + rtVBR class output queue 4.2.28 0090h OQthRM...
Page 125: Register Map
CHAPTER 4 INTERNAL REGISTERS 4.2 Register Map ALLmin TCminUBR TCminABR TCminRNV TCminCRV MQminUBR MQminABR MQminRNV MQminCRV OQminUBR OQminABR OQminRNV OQminCRV CTMEMEMP CTERHEC CTERHT CTEXTH CTRCV CTENRCV CTENMEM EN CL CT CB EN CL CTENHEC CTENHT EN CL CTENHT OE ON OC TM TE TN QN QC AB NV RM RV CB EN CL...
Page 126 CHAPTER 4 INTERNAL REGISTERS UCthUEP UCthUBR UCthAEP UCthABR UCthNVR UCthRM UCthRVR UCthCBR MQthUBR MQthABR MQthRNV MQthCRV OQthUCL OQthUCI OQthUEP OQthUBR OQthACL OQthACI OQthAEP OQthABR OQthRCL OQthRCI OQthNVR OQthRM OQthCCL OQthRVR OQthCBR...
Page 127 CHAPTER 4 INTERNAL REGISTERS PT23 SG EN SC RP PT22 SG EN SC RP PT21 SG EN SC RP PT20 SG EN SC RP PT19 SG EN SC RP PT18 SG EN SC RP PT17 SG EN SC RP PT16 SG EN SC RP PT15...
Page 128 CHAPTER 4 INTERNAL REGISTERS PERIOD PERIOD PT23 PT22 PT21 PT20 PT19 PT18 PT17 PT16 PT15 PT14 PT13 PT12 PT11 PT10...
Page 129 CHAPTER 4 INTERNAL REGISTERS HT23 NVCI BASE NVPC HT22 BASE NVPC NVCI HT21 BASE NVCI NVPC HT20 NVCI BASE NVPC HT19 BASE NVPC NVCI HT18 BASE NVPC NVCI HT17 BASE NVPC NVCI HT16 BASE NVPC NVCI HT15 BASE NVPC NVCI HT14 BASE NVPC...
Page 130 CHAPTER 4 INTERNAL REGISTERS...
Page 131 CHAPTER 4 INTERNAL REGISTERS...
Page 132 CHAPTER 4 INTERNAL REGISTERS...
Page 133: Register Functions
CHAPTER 4 INTERNAL REGISTERS 4.3 Register Functions This section explains the registers of the µ PD98410. The shaded portions in the descriptions below indicates a reserved area. Write “0” to the bits of a reserved area. These bits are “don’t care” when they are read. 4.3.1 Command register (0000h) Register name Address...
Page 134: Memory Bank Register (0004H)
CHAPTER 4 INTERNAL REGISTERS 4.3.2 Memory bank register (0004h) Register name Address Default BANK 0004h xxxx_xxxx_x000_0000 BANK Field Function Default Value BANK bit [6:0] These bits specify a bank used to access the external memory when the 16-bit separated asynchronous bus interface is used. For details, refer to 3.11 Microprocessor Interface.
Page 135 CHAPTER 4 INTERNAL REGISTERS Field Function Default Value bit [14] This bit sets the byte alignment of the microprocessor to be connected. Because the default value after reset is little endian, care must be exercised if a microprocessor with a big endian interface accesses this register after reset.
Page 136: Interrupt Mask Register (0008H)
CHAPTER 4 INTERNAL REGISTERS 4.3.4 Interrupt mask register (0008h) Register name Address Default INTMASK 0008h x000_00xx_0000_0xxx_xxxx_xxxx_xxx0_0000 CHE CHT The INTMASK register masks an interrupt that occurs when the corresponding status becomes active. Indication by the status register is not masked. Each bit of this register can be set in the same manner. For the cause of an interrupt, refer to the description of the status register.
Page 137: Status Register (000Ch)
CHAPTER 4 INTERNAL REGISTERS 4.3.5 Status register (000Ch) Register name Address Default STATUS 000Ch 0000_00xx_0000_0xxx_xxxx_xxxx_xxx0_0000 R/W or R CHE CHT The status register is set when the corresponding cause becomes active. An interrupt occurs for the corresponding interrupt cause, except for the BY bit. When this register is read it indicates the current status, and when it is written the status is cleared.
Page 138 CHAPTER 4 INTERNAL REGISTERS Field Function Default Value bit [30] Indicates a parity error in the HTT & control memory. bit [29] Indicates a parity error in the cell buffer memory. bit [28] Indicates an overrun of the input FIFO at the reception side. bit [27] Indicates an abnormal status in the pointer that manages the queue.
Page 139: Threshold Value Exceeding Discard Indication Mask Register (0010H)
CHAPTER 4 INTERNAL REGISTERS 4.3.6 Threshold value exceeding discard indication mask register (0010h) Register name Address Default EXTHMS 0010h 0000_000x_0xx0_0x00_x0x0_0000_xxxx_xxxx The EXTHMS register masks the use of the EXTH register to indicate when a threshold value is expected. Exceeding of a threshold value is reflected on the EX bit of the status register and an interrupt cause by setting the corresponding threshold value cause and condition of the corresponding class to the EXTHMS register.
Page 140 CHAPTER 4 INTERNAL REGISTERS Even if a cell is discarded because of the class of threshold value masked by the EXTHMS register, it is not reflected on the EXTH register. Nor is the EX bit of the status register set. bit [31 through 25, 23, 19, 17, 16] OM, OE, ON, OC, TM, TE, TN, MM, QM, QN, QC 0: Indicates that the corresponding class did not bring about discarding a cell first.
Page 141 CHAPTER 4 INTERNAL REGISTERS Field Function Default Value bit [17] Indicates that the cell of the channel not set for EPD is discarded because the output queue exceeds OQthAEP or OQthUEP threshold value during re-queuing of multi-cast, or the UC (Used Cell) counter exceeds UCthAEP or UCthUEP threshold value.
Page 142: Header Translation Error Discard Indication Register (0018H)
CHAPTER 4 INTERNAL REGISTERS 4.3.8 Header translation error discard indication register (0018h) Register name Address Default ERHT 0018h 0000_00xx_xxx1_1111 The ERHT register indicates a header translation error and an input port that are responsible for the first cell discarding after the HT bit of the status register has been cleared. When a cell is discarded, the corresponding bit of this register is set and, at the same time, the HT bit of the status register is set.
Page 143 CHAPTER 4 INTERNAL REGISTERS Field Function Default Value bit [10] Indicates that a cell has been discarded because an attempt was made to merge the RM cells of channels that were disabled (CEN = “0”) or because an attempt was made to merge the RM cells of a channel set in the single cast mode (CM = “0”) when the µ...
Page 144: Hec/Crc Error Discard Indication Register (001Ah)
CHAPTER 4 INTERNAL REGISTERS 4.3.9 HEC/CRC error discard indication register (001Ah) Register name Address Default ERHEC 001Ah 00xx_xxxx_xxx1_1111 The ERHEC register indicates an HEC error or CRC-10 error and an input port responsible for the first discarding of a cell after the HE bit of the status register has been cleared. When a cell is discarded, the corresponding bit of this register is set and, at the same time, the HE bit of the status register is set.
Page 145: Input Port Overrun Error Discard Indication Register (001Ch)
CHAPTER 4 INTERNAL REGISTERS 4.3.10 Input port overrun error discard indication register (001Ch) Register name Address Default ERINOV 001Ch xxxx_xxxx_xxxx_0000 UPN3 UPN2 UPN1 UPN0 The ERINOV register indicates a port number of the UTOPIA receive interface that has caused a cell to be discarded.
Page 146: Threshold Value Exceeding Discard Cell Count Enable Register (0020H)
CHAPTER 4 INTERNAL REGISTERS 4.3.11 Threshold value exceeding discard cell count enable register (0020h) Register name Address Default CTENTH 0020h 0000_000x_0xxx_0x00_x0x0_0000_00x0_0000 The CTENTH register specifies the conditions under which cells discarded because a threshold value is exceeded are counted. The count value is indicated by the CTEXTH register. The CTENTH register gives the conditions of the corresponding threshold value, class, and output port, and enables counting the number of discarded cells by using the EN bit.
Page 147: Header Translation Error Discard Cell Count Enable Register (0024H)
CHAPTER 4 INTERNAL REGISTERS 4.3.12 Header translation error discard cell count enable register (0024h) Register name Address Default CTENHT 0024h xxxx_xxxx_00x0_0000 The CTENHT register specifies a logical input port that counts the number of cells discarded because a header translation error occurs. The counted value is indicated by the CTERHT register. IPN gives a condition, and the EN bit enables counting.
Page 148: Hec/Crc Error Discard Cell Count Enable Register (0026H)
CHAPTER 4 INTERNAL REGISTERS 4.3.13 HEC/CRC error discard cell count enable register (0026h) Register name Address Default CTENHEC 0026h xxxx_xxxx_00x0_0000 The CTENHEC register specifies a logical input port that counts the number of cells discarded because an HEC or CRC error occurs. The counted value is indicated by the CTERHEC register. IPN givens a condition, and the EN bit enables counting.
Page 149: Control/Cell Buffer Memory Shortage Discard Cell Count Enable Register (0028H)
CHAPTER 4 INTERNAL REGISTERS 4.3.14 Control/cell buffer memory shortage discard cell count enable register (0028h) Register name Address Default CTENMEM 0028h 00xx_xxxx_00xx_xxxx The CTENMEM register specifies whether the number of cells discarded because the vacant control area of the HTT & control memory or the vacant area of the cell buffer memory has run short is counted. The counted value is not indicated by the CTMEMEMP register.
Page 150: Receive Cell Count Enable Register (002Ah)
CHAPTER 4 INTERNAL REGISTERS 4.3.15 Receive cell count enable register (002Ah) Register name Address Default CTENRCV 002Ah xxxx_xxxx_00xx_0000 UPN3 UPN2 UPN1 UPN0 The CTENRCV register specifies whether the number of cells received by each UTOPIA interface port is counted. The counted value is indicated by the CTRCV register. The EN bit enables counting. Field Function Default Value...
Page 151: Receive Cell Count Register (002Ch)
CHAPTER 4 INTERNAL REGISTERS 4.3.16 Receive cell count register (002Ch) Register name Address Default CTRCV 002Ch 0000_0000_0000_0000_0000_0000_0000_0000 CTRCV CTRCV The CTRCV register indicates the number of cells received under the condition specified by the CTENRCV register. The number of cells is counted while EN of the CTENRCV register is “1”. The value of this register is cleared when the reset signal is applied to the µ...
Page 152: Threshold Value Exceeding Discard Cell Count Register (0030H)
CHAPTER 4 INTERNAL REGISTERS 4.3.17 Threshold value exceeding discard cell count register (0030h) Register name Address Default CTEXTH 0030h 0000_0000_0000_0000_0000_0000_0000_0000 CTEXTH CTEXTH The CTEXTH register indicates the number of cells discarded under the condition specified by the CTENTH register. Counting is performed when EN of the CTENTH register is “1”, and is cleared when the reset signal is applied to the µ...
Page 153: Header Translation Error Discard Cell Count Register (0034H)
CHAPTER 4 INTERNAL REGISTERS 4.3.18 Header translation error discard cell count register (0034h) Register name Address Default CTERHT 0034h 0000_0000_0000_0000_0000_0000_0000_0000 CTERHT CTERHT The CTERTH register indicates the number of cells discarded under the condition specified by the CTENHT register. Counting is performed when EN of the CTENHT register is “1”, and is cleared when the reset signal is applied to the µ...
Page 154: Hec/Crc Error Discard Cell Count Register (0038H)
CHAPTER 4 INTERNAL REGISTERS 4.3.19 HEC/CRC error discard cell count register (0038h) Register name Address Default CTERHEC 0038h 0000_0000_0000_0000_0000_0000_0000_0000 CTERHEC CTERHEC The CTERHEC register indicates the number of cells discarded under the condition specified by the CTENHEC register. Counting is performed when EN of the CTENHEC register is “1”, and is cleared when the reset signal is applied to the µ...
Page 155: Control/Cell Buffer Memory Shortage Discard Cell Count Register (003Ch)
CHAPTER 4 INTERNAL REGISTERS 4.3.20 Control/cell buffer memory shortage discard cell count register (003Ch) Register name Address Default CTMEMEMP 003Ch 0000_0000_0000_0000_0000_0000_0000_0000 CTMEMEMP CTMEMEMP The CTMEMEMP register indicates the number of cells discarded because the vacant area in the control memory or cell buffer memory has run short.
Page 156: Output Queue Minimum Threshold Value Registers (0040H, 0044H, 0048H, 004Ch)
CHAPTER 4 INTERNAL REGISTERS 4.3.21 Output queue minimum threshold value registers (0040h, 0044h, 0048h, 004Ch) Register name Address Default OQminCRV 0040h xxxx_xxxx_000x_xxxx OQminRNV 0044h xxxx_xxxx_000x_xxxx OQminABR 0048h xxxx_xxxx_000x_xxxx OQminUBR 004Ch xxxx_xxxx_000x_xxxx OQminCRV OQminRNV OQminABR OQminUBR These registers specify the minimum number of guaranteed cells for each logical output port. Be sure to set the minimum threshold value before enabling the switching operation by using the CMD register.
Page 157: Multi-Cast Queue Minimum Threshold Value Registers (0050H, 0054H, 0058H, 005Ch)
CHAPTER 4 INTERNAL REGISTERS 4.3.22 Multi-cast queue minimum threshold value registers (0050h, 0054h, 0058h, 005Ch) Register name Address Default MQminCRV 0050h xxxx_xxxx_000x_xxxx MQminRNV 0054h xxxx_xxxx_000x_xxxx MQminABR 0058h xxxx_xxxx_000x_xxxx MQminUBR 005Ch xxxx_xxxx_000x_xxxx MQminCRV MQminRNV MQminABR MQminUBR These registers specify the minimum number of guaranteed cells for the multi-cast in each class. Be sure to set the minimum threshold value before enabling the switching operation by using the CMD register.
Page 158: Tc (Total Cell) Counter Minimum Threshold Registers (0060H, 0064H, 0068H, 006Ch)
CHAPTER 4 INTERNAL REGISTERS 4.3.23 TC (Total Cell) counter minimum threshold registers (0060h, 0064h, 0068h, 006Ch) Register name Address Default TCminCRV 0060h xx00_0000_0xxx_xxxx TCminRNV 0064h 0000_0000_0xxx_xxxx TCminABR 0068h 0000_0000_0xxx_xxxx TCminUBR 006Ch 0000_0000_0xxx_xxxx TCminCRV TCminRNV TCminABR TCminUBR These registers specify the minimum number of guaranteed cells for each class. The minimum number of cells guaranteed for each class is counted after the number of cells has exceeded the minimum number of guaranteed cells for each logical output port.
Page 159: Total Number Of Cells Minimum Threshold Value Register (007Eh)
CHAPTER 4 INTERNAL REGISTERS 4.3.24 Total number of cells minimum threshold value register (007Eh) Register name Address Default ALLmin 007Eh 0000_0000_000x_xxxx ALLmin The ALLmin register specifies the total of the minimum number of guaranteed cells. Before enabling the switching operation by using the CMD register, be sure to set the value calculated by the following expression to the CMD register.
Page 160: Output Queue Maximum Threshold Value Registers
CHAPTER 4 INTERNAL REGISTERS 4.3.25 Output queue maximum threshold value registers (0080h, 0082h, 0090h, 0092h, 00A0h, 00B0h) Register name Address Default OQthCBR 0080h xxxx_xxx0_000x_xxxx OQthRVR 0082h xxxx_xxx0_000x_xxxx OQthRM 0090h xxxx_0000_0xxx_xxxx OQthNVR 0092h xxxx_0000_0xxx_xxxx OQthABR 00A0h xxx0_0000_0xxx_xxxx OQthUBR 00B0h 0000_0000_0xxx_xxxx OQthCBR TCminRNV OQthRVR OQthRM...
Page 161: Output Queue Epd Threshold Value Registers (00A2H, 00B2H)
CHAPTER 4 INTERNAL REGISTERS Remarks 1. OQthCBR and OQthRVR are the threshold values for the same output queue. 2. OQthRM and OQthNVR are the threshold values for the same output queue. 3. For cells in ABR and UBR classes for which EPD is disabled, OQthAEP and OQthUEP are the upper-limit threshold values.
Page 162: Output Queue Efci Threshold Value Registers (0094H, 00A4H, 00B4H)
CHAPTER 4 INTERNAL REGISTERS 4.3.27 Output queue EFCI threshold value registers (0094h, 00A4h, 00B4h) Register name Address Default OQthRCI 0094h xxxx_0000_0xxx_xxxx OQthACI 00A4h xxx0_0000_0xxx_xxxx OQthUCI 00B4h 0000_0000_0xxx_xxxx OQthRCI OQthACI OQthUCI These registers set the EFCI threshold value of each logical output port in each class. If a cell in each class is congested in the output queue, exceeding the corresponding threshold value, EFCI marking is performed of the user cells and CI/NI marking is performed for the backward RM cells.
Page 163: Output Queue Clp Threshold Value Registers (0086H, 0096H, 00A6H, 00B6H)
CHAPTER 4 INTERNAL REGISTERS 4.3.28 Output queue CLP threshold value registers (0086h, 0096h, 00A6h, 00B6h) Register name Address Default OQthCCL 0086h xxxx_xxx0_000x_xxxx OQthRCL 0096h xxxx_0000_0xxx_xxxx OQthACL 00A6h xxx0_0000_0xxx_xxxx OQthUCL 00B6h 0000_0000_0xxx_xxxx OQthCCL OQthRCL OQthACL OQthUCL These registers set the CLP threshold value of each logical output port in each class. If a cell in each class is congested in the output queue, exceeding the corresponding threshold value, the cell for which CLP is set is discarded.
Page 164: Multi-Cast Queue Maximum Threshold Value Registers (00C0H, 00C4H, 00C8H, 00Cch)
CHAPTER 4 INTERNAL REGISTERS 4.3.29 Multi-cast queue maximum threshold value registers (00C0h, 00C4h, 00C8h, 00CCh) Register name Address Default MQthCRV 00C0h xxxx_xxx0_000x_xxxx MQthRNV 00C4h xxxx_xx00_00xx_xxxx MQthABR 00C8h xxxx_xx00_00xx_xxxx MQthUBR 00CCh xxxx_x000_0xxx_xxxx MQthCRV MQthRNV MQthABR MQthUBR These registers set the upper-limit threshold value of the multi-cast queue in each class. If a cell in each class is congested in the multi-cast queue, exceeding the corresponding threshold value, the cell is discarded.
Page 165: Uc (Used Cell) Counter Maximum Threshold Value Register
CHAPTER 4 INTERNAL REGISTERS 4.3.30 UC (Used Cell) counter maximum threshold value register (00D0h, 00D4h, 00D8h, 00DCh, 00E0h, 00E8h) Register name Address Default UCthCBR 00D0h 0000_0000_0xxx_xxxx UCthRVR 00D4h 0000_0000_0xxx_xxxx UCthRM 00D8h 0000_0000_0xxx_xxxx UCthNVR 00DCh 0000_0000_0xxx_xxxx UCthABR 00E0h 0000_0000_0xxx_xxxx UCthUBR 00E8h 0000_0000_0xxx_xxxx UCthCBR UCthRVR...
Page 166: Uc (Used Cell) Counter Epd Threshold Value Registers (00E2H, 00Eah)
CHAPTER 4 INTERNAL REGISTERS Field Function Default Value UCthABR bit [15:7] 0000_0000_0 to 1111_1111_1: Upper-limit threshold value in ABR 0000_0000_0 class (128-cell units: 0/128/256/ ... /65408) (0000h) UCthUBR bit [15:7] 0000_0000_0 to 1111_1111_1: Upper-limit threshold value in UBR 0000_0000_0 class (128-cell units: 0/128/256/ ...
Page 167: Port Configuration Register
CHAPTER 4 INTERNAL REGISTERS 4.3.32 Port configuration register Register name Address Default PT0-PT23 Note xxxx_xxx0_000x_1111_xxxx_xx00_0000_0000 Note 0100h, 0104h, 0108h, 010Ch, 0110h, 0114h, 0118h, 011Ch, 0120h, 0124h, 0128h, 012Ch, 0130h, 0134h, 0138h, 013Ch, 0140h, 0144h, 0148h, 014Ch, 0150h, 0154h, 0158h, 015Ch These registers are used to map physical ports to logical ports.
Page 168 CHAPTER 4 INTERNAL REGISTERS Field Function Default Value bit [8] Enables successive output to the same logical output port. 0: Does not performs successive output to the same logical output port. 1: Performs successive output to the same logical output port. Refer to 3.6 Successive Transmission.
Page 169: Class Priority Control Register
CHAPTER 4 INTERNAL REGISTERS 4.3.33 Class priority control register Register name Address Default PC0-PC23 xxxx_x000_xxxx_x001_x000_0001_x000_0001 Note Note 0180h, 0184h, 0188h, 018Ch, 0190h, 0194h, 0198h, 019Ch, 01A0h, 01A4h, 01A8h, 01ACh, 01B0h, 01B4h, 01B8h, 01BC0h, 01C0h, 01C4h, 01C8h, 01CCh, 01D0h, 01D4h, 01D8h, 01DCh These registers specify class priority control for each logical output port.
Page 170: Cycle Count Register (01Fch)
CHAPTER 4 INTERNAL REGISTERS 4.3.34 Cycle count register (01FCh) Register name Address Default PERIOD 01FCh xxxx_xxxx_0000_0001 PERIOD This register specifies the cycle of PC0 through PC23, CBR, and VBR. It performs class priority control of each logical output port, as well as setting of CBR and VBR for PC0 through PC23. Field Function Default Value...
Page 171: Header Translation Configuration Register
CHAPTER 4 INTERNAL REGISTERS 4.3.35 Header translation configuration register Register name Address Default HT0-HT23 Note x000_0x00_000x_xxxx_0000_0000_00xx_xxxx NVPC NVCI BASE Note 0200h, 0204h, 0208h, 020Ch, 0210h, 0214h, 0218h, 021Ch, 0220h, 0224h, 0228h, 022Ch, 0230h, 0234h, 0238h, 023Ch, 0240h, 0244h, 0248h, 024Ch, 0250h, 0254h, 0258h, 025Ch This register is used to translate VPI and VCI of a received cell into the addresses of the header translation table (HTT), to translate the OVPC specified in HTT into VPC and VCI of a transmit cell, and specified NNI/UNI, for each logical output port.
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Page 173: Chapter 5 Jtag Boundary Scan
CHAPTER 5 JTAG BOUNDARY SCAN The µ PD98410 has a JTAG boundary scan circuit. 5.1 Features • Conforms to IEEE1149.1 JTAG Boundary Scan Standard. • Three registers dedicated to boundary scan · Instruction register · Bypass register · Boundary scan register •...
Page 174: Internal Configuration Of Boundary Scan Circuit
CHAPTER 5 JTAG BOUNDARY SCAN 5.2 Internal Configuration of Boundary Scan Circuit Figure 5-1 shows the block diagram of the internal JTAG boundary scan circuit of the µ PD98410. Figure 5-1. Block Diagram of Boundary Scan Circuit Boundary scan register Bypass register Output buffer Instruction decoder...
Page 175: Pin Function
CHAPTER 5 JTAG BOUNDARY SCAN 5.3 Pin Function 5.3.1 JCK (JTAG Clock) pin The JCK pin is used to supply a clock signal to the JTAG boundary scan circuit (such as the bypass register, instruction register, and TAP controller. This clock signal is isolated so as not to be supplied to the other internal circuits of the µ...
Page 176: Operation Description
CHAPTER 5 JTAG BOUNDARY SCAN 5.4 Operation Description 5.4.1 TAP controller The TAP controller is a circuit having 16 states synchronized with changes of the JMS and JCK pins. Its operation is specified by IEEE Standard 1149.1. 5.4.2 TAP controller state Figure 5-2 shows the state transition of the TAP controller.
Page 177 CHAPTER 5 JTAG BOUNDARY SCAN Figure 5-3. Operation Timing in Controller State Controller state Enters state Starts in state Starts in state at rising edge of JCK pin at rising edge of JCK pin (1) Test-Logic-Reset The boundary scan circuit performs no operation on the µ PD98410. Therefore, it does not affect the system logic of the µ...
Page 178 CHAPTER 5 JTAG BOUNDARY SCAN (4) Select-IR-Scan This is a temporary boundary scan state. The boundary scan register and bypass register selected by the current instruction hold the previous state. If the JMS signal is held low at the rising edge of the JCK pin signal while the TAP controller is in this state, the controller enters the Capture-IR state, and scan sequence to the selected registers is started.
Page 179 CHAPTER 5 JTAG BOUNDARY SCAN (9) Exit2-DR This is a temporary controller state. If the JMS pin signal is held high at the rising edge of the JCK pin signal with the TAP controller in this state, the controller enters the Update-DR state. This ends the scan process. If the JMS pin signal is held low at the rising edge of the JCK pin signal, the TAP controller enters the Shift-DR state.
Page 180 CHAPTER 5 JTAG BOUNDARY SCAN (13) Exit1-IR This is a temporary controller state. If the JMS pin signal is held high at the rising edge of the JCK pin signal, the TAP controller enters the Update-IR state. This ends the scan process. If the JMS pin signal is held low at the rising edge of the JCK pin, the TAP controller enters the Pause-IR state.
Page 181: Tap Controller Operation
CHAPTER 5 JTAG BOUNDARY SCAN 5.5 TAP Controller Operation The TAP controller operates as follows. The state of the controller is changed by either of (1) and (2) below. (1) Rising edge of JCK pin signal (2) JRST_B pin input The TAP controller generates signals that control the operations of the bypass register, boundary scan register, and instruction register defined by the IEEE1149.1 JTAG Boundary Scan Standard (refer to Figures 5-4 and 5-5).
Page 182 CHAPTER 5 JTAG BOUNDARY SCAN Figure 5-4. Operation of Test Logic (instruction scan) JCK pin signal JMS pin signal Controller state JDI pin signal Input data to IR IR shift register Parallel output of IR Bypass New instruction Note Input data to TDR TDR shift register Parallel output of TDR Old data...
Page 183 CHAPTER 5 JTAG BOUNDARY SCAN Figure 5-5. Operation of Test Logic (data scan) JCK pin signal JMS pin signal Controller state JDI pin signal Input data to IR IR shift register Instruction Bypass Parallel output of IR Note Input data to TDR TDR shift register Old data New data...
Page 184: Initializing Tap Controller
CHAPTER 5 JTAG BOUNDARY SCAN 5.6 Initializing TAP Controller The TAP controller is initialized as follows: (1) The TAP controller is not initialized by the operation of system input such as system reset. (2) The TAP controller enters the Test-Logic-Reset controller state at the fifth rising edge of the JCK pin signal (while the JMS pin signal is held high).
Page 185: Bypass Instruction
JCK pin signal while the TAP controller is in the Capture-DR state. 5.8 Boundary Scan Data Bit Definition NEC will provide the BSDL (Boundary Scan Description Language) file for the µ PD98410 upon request. For details, call NEC Semiconductor Technical Hot Line shown at the end of this document.
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Page 187: Chapter 6 Limitations
CHAPTER 6 LIMITATIONS The K model of the µ PD98410 has the following 11 limitations. 6.1 Limitations (1) Error in 52-byte short cell reception (2) Error in cell transmission when multi-PHY mode is changed (3) Limitation of logical port mapping (output of congested cell) (4) Limitation when operation command is issued (5) Limitation of logical port mapping (output of illegal cell) (6) Limitation of logical port mapping (mapping of unconnected PHY)
Page 188: Description Of Limitations
CHAPTER 6 LIMITATIONS 6.2 Description of Limitations (1) Error in 52-byte short cell reception <Phenomenon> If the following two conditions are satisfied at the same time, the cell following a short cell of 52 bytes is lost. (a) When RXSOC (input of a high level to the RXSOC pin) is received at the P48 (payload 48) timing of a received cell (b) When a PHY device that can be transferred next is received before reception of RXSOC in (a) The µ...
Page 189 CHAPTER 6 LIMITATIONS (5) Limitation of logical port mapping (output of illegal cell) <Phenomenon> If the mapping of a logical port is changed while it is active (EN bit = 1), one cell may be output to the new PHY address on UTOPIA immediately before the change.
Page 190 <Remedy> Do not connect too many devices. There is no problem when connecting two NEC’s 155M-PHY ( µ PD98404s) to one UTOPIA port, or when connecting two 6-port 25M-PHY ( µ PD98408s) to one UTOPIA port. (9) Error in queue management <Phenomenon>...
Page 191 CHAPTER 6 LIMITATIONS (10) Queue management malfunctioning due to unmatched broadcast count and problem of timing of reusing Area-B <Phenomena> If multi-cast connection is added, changed, or deleted while the µ PD98410 operates, the following two phenomena may occur. [Problem 1] Queue management malfunctioning due to mismatching broadcast count If the broadcast count is changed for multi-cast connection, and if the cells of the corresponding connection are congested, queue management malfunctions.
Page 192 CHAPTER 6 LIMITATIONS [Initial setting] • Divide the Area-B of the HTT memory by each broadcast count and use the same area for connection of the same broadcast count. Even if Area-B is changed during re-queuing, broadcast count is not unmatched because it is the same before and after the change, and queue management does not malfunction (in the example below, 2048 channels are used as the area of Area-B, and a dedicated area is prepared for each broadcast count where broadcast count is 2 to 24).
Page 193 CHAPTER 6 LIMITATIONS <Effect of remedy> Problem 1 can be prevented by taking the above remedial action. It is considered that Problem 2 can be almost completely prevented in actual operating conditions, however, there is no perfect remedy. This is because whether all the cells congested in the queue of each channel have been output cannot be known.
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Page 195: Chapter 7 Faq (Frequently Asked Questions)
What are the recommended soldering conditions? Refer to Condition IR20-202-3 in NEC’s Semiconductor Device Mounting Technology Manual (C10535E). How should X10 be set to output an input cell of VCI = 0 to a specific output port, regardless of the VPI value? It is necessary to set parameters for all the VPI values on the HTT (Header Translation Table) memory before starting a switching operation.
Page 196 CHAPTER 7 FAQ (Frequently Asked Questions) How fast should the access speed of the SRAM that is connected as the cell buffer memory or HTT & control memory be? SRAM of 15 ns is recommended, though the access speed differs depending on the number of SRAMs to be connected and wiring length.
Page 197 CHAPTER 7 FAQ (Frequently Asked Questions) (1) In what sequence are cells output to an actual port from the output queue of each logical output port? Are they output in a simple round-robin mode? If a cell exists in a specific queue such as the CBR queue, does that cell take precedence, or not? (2) CBR and rt-VBR are in the same output queue.
Page 198 CHAPTER 7 FAQ (Frequently Asked Questions) Q.11 This is a question related to the WFQ operation. When a time out of the cycle counter occurs, are the present values of C and C counters and the set value of the class priority control register loaded to C and C counters? A.11...
Page 199 CHAPTER 7 FAQ (Frequently Asked Questions) Q.13 How much is the output (re-queuing) throughput of the multi-cast queue? A.13 The HTT & control memory is accessed in the following three ways during re-queuing of the multi-cast cell (= cell storage address copy): •...
Page 200 CHAPTER 7 FAQ (Frequently Asked Questions) Q.14 While X10 receives a cell from a certain PHY (e.g., PHY#1), it selects PHY#1 again after it has received the cell if the result of polling the other PHY devices is no good. At this time, does RXENB_B go high again as shown below? UCLK RXADDR [3:0]...
Page 201 CHAPTER 7 FAQ (Frequently Asked Questions) Q.16 Give me an example of interrupt processing. A.16 The microprocessor detects the low level of the INT_B pin. → Read the status register (STATUS) and recognize the interrupt cause. The processing branches depending on the interrupt cause. (1) Parity error (PH, PC = 1) The microprocessor resets X10.
Page 202 CHAPTER 7 FAQ (Frequently Asked Questions) Q.17 Give me an example of changing the setting of the HTT memory. A.17 (1) Single cast [To register new single cast connection] Set connection information in Area-A. Remark When the 16-bit separated asynchronous bus mode is used, the procedure is “setting of HTT [15:0] →...
Page 203 CHAPTER 7 FAQ (Frequently Asked Questions) Q.18 How the header translation operation is performed in the case of V switching and single cast? A.18 Let’s assume the case where an input cell of UTOPIA interface = 0h, PHY address = 1h, VPI = 02h, and VCI = 0034h is output to UTOPIA interface = 1h, PHY address = 2h, VPI = 03h, VCI = 0045h.
Page 204 CHAPTER 7 FAQ (Frequently Asked Questions) Figure 7-2. Header Translation Flow (reception side) NVPC NVCI BASE PT register HT register PT24 HT24 • • • • • • • • 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 0 1...
Page 205 CHAPTER 7 FAQ (Frequently Asked Questions) Figure 7-3. Header Translation Flow (transmission side) NVPC NVCI BASE PT register HT register PT24 HT24 • • • • • • • • 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 0 1...
Page 206 CHAPTER 7 FAQ (Frequently Asked Questions) Q.19 Give me a specific mapping example of the HTT memory. A.19 For example, if the HT23 through HT0 registers are set as shown in Figure 7-4, the mapping of the HTT memory is as shown in Figure 7-5.
Page 207 CHAPTER 7 FAQ (Frequently Asked Questions) Figure 7-5. Example of HTT Memory Mapping Example 1M-bits (×18) SRAM × 7 HTT pointer Memory address HTT Area-A VPI = 0-3 3FFFh 0FFFFh 512-channel 3E00h 0F800h VCI = 0-127 VPI = 0-3 512-channel 3C00h 0F000h VCI = 0-127...
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Page 209 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

NEC mPD98410 User Manual

Chapter 1 General

Chapter 2 Pin Functions

Chapter 3 Functional Outline

Chapter 4 Internal Registers

Chapter 5 Jtag Boundary Scan

Chapter 6 Limitations

CHAPTER 7 FAQ (Frequently Asked Questions)

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