Page 1 User’s Manual V850E/IA1 32-Bit Single-Chip Microcontrollers Hardware µ PD703116 µ PD703116(A) µ PD703116(A1) µ PD70F3116 µ PD70F3116(A) µ PD70F3116(A1) Document No. U14492EJ5V0UD00 (5th edition) Date Published August 2005 N CP(K) 1999, 2002 Printed in Japan...
Page 2 [MEMO] User’s Manual U14492EJ5V0UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 INTRODUCTION Readers This manual is intended for users who wish to understand the functions of the V850E/IA1 and design application systems using it. The target products are as follows. µ • Standard products: PD703116, 70F3116 µ • Special products: PD703116(A), 703116(A1), 70F3116(A), 70F3116(A1) Purpose This manual introduces the hardware functions of the V850E/IA1 shown below for user’s understanding.
Page 7 • To understand the overall functions of the V850E/IA1 → Read this manual according to the CONTENTS. • How to read register formats → The name of a bit whose number is in angle brackets (<>) is defined as a reserved word in the device file.
Page 8 Documents related to development tools (User’s Manuals) Document Name Document No. IE-V850E-MC, IE-V850E-MC-A (In-circuit emulator) U14487E IE-703116-MC-EM1 (In-circuit emulator option board) U14700E CA850 (Ver. 3.00) (C compiler package) Operation U17293E C Language U17291E Assembly Language U17292E Link Directives U17294E PM+ (Ver. 6.00) (Project manager) U17178E ID850 (Ver.
Page 9: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION .........................18 Outline............................18 Features ............................. 21 Applications..........................23 Ordering Information ........................ 23 Pin Configuration (Top View)....................24 Configuration of Function Block..................... 26 1.6.1 Internal block diagram ........................26 1.6.2 Internal units..........................27 Differences Between Products ....................29 CHAPTER 2 PIN FUNCTIONS ........................30 List of Pin Functions ........................
Page 10 4.3.1 Chip select control function ....................... 102 Bus Cycle Type Control Function ..................105 Bus Access ..........................106 4.5.1 Number of access clocks......................106 4.5.2 Bus sizing function........................107 4.5.3 Word data processing format..................... 107 4.5.4 Bus width ........................... 108 Wait Function...........................
Page 11 DMA Channel Priorities ......................147 Next Address Setting Function ..................... 147 DMA Transfer Start Factors ....................149 6.10 Forcible Interruption....................... 150 6.11 DMA Transfer End........................150 6.12 Forcible Termination ......................151 6.12.1 Restriction related to DMA transfer forcible termination .............152 6.13 Times Related to DMA Transfer.....................
Page 12 Power Save Control ........................ 204 8.5.1 Overview ........................... 204 8.5.2 Control registers ........................207 8.5.3 HALT mode ..........................210 8.5.4 IDLE mode..........................212 8.5.5 Software STOP mode........................ 214 Securing Oscillation Stabilization Time................216 8.6.1 Oscillation stabilization time security specification..............216 8.6.2 Time base counter (TBC) ......................
Page 13 Timer Connection Function ....................408 9.6.1 Overview ............................408 9.6.2 Control register...........................409 CHAPTER 10 SERIAL INTERFACE FUNCTION ................410 10.1 Features ........................... 410 10.2 Asynchronous Serial Interface 0 (UART0) ................411 10.2.1 Features .............................411 10.2.2 Configuration ..........................412 10.2.3 Control registers .........................414 10.2.4 Interrupt requests ........................421 10.2.5 Operation ...........................422...
Page 14 11.8.6 Error control function ......................... 536 11.8.7 Baud rate control function......................539 11.9 Cautions on Bit Set/Clear Function..................542 11.10 Control Registers ........................544 11.11 Operations ..........................596 11.11.1 Initialization processing ......................596 11.11.2 Transmit setting ......................... 609 11.11.3 Receive setting .......................... 610 11.11.4 CAN sleep mode ........................
Page 15 13.7.1 Operation in select mode ......................662 13.7.2 Operation in scan mode ......................663 13.8 Operation in Timer Trigger Mode ..................664 13.8.1 Operation in select mode ......................664 13.8.2 Operation in scan mode ......................665 13.9 Operation in External Trigger Mode..................666 13.9.1 Operation in select mode ......................666 13.9.2 Operation in scan mode ......................667...
Page 16 16.3 Programming Environment....................729 16.4 Communication Mode......................729 16.5 Pin Connection ........................731 16.5.1 pin ............................731 16.5.2 Serial interface pin........................731 16.5.3 RESET pin..........................733 16.5.4 NMI pin ............................733 16.5.5 MODE0 to MODE2 pins ......................733 16.5.6 Port pins ............................ 733 16.5.7 Other signal pins........................
Page 17 APPENDIX B REGISTER INDEX......................792 APPENDIX C INSTRUCTION SET LIST....................803 Functions ..........................803 Instruction Set (Alphabetical Order) ..................806 APPENDIX D REVISION HISTORY ......................812 Major Revisions in This Edition .................... 812 Revision History up to Previous Edition ................814 User’s Manual U14492EJ5V0UD...
Page 18: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850E/IA1 is a product in the V850 Series of NEC Electronics Corporation single-chip microcontrollers. This chapter provides an overview of the V850E/IA1. 1.1 Outline The V850E/IA1 is a 32-bit single-chip microcontroller that realizes high-precision inverter control of a motor due to high-speed operation.
Page 19 100-pin plastic LQFP 100-pin plastic QFP Note The maximum operating frequency of the in-circuit emulator is 40 MHz. A frequency of 50 MHz can be supported by upgrading the in-circuit emulator, so contact an NEC Electronics sales representative or distributor. Remark For details, refer to the user’s manual of each product.
Page 20 CHAPTER 1 INTRODUCTION Table 1-2. Differences Between V850E/IA1 and V850E/IA2 Register Setting Values Note Register Name V850E/IA1 V850E/IA2 System wait control register (VSWC) Timer 1/timer 2 clock selection register 00H or 01H 01H (initial value 00H) (PRM02) Notes 1. Setting the TESnE1 and TESnE0 bits of timer 2 count clock/control edge select register 0 (CSE0) to 11B (both rising/falling edges) is prohibited when the PRM2 bit of the timer 1/timer 2 clock selection register (PRM02) is 1B (f Set the VSWC register to 15H when the PRM2 bit of the timer 1/timer 2 clock selection register...
Page 21: Features
CHAPTER 1 INTRODUCTION 1.2 Features Number of instructions Minimum instruction execution time 20 ns (@ internal 50 MHz operation) 32 bits × 32 registers General-purpose registers Instruction set V850E1 CPU Signed multiplication (32 bits × 32 bits → 64 bits): 1 or 2 clocks Saturated operation instructions (with overflow/underflow detection function) 32-bit shift instruction: 1 clock Bit manipulation instructions...
Page 22 CHAPTER 1 INTRODUCTION DMA controller 4-channel configuration Transfer unit: 8 bits/16 bits Maximum transfer count: 65,536 (2 Transfer type: 2-cycle transfer Transfer modes: Single transfer, single-step transfer, block transfer Memory ↔ Memory, Memory ↔ I/O, I/O ↔ I/O Transfer subjects: Transfer requests: On-chip peripheral I/O, software Next address setting function...
Page 23: Applications
Operating ambient temperature (T Note The maximum operating frequency of the in-circuit emulator is 40 MHz. A frequency of 50 MHz can be supported by upgrading the in-circuit emulator, so contact an NEC Electronics sales representative or distributor. User’s Manual U14492EJ5V0UD...
Page 24: Pin Configuration (Top View)
CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) • 144-pin plastic LQFP (fine pitch) (20 × 20) µ PD703116GJ-xxx-UEN, 703116GJ-xxx-UEN-A, 703116GJ(A)-xxx-UEN, 703116GJ(A)-xxx-UEN-A, µ PD703116GJ(A1)-xxx-UEN, 703116GJ(A1)-xxx-UEN-A, 70F3116GJ-UEN, 70F3116GJ-UEN-A, µ PD70F3116GJ(A)-UEN, 70F3116GJ(A)-UEN-A, 70F3116GJ(A1)-UEN, 70F3116GJ(A1)-UEN-A ANI07 TIUD11/TO11/P13 TCLR10/INTP101/P12 TCUD10/INTP100/P11 TIUD10/TO10/P10 REF1 ANI10 PCM4 ANI11 HLDRQ/PCM3 ANI12...
Page 25 CHAPTER 1 INTRODUCTION Pin Identification A16 to A23: Address bus P20 to P27: Port 2 AD0 to AD15: Address/data bus P30 to P37: Port 3 AD0_DBG to AD3_DBG: Debug address/data bus P40 to P47: Port 4 ADTRG0, ADTRG1: A/D trigger input PCM0 to PCM4: Port CM ANI00 to ANI07,...
Page 26: Configuration Of Function Block
CHAPTER 1 INTRODUCTION 1.6 Configuration of Function Block 1.6.1 Internal block diagram MEMC INTP0 to INTP6 Instruction INTC SRAMC HLDRQ INTP20 to INTP25 queue Note 1 HLDAK INTP30, INTP31 32-bit CS0 to CS7 INTP100, INTP101 barrel Multiplier ROMC INTP110, INTP111 shifter ASTB 32×32...
Page 27: Internal Units
CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses 5-stage pipeline control to execute address calculation, arithmetic and logical operation, data transfer, and most other instruction processing in one clock. A multiplier (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits), barrel shifter (32-bit), and other dedicated hardware are on-chip to accelerate complex instruction processing.
Page 28 CHAPTER 1 INTRODUCTION (9) Timer/counter function This unit incorporates a 2-channel 16-bit timer (TM0) for 3-phase sine wave PWM inverter control, a 2- channel 16-bit up/down counter (TM1) that can be used for 2-phase encoder input or as a general-purpose timer, a 2-channel 16-bit general-purpose timer unit (TM2), a 1-channel 16-bit timer/event counter (TM3), and a 1-channel 16-bit interval timer (TM4) on-chip, and can measure the pulse interval or frequency and can output a programmable pulse.
Page 29: Differences Between Products
CHAPTER 1 INTRODUCTION 1.7 Differences Between Products µ µ µ µ µ µ Item PD703116 PD703116(A) PD703116(A1) PD70F3116 PD70F3116(A) PD70F3116(A1) Internal ROM Mask ROM Flash memory 256 KB Internal RAM 10 KB NBD (Non Break Not provided Provided Debug) function (IC1 to IC4) (TRIG_DBG, AD0_DBG to AD3_DBG, SYNC, CLK_DBG)
Page 30: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS The names and functions of the V850E/IA1 pins are shown below. These pins can be divided by function into port pins and non-port pins. 2.1 List of Pin Functions (1) Port pins (1/3) Pin Name Function Alternate Function Port 0 8-bit input-only port...
Page 31 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Function Alternate Function Port 4 8-bit I/O port Input/output can be specified in 1-bit units. SCK0 SCK1 CRXD CTXD PCM0 Port CM WAIT 5-bit I/O port PCM1 CLKOUT Input/output can be specified in 1-bit units. PCM2 HLDAK PCM3...
Page 32 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Function Alternate Function PDL0 Port DL 16-bit I/O port PDL1 Input/output can be specified in 1-bit units. PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 AD10 PDL11 AD11 PDL12 AD12 PDL13 AD13 PDL14 AD14 PDL15...
Page 33 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/3) Pin Name Function Alternate Function − TO000 Timer 00 pulse signal output − TO001 − TO002 − TO003 − TO004 − TO005 − TO010 Timer 01 pulse signal output − TO011 − TO012 −...
Page 34 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Function Alternate Function INTP100 External maskable interrupt request input and timer 10 external capture P11/TCUD10 trigger input INTP101 P12/TCLR10 INTP110 External maskable interrupt request input and timer 11 external capture P14/TCUD11 trigger input INTP111 P15/TCLR11 INTP20...
Page 35 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Function Alternate Function WAIT Control signal input to insert wait in bus cycle PCM0 HLDAK Bus hold acknowledge output PCM2 HLDRQ Bus hold request input PCM3 External data lower byte write strobe signal output PCT0 External data upper byte write strobe signal output PCT1...
Page 36: Pin Status
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Status The following table shows the status of each pin after a reset, in power-saving mode (software STOP mode, IDLE, HALT), on a DMA transfer, and on a bus hold. Operating Status Reset Reset IDLE Mode/ HALT Mode/ (Single-Chip...
Page 37: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P00 to P07 (Port 0) … Input Port 0 is an 8-bit input-only port in which all pins are fixed for input. Besides functioning as an input port, in control mode, P00 to P07 operate as NMI input, timer/counter output stop signal input, external interrupt request input, and A/D converter (ADC) external trigger input.
Page 38 CHAPTER 2 PIN FUNCTIONS (iii) TCUD10, TCUD11 (Timer control pulse input) … Input These pins input count operation switching signals to the up/down counter (timer 10, timer 11). (iv) TCLR10, TCLR11 (Timer clear) … Input These are clear signal input pins to the up/down counter (timer 10, timer 11). (v) INTP100, INTP101 (External interrupt input) …...
Page 39 CHAPTER 2 PIN FUNCTIONS (4) P30 to P37 (Port 3) … I/O Port 3 is an 8-bit I/O that can be set to input or output in 1-bit units. Besides functioning as an I/O port, in control mode, P30 to P37 operate as serial interface (UART0 to UART2) I/O.
Page 40 CHAPTER 2 PIN FUNCTIONS (v) CRXD (Receive data for controller area network) … Input This pin inputs FCAN serial receive data. (6) PCM0 to PCM4 (Port CM) … I/O Port CM is a 5-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, PCM0 to PCM4 operate as wait insertion signal input, internal system clock output, and bus hold control signal output.
Page 41 CHAPTER 2 PIN FUNCTIONS (7) PCT0 to PCT7 (Port CT) … I/O Port CT is an 8-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, it operates as control signal output for when memory is expanded externally.
Page 42 CHAPTER 2 PIN FUNCTIONS (b) Control mode PCS0 to PCS7 can be set to port or control mode in 1-bit units using PMCCS. (i) CS0 to CS7 (Chip select) … Output This is the chip select signal for external SRAM, external ROM, or external peripheral I/O. The signal CSn is assigned to memory block n (n = 0 to 7).
Page 43 CHAPTER 2 PIN FUNCTIONS (12) TO010 to TO015 (Timer output) … Output These pins output the pulse signal of timer 01. (13) ANI00 to ANI07, ANI10 to ANI17 (Analog input) … Input These are analog input pins to the A/D converter. (14) CKSEL (Clock generator operating mode select) …...
Page 44 CHAPTER 2 PIN FUNCTIONS (17) X1, X2 (Crystal) These pins connect a resonator for system clock generation. They also can input external clocks. For external clock input, connect to the X1 pin and leave the X2 pin open. (18) CV (Power supply for clock generator) This is the positive power supply pin for the clock generator.
Page 45: Types Of Pin I/O Circuit And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.4 Types of Pin I/O Circuit and Connection of Unused Pins Connection of a 1 to 10 kΩ resistor is recommended when connecting to V , CV , CV , or AV via a resistor. (1/2) I/O Circuit Type Recommended Connection P00/NMI...
Page 46 CHAPTER 2 PIN FUNCTIONS (2/2) I/O Circuit Type Recommended Connection PCM3/HLDRQ Input status: Independently connect to V or V via a resistor. Output status: Leave open. PCM4 PCT0/LWR PCT1/UWR PCT2 PCT3 PCT4/RD PCT5 PCT6/ASTB PCT7 PCS0/CS0 PCS1/CS1 PCS2/CS2 PCS3/CS3 PCS4/CS4 PCS5/CS5 PCS6/CS6 PCS7/CS7...
Page 47: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits Type 2 Type 5 Data P-ch IN/OUT Output N-ch disable Input Schmitt-triggered input with hysteresis characteristics enable Type 3 Type 5-AC Data P-ch IN/OUT P-ch Output N-ch disable N-ch Input enable Type 4 Type 7 Data P-ch...
Page 48: Chapter 3 Cpu Function
CHAPTER 3 CPU FUNCTION The CPU of the V850E/IA1 is based on RISC architecture and executes almost all instructions in one clock cycle, using 5-stage pipeline control. 3.1 Features • Minimum instruction execution time: 20 ns (@ internal 50 MHz operation) •...
Page 49: Cpu Register Set
CHAPTER 3 CPU FUNCTION 3.2 CPU Register Set The registers of the V850E/IA1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers are 32-bit width. For details, refer to V850E1 Architecture User’s Manual. (1) Program register set (2) System register set (Zero register)
Page 50: Program Register Set
CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable.
Page 51: System Register Set
CHAPTER 3 CPU FUNCTION 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. To read/write these system registers, specify a system register number indicated below using the system register load/store instruction (LDSR or STSR instruction). Table 3-2.
Page 52 CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)).
Page 53 CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for some instructions.
Page 54 CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of LDSR instruction execution.
Page 55 CHAPTER 3 CPU FUNCTION (2/2) Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Saturated Operation result status Flag status...
Page 56 CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW.
Page 57: Operation Modes
CHAPTER 3 CPU FUNCTION 3.3 Operation Modes 3.3.1 Operation modes The V850E/IA1 has the following operation modes. Mode specification is carried out by the MODE0 to MODE2 pins. (1) Normal operation mode (a) Single-chip modes 0, 1 Access to the internal ROM is enabled. In single-chip mode 0, after the system reset is cleared, each pin related to the bus interface enters the port mode, program execution branches to the reset entry address of the internal ROM, and instruction processing starts.
Page 58: Operation Mode Specification
CHAPTER 3 CPU FUNCTION 3.3.2 Operation mode specification The operation mode is specified according to the status of pins MODE0 to MODE2. In an application system fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins are changed during operation.
Page 59: Address Space
CHAPTER 3 CPU FUNCTION 3.4 Address Space 3.4.1 CPU address space The CPU of the V850E/IA1 is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a maximum of 64 MB of linear address space (program space) is supported.
Page 60: Image
CHAPTER 3 CPU FUNCTION 3.4.2 Image 16 images, each containing a 256 MB physical address space, are seen in the 4 GB CPU address space. In actuality, the same 256 MB physical address space is accessed regardless of the values of bits 31 to 28 of the CPU address.
Page 61: Wrap-Around Of Cpu Address Space
CHAPTER 3 CPU FUNCTION 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to 26 as a result of branch address calculation, the higher 6 bits ignore the carry or borrow.
Page 62: Memory Map
CHAPTER 3 CPU FUNCTION 3.4.4 Memory map The V850E/IA1 reserves areas as shown below. Each mode is specified by the MODE0 to MODE2 pins. Figure 3-3. Memory Map Single-chip mode 0 Single-chip mode 1 ROMless mode 0, 1 xFFFFFFFH On-chip peripheral On-chip peripheral On-chip peripheral 4 KB...
Page 63: Area
CHAPTER 3 CPU FUNCTION 3.4.5 Area (1) Internal ROM/internal flash memory area (a) Memory map Up to 1 MB of internal ROM/internal flash memory area is reserved. 256 KB are provided in the following addresses as physical internal ROM (mask ROM/flash memory). •...
Page 64 CHAPTER 3 CPU FUNCTION Table 3-3. Interrupt/Exception Table Start Address of Interrupt/Exception Start Address of Interrupt/Exception Interrupt/Exception Table Source Interrupt/Exception Table Source 00000000H RESET 00000200H INTP21/INTCC21 00000010H NMI0 00000210H INTP22/INTCC22 00000040H TRAP0n (n = 0 to F) 00000220H INTP23/INTCC23 00000050H TRAP1n (n = 0 to F) 00000230H INTP24/INTCC24...
Page 65 CHAPTER 3 CPU FUNCTION (c) Internal ROM area relocation function If set in single-chip mode 1, the internal ROM area is located beginning from address 100000H, so booting from external memory becomes possible. Therefore, in order to resume correct operation after reset, provide a handler address to the reset routine in address 0 of the external memory.
Page 66 CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB of memory, addresses FFFF000H to FFFFFFFH, is provided as an on-chip peripheral I/O area. An image of addresses FFFF000H to FFFFFFFH can be seen in the area between addresses 3FFF000H and Note 3FFFFFFH Note Access to the area of addresses 3FFF000H to 3FFFFFFH is prohibited.
Page 67: External Memory Expansion
CHAPTER 3 CPU FUNCTION (4) External memory area 256 MB are available for external memory area. The lower 64 MB can be used as program/data area and the higher 192 MB as data area. • When in single-chip mode 0: x0100000H to xFFFBFFFH •...
Page 68: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTION 3.4.7 Recommended use of address space The architecture of the V850E/IA1 requires that a register that serves as a pointer be secured for address generation when accessing operand data in the data space. Operand data access from instruction can be directly executed at the address in this pointer register ±32 KB.
Page 69 CHAPTER 3 CPU FUNCTION Figure 3-6. Recommended Memory Map Program space Data space FFFFFFFFH On-chip FFFFFA78H peripheral I/O FFFFFA77H FFFFF000H FFFFEFFFH Internal RAM FFFFE800H FFFFE7FFH xFFFFFFFH On-chip xFFFFA78H peripheral I/O FFFFC000H xFFFFA77H FFFFBFFFH xFFFF000H xFFFEFFFH Internal RAM xFFFE800H xFFFE7FFH xFFFC000H 04000000H xFFFBFFFH 03FFFFFFH...
Page 70: On-Chip Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.8 On-chip peripheral I/O registers (1/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF004H Port DL Undefined √ √ FFFFF004H Port DLL PDLL Undefined √ √...
Page 71 CHAPTER 3 CPU FUNCTION (2/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF094H DMA destination address register 2L DDA2L Undefined √ FFFFF096H DMA destination address register 2H DDA2H Undefined √...
Page 72 CHAPTER 3 CPU FUNCTION (3/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ √ FFFFF11AH Interrupt control register P0IC5 √ √ FFFFF11CH Interrupt control register P0IC6 √ √ FFFFF11EH Interrupt control register DETIC0 √...
Page 73 CHAPTER 3 CPU FUNCTION (4/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ √ FFFFF164H Interrupt control register CSIIC1 √ √ FFFFF166H Interrupt control register SRIC0 √ √ FFFFF168H Interrupt control register STIC0 √...
Page 74 CHAPTER 3 CPU FUNCTION (5/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF244H A/D voltage detection mode register 1 ADETM1 0000H √ √ FFFFF244H A/D voltage detection mode register 1L ADETM1L √...
Page 75 CHAPTER 3 CPU FUNCTION (6/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF572H Buffer register CM00 BFCM00 FFFFH √ FFFFF574H Buffer register CM01 BFCM01 FFFFH √ FFFFF576H Buffer register CM02 BFCM02 FFFFH √...
Page 76 CHAPTER 3 CPU FUNCTION (7/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ √ FFFFF5EFH Status register 0 STATUS0 √ √ FFFFF5F6H CC101 capture input selection register CSL10 √ √ FFFFF5F8H Timer 10 noise elimination time selection register NRC10 √...
Page 77 CHAPTER 3 CPU FUNCTION (8/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF646H Timer 2 time base control register 0 TCRE0 0000H √ √ FFFFF646H Timer 2 time base control register 0L TCRE0L √...
Page 78 CHAPTER 3 CPU FUNCTION (9/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF668H Timer 2 output delay register 0 ODELE0 0000H √ √ FFFFF668H Timer 2 output delay register 0L ODELE0L √...
Page 79 CHAPTER 3 CPU FUNCTION (10/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF906H Clocked serial interface read-only receive SIRBE0 0000H buffer register 0 √ √ FFFFF906H Clocked serial interface read-only receive SIRBEL0 buffer register L0 √...
Page 80 CHAPTER 3 CPU FUNCTION (11/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFFA07H Baud rate generator control register 0 BRGC0 √ FFFFFA20H 2-frame continuous reception buffer register 1 RXB1 Undefined √...
Page 81: Programmable Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.9 Programmable peripheral I/O registers In the V850E/IA1, the 16 KB area of x0000H to x3FFFH is provided as a programmable peripheral I/O area. In this area, the area between x2000H and x2FFFH is used exclusively for the FCAN controller. The internal bus of the V850E/IA1 becomes active when the on-chip peripheral I/O register area (FFFF000H to FFFFFFFH) or the programmable peripheral I/O register area (xxxxm000H to xxxxnFFFH) is accessed (m = xx00B, n = xx11B).
Page 82 CHAPTER 3 CPU FUNCTION (1) Peripheral area selection control register (BPC) This register can be read/written in 16-bit units. Address Initial value FFFFF064H 0000H PA15 PA13 PA12 PA11 PA10 PA09 PA08 PA07 PA06 PA05 PA04 PA03 PA02 PA01 PA00 Bit position Bit name Function PA15...
Page 83 CHAPTER 3 CPU FUNCTION (1/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn804H CAN message data length register 00 M_DLC00 Undefined √ xxxxn805H CAN message control register 00 M_CTRL00 Undefined √...
Page 84 CHAPTER 3 CPU FUNCTION (2/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn849H CAN message data register 021 M_DATA021 Undefined √ xxxxn84AH CAN message data register 022 M_DATA022 Undefined √...
Page 85 CHAPTER 3 CPU FUNCTION (3/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn88DH CAN message data register 045 M_DATA045 Undefined √ xxxxn88EH CAN message data register 046 M_DATA046 Undefined √...
Page 86 CHAPTER 3 CPU FUNCTION (4/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn8D2H CAN message ID register H06 M_IDH06 Undefined √ xxxxn8D4H CAN message configuration register 06 M_CONF06 Undefined √...
Page 87 CHAPTER 3 CPU FUNCTION (5/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn924H CAN message data length register 09 M_DLC09 Undefined √ xxxxn925H CAN message control register 09 M_CTRL09 Undefined √...
Page 88 CHAPTER 3 CPU FUNCTION (6/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn969H CAN message data register 111 M_DATA111 Undefined √ xxxxn96AH CAN message data register 112 M_DATA112 Undefined √...
Page 89 CHAPTER 3 CPU FUNCTION (7/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn9ADH CAN message data register 135 M_DATA135 Undefined √ xxxxn9AEH CAN message data register 136 M_DATA136 Undefined √...
Page 90 CHAPTER 3 CPU FUNCTION (8/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn9F2H CAN message ID register H15 M_IDH15 Undefined √ xxxxn9F4H CAN message configuration register 15 M_CONF15 Undefined √...
Page 91 CHAPTER 3 CPU FUNCTION (9/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnA44H CAN message data length register 18 M_DLC18 Undefined √ xxxxnA45H CAN message control register 18 M_CTRL18 Undefined √...
Page 92 CHAPTER 3 CPU FUNCTION (10/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnA89H CAN message data register 201 M_DATA201 Undefined √ xxxxnA8AH CAN message data register 202 M_DATA202 Undefined √...
Page 93 CHAPTER 3 CPU FUNCTION (11/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnACDH CAN message data register 225 M_DATA225 Undefined √ xxxxnACEH CAN message data register 226 M_DATA226 Undefined √...
Page 94 CHAPTER 3 CPU FUNCTION (12/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnB12H CAN message ID register H24 M_IDH24 Undefined √ xxxxnB14H CAN message configuration register 24 M_CONF24 Undefined √...
Page 95 CHAPTER 3 CPU FUNCTION (13/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnB64H CAN message data length register 27 M_DLC27 Undefined √ xxxxnB65H CAN message control register 27 M_CTRL27 Undefined √...
Page 96 CHAPTER 3 CPU FUNCTION (14/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnBA9H CAN message data register 291 M_DATA291 Undefined √ xxxxnBAAH CAN message data register 292 M_DATA292 Undefined √...
Page 97 CHAPTER 3 CPU FUNCTION (15/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnBEDH CAN message data register 315 M_DATA315 Undefined √ xxxxnBEEH CAN message data register 316 M_DATA316 Undefined √...
Page 98: Specific Registers
CHAPTER 3 CPU FUNCTION 3.4.10 Specific registers Specific registers are registers that are protected from being written with illegal data due to inadvertent program loop (runaway), etc. The V850E/IA1 has three specific registers, the power save control register (PSC) (refer to 8.5.2 (13) Power save control register (PSC)), clock control register (CKC) (refer to 8.3.4 Clock control register (CKC)), and flash programming mode control register (FLPMC) (refer to 16.7.12 Flash programming mode control register (FLPMC)).
Page 99 CHAPTER 3 CPU FUNCTION (2) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1>...
Page 100: Chapter 4 Bus Control Function
CHAPTER 4 BUS CONTROL FUNCTION The V850E/IA1 is provided with an external bus interface function by which external I/O and memories, such as ROM and RAM, can be connected. 4.1 Features • 16-bit/8-bit data bus sizing function • 8-space chip select function •...
Page 101: Memory Block Function
CHAPTER 4 BUS CONTROL FUNCTION 4.3 Memory Block Function The 256 MB memory space is divided into memory blocks of 2 MB and 64 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for each block. The area that can be used as program area is the 64 MB space of addresses 0000000H to 3FFFFFFH.
Page 102: Chip Select Control Function
CHAPTER 4 BUS CONTROL FUNCTION 4.3.1 Chip select control function Of the 256 MB memory area, the lower 8 MB (0000000H to 07FFFFFH) and the higher 8 MB (F800000H to FFFFFFFH) can be divided into 2 MB memory blocks by chip area selection control registers 0 and 1 (CSC0, CSC1) to control the chip select signal.
Page 103 CHAPTER 4 BUS CONTROL FUNCTION Address Initial value CSC0 CS33 CS32 CS31 CS30 CS23 CS22 CS21 CS20 CS13 CS12 CS11 CS10 CS03 CS02 CS01 CS00 FFFFF060H 2C11H Address Initial value CSC1 CS43 CS42 CS41 CS40 CS53 CS52 CS51 CS50 CS63 CS62 CS61 CS60...
Page 104 CHAPTER 4 BUS CONTROL FUNCTION The following diagram shows the CS signal, which is enabled for area 0 when the CSC0 register is set to 0703H. When the CSC0 register is set to 0703H, CS0 and CS2 are output to block 0 and block 1, but since CS0 has priority over CS2, CS0 is output if the addresses of block 0 and block 1 are accessed.
Page 105: Bus Cycle Type Control Function
CHAPTER 4 BUS CONTROL FUNCTION 4.4 Bus Cycle Type Control Function In the V850E/IA1, the following external devices can be connected directly to each memory block. • SRAM, external ROM, external I/O Connected external devices are specified by bus cycle type configuration registers 0, 1 (BCT0, BCT1). (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1) These registers can be read/written in 16-bit units.
Page 106: Bus Access
CHAPTER 4 BUS CONTROL FUNCTION 4.5 Bus Access 4.5.1 Number of access clocks The number of base clocks required to access each resource is shown below. Bus Cycle Status Instruction Fetch Operand Data Access Resource (Bus Width) Note 1 Internal ROM (32 bits) Note 2 Internal RAM (32 bits) −...
Page 107: Bus Sizing Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 Bus sizing function The bus sizing function controls the data bus width for each CS space. The data bus width is specified by using the bus size configuration register (BSC). (1) Bus size configuration register (BSC) This register can be read/written in 16-bit units.
Page 108: Bus Width
CHAPTER 4 BUS CONTROL FUNCTION 4.5.4 Bus width The V850E/IA1 accesses on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each type of access. Access all data in order starting from the lower side. (1) Byte access (8 bits) (a) When the data bus width is 16 bits (little endian) <1>...
Page 109 CHAPTER 4 BUS CONTROL FUNCTION (2) Halfword access (16 bits) (a) When the data bus width is 16 bits (little endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) 1st access 2nd access Address Address Address 2n + 1...
Page 110 CHAPTER 4 BUS CONTROL FUNCTION (3) Word access (32 bits) (a) When the data bus width is 16 bits (little endian) (1/2) <1> Access to address (4n) 1st access 2nd access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data...
Page 111 CHAPTER 4 BUS CONTROL FUNCTION (a) When the data bus width is 16 bits (little endian) (2/2) <3> Access to address (4n + 2) 1st access 2nd access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data...
Page 112 CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 8 bits (little endian) (1/2) <1> Access to address (4n) 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External...
Page 113 CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 8 bits (little endian) (2/2) <3> Access to address (4n + 2) 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data...
Page 114: Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6 Wait Function 4.6.1 Programmable wait function (1) Data wait control registers 0, 1 (DWC0, DWC1) To facilitate interfacing with low-speed memory or with I/Os, it is possible to insert up to 7 data wait states in the starting bus cycle for each CS space.
Page 115 CHAPTER 4 BUS CONTROL FUNCTION (2) Address wait control register (AWC) In the V850E/IA1, address setup wait and address hold wait states can be inserted before and after the T1 cycle, respectively. These wait states can be set for each CS space via the AWC register. This register can be read/written in 16-bit units.
Page 116: External Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, an arbitrary number of wait states can be inserted in the bus cycle by the external wait pin (WAIT) for synchronization with the external device. Just as with programmable waits, accessing internal ROM, internal RAM, and on-chip peripheral I/O areas cannot be controlled by external waits.
Page 117: Idle State Insertion Function
CHAPTER 4 BUS CONTROL FUNCTION 4.7 Idle State Insertion Function To facilitate interfacing with low-speed memory devices, a set number of idle states (TI) can be inserted into the starting bus cycle after the T3 state to secure the data output float delay time (t ) of the memory when each CS space is read accessed.
Page 118: Bus Hold Function
CHAPTER 4 BUS CONTROL FUNCTION 4.8 Bus Hold Function 4.8.1 Function outline If pins PCM2 and PCM3 are specified in the control mode, the HLDAK and HLDRQ functions become valid. If it is determined that the HLDRQ pin has become active (low level) as a bus mastership request from another bus master, the external address/data bus and each strobe pin are shifted to high impedance and then released (bus hold state).
Page 119: Operation In Power Save Mode
CHAPTER 4 BUS CONTROL FUNCTION 4.8.3 Operation in power save mode In the software STOP or IDLE mode, the internal system clock is stopped. Consequently, the bus hold state is not accepted and set since the HLDRQ pin cannot be accepted even if it becomes active. In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the bus hold state is set.
Page 120: Bus Priority Order
CHAPTER 4 BUS CONTROL FUNCTION 4.9 Bus Priority Order There are four external bus cycles: bus hold, DMA cycle, operand data access, and instruction fetch. In order of priority, bus hold is the highest, followed by DMA cycle, operand data access, and instruction fetch, in that order.
Page 121: Chapter 5 Memory Access Control Function
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1 SRAM, External ROM, External I/O Interface 5.1.1 Features • SRAM is accessed in a minimum of 2 states. • A maximum of 7 programmable data wait states can be inserted according to DWC0 and DWC1 register settings.
Page 122: Sram, External Rom, External I/O Access
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1.2 SRAM, external ROM, external I/O access Figure 5-1. SRAM, External ROM, External I/O Access Timing (1/5) (a) On a read (1 wait insertion) CLKOUT (Output) A16 to A23 (Output) Address AD0 to AD15 (I/O) Address Data ASTB (Output)
Page 123 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (2/5) (b) On a read (0 wait, address setup wait, address hold wait state insertion) TASW TAHW CLKOUT (Output) Address A16 to A23 (Output) AD0 to AD15 (I/O) Address Data ASTB (Output)
Page 124 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (3/5) (c) On a write (1 wait insertion) CLKOUT (Output) Address A16 to A23 (Output) Note Address Data AD0 to AD15 (I/O) ASTB (Output) RD (Output) UWR, LWR (Output) CSn (Output) WAIT (Input)
Page 125 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (4/5) (d) On a write (0 wait insertion, for 8-bit data bus) CLKOUT (Output) Address A16 to A23 (Output) Address AD8 to AD15 (I/O) Note Address Data AD0 to AD7 (I/O)
Page 126 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (5/5) (e) Bus hold timing CLKOUT (Output) HLDRQ (Input) HLDAK (Output) Note 1 Undefined Address A16 to A23 (Output) Note 2 Undefined Undefined Address AD0 to AD15 (I/O) ASTB (Output) RD (Output) UWR, LWR (Output)
Page 127: Chapter 6 Dma Functions (Dma Controller)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The V850E/IA1 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and peripheral I/O, among memories or among peripheral I/Os, based on DMA requests issued by the on-chip peripheral I/O (such as serial interface, timer/counter, and A/D converter), or software triggers (memory refers to internal RAM or external memory).
Page 128: Configuration
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.2 Configuration On-chip Internal RAM peripheral I/O Internal bus On-chip peripheral I/O bus DMA source address Data Address register (DSAnH/DSAnL) control control DMA destination address register (DDAnH/DDAnL) DMA transfer count Count register (DBCn) control DMA channel control register (DCHCn) DMA addressing control...
Page 129: Control Registers
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3 Control Registers 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) These registers are used to set the DMA source addresses (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DSAnH and DSAnL.
Page 130 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA source address registers 0L to 3L (DSA0L to DSA3L) These registers can be read/written in 16-bit units. Address Initial value DSA0L SA15 SA14 SA13 SA12 SA11 SA10 FFFFF080H Undefined DSA1L SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF088H Undefined DSA2L...
Page 131: Dma Destination Address Registers 0 To 3 (Dda0 To Dda3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) These registers are used to set the DMA destination address (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DDAnH and DDAnL.
Page 132 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA destination address registers 0L to 3L (DDA0L to DDA3L) These registers can be read/written in 16-bit units. Address Initial value DDA0L DA15 DA14 DA13 DA12 DA11 DA10 FFFFF084H Undefined DDA1L DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF08CH Undefined DDA2L...
Page 133: Dma Transfer Count Registers 0 To 3 (Dbc0 To Dbc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) These 16-bit registers are used to set the byte transfer counts for DMA channel n (n = 0 to 3). They store the remaining transfer counts during DMA transfer.
Page 134: Dma Addressing Control Registers 0 To 3 (Dadc0 To Dadc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) These 16-bit registers are used to control the DMA transfer modes for DMA channel n (n = 0 to 3). These registers cannot be accessed during DMA operation. These registers can be read/written in 16-bit units.
Page 135 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2/2) Bit position Bit name Function 7, 6 SAD1, Sets the count direction of the source address for DMA channel n (n = 0 to 3). SAD0 SAD1 SAD0 Count direction Increment Decrement Fixed Setting prohibited 5, 4 DAD1,...
Page 136: Dma Channel Control Registers 0 To 3 (Dchc0 To Dchc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n (n = 0 to 3). These registers can be read/written in 8-bit or 1-bit units. (However, bit 7 is read only and bits 2 and 1 are write only.
Page 137 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) <7> <3> <2> <1> <0> Address Initial value DCHC0 MLE0 INIT0 STG0 FFFFF0E0H DCHC1 MLE1 INIT1 STG1 FFFFF0E2H DCHC2 MLE2 INIT2 STG2 FFFFF0E4H DCHC3 MLE3 INIT3 STG3 FFFFF0E6H Bit position Bit name Function This status bit indicates whether DMA transfer through DMA channel n has ended or not. This bit is read-only.
Page 138: Dma Disable Status Register (Ddis)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.6 DMA disable status register (DDIS) This register holds the contents of the Enn bit of the DCHCn register during forcible interruption by NMI input (n = 0 to 3). This register is read-only, in 8-bit units. Be sure to set bits 4 to 7 to 0.
Page 139: Dma Trigger Factor Registers 0 To 3 (Dtfr0 To Dtfr3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) These 8-bit registers are used to control the DMA transfer start trigger through interrupt requests from on-chip peripheral I/O. The interrupt requests set with these registers serve as DMA transfer start factors. These registers can be read/written in 8-bit units.
Page 140 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2/2) Bit position Bit name Function 5 to 0 IFCn5 to IFCn0 IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt source INTP5 INTP6 INTDET0 INTDET1 INTTM00 INTCM003 INTTM01 INTCM013 INTP100/INTCC100 INTP101/INTCC101 INTCM100 INTCM101 INTP110/INTCC110 INTP111/INTCC111 INTCM110 INTCM111 INTTM20...
Page 141 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The relationship between the interrupt source and the DMA transfer trigger is as follows (n = 0 to 3). Interrupt source Internal DMA request signal IFCn0 to IFCn5 Caution An interrupt request will be generated when DMA transfer starts. To prevent an interrupt from being generated, mask the interrupt by setting the interrupt request control register.
Page 142: Transfer Mode
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4 Transfer Mode 6.4.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 143 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-3 shows a single transfer mode example in which a lower priority DMA transfer request is generated within one clock after the end of a single transfer. DMA channels 0 and 3 are used for a single transfer. When two DMA transfer request signals are activated at the same time, the two DMA transfers are performed alternately.
Page 144: Single-Step Transfer Mode
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4.2 Single-step transfer mode In single-step transfer mode, the DMAC releases the bus at each byte/halfword transfer. Once a DMA transfer request signal is received, transfer is performed again. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 145: Block Transfer Mode
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4.3 Block transfer mode In the block transfer mode, once transfer starts, the DMAC continues the transfer operation without releasing the bus until a terminal count occurs. No other DMA requests are acknowledged during block transfer. After the block transfer ends and the DMAC releases the bus, another DMA transfer can be acknowledged.
Page 146: Transfer Target
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6 Transfer Target 6.6.1 Transfer type and transfer target Table 6-1 shows the relationship between the transfer type and transfer target (√: transfer enabled, ×: transfer disabled). Table 6-1. Relationship Between Transfer Type and Transfer Target Destination Internal ROM On-Chip...
Page 147: External Bus Cycles During Dma Transfer (Two-Cycle Transfer)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6.2 External bus cycles during DMA transfer (two-cycle transfer) The external bus cycles during DMA transfer (two-cycle transfer) are shown below. Table 6-2. External Bus Cycles During DMA Transfer (Two-Cycle Transfer) Transfer Target External Bus Cycle On-chip peripheral I/O, internal RAM None –...
Page 148 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-8 shows the configuration of the buffer register. Figure 6-8. Buffer Register Configuration Data read Address/ Data write Master Slave count register register controller The actual DMA transfer is performed based on the settings of the slave register. The settings incorporated in the master and slave registers differ as follows according to the timing (time) at which the settings were made.
Page 149: Dma Transfer Start Factors
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. Cautions 1. Do not use two or more start factors ((1) and (2)) in combination for the same channel (if two or more start factors are generated at the same time, only one of them is valid, but the valid start factor cannot be identified).
Page 150: Forcible Interruption
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.10 Forcible Interruption DMA transfer can be forcibly interrupted by NMI input during DMA transfer. At such a time, the DMAC clears the Enn bit of the DCHCn register of all channels to 0 and the DMA transfer disabled state is entered.
Page 151: Forcible Termination
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.12 Forcible Termination In addition to the forcible interruption operation by means of NMI input, DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register (n = 0 to 3). An example of forcible termination by the INITn bit of the DCHCn register is illustrated below (n = 0 to 3).
Page 152: Restriction Related To Dma Transfer Forcible Termination
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.12.1 Restriction related to DMA transfer forcible termination When terminating a DMA transfer by setting the INITn bit of the DCHCn register, the transfer may not be terminated, but just suspended, even though the INITn bit is set to 1. As a result, when the DMA transfer of a channel that should have been terminated is resumed, the DMA transfer will terminate after an unexpected number of transfers are completed and a DMA transfer completion interrupt may occur.
Page 153: Times Related To Dma Transfer
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) Repeat setting the INITn bit of the DCHCn register until forcible termination of DMA transfer is completed normally The procedure is shown below. <1> Copy the initial transfer count of the channel to be forcibly terminated to a general-purpose register. <2>...
Page 154: Precautions
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.14 Precautions (1) Memory boundary The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA targets (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer. (2) Transfer of misaligned data DMA transfer of 16-bit bus width misaligned data is not supported.
Page 155: Interrupt Factors
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (7) Read values of DSAn and DDAn registers If the values of the DSAn and DDAn registers are read during DMA transfer, the values in the middle of being updated may be read (n = 0 to 3). For example, if the DSAnH register and the DSAnL register are read in that order when the value of the DMA transfer source address (DSAn register) is “0000FFFFH”...
Page 156: Chapter 7 Interrupt/Exception Processing Function
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850E/IA1 is provided with an interrupt controller (INTC) that can process a total of 53 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 157 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt/Exception Source List (1/2) Type Classification Interrupt/Exception Source Default Exception Handler Restored PC Priority Code Address Name Controlling Generating Source Generating Register Unit − − Reset Interrupt RESET RESET input 0000H 00000000H Undefined −...
Page 158 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt/Exception Source List (2/2) Type Classification Interrupt/Exception Source Default Exception Handler Restored PC Priority Code Address Name Controlling Generating Source Generating Register Unit Maskable Interrupt INTP30/ CC3IC0 INTP30 pin/CC30 match Pin/TM3 0260H 00000260H nextPC INTCC30 Interrupt INTP31/...
Page 159 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Remarks 1. Default priority: The priority order when two or more maskable interrupt requests are generated at the same time. The highest priority is 0. Restored PC: The value of the program counter (PC) saved to EIPC, FEPC, or DBPC of CPU when interrupt servicing is started.
Page 160: Non-Maskable Interrupt
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2 Non-Maskable Interrupt A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupts. A non-maskable interrupt request is input from the NMI pin.
Page 161: Operation
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.1 Operation If a non-maskable interrupt is generated by NMI input, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception code 0010H to the higher halfword (FECC) of ECR.
Page 162 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-2. Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service program is being executed Main routine (PSW.NP = 1) NMI request held pending regardless NMI request NMI request of the value of the NP bit of the PSW Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service program is being executed...
Page 163: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.2 Restore Execution is restored from the non-maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of the PC and the PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW is 1.
Page 164: Non-Maskable Interrupt Status Flag (Np)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 165: Maskable Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850E/IA1 has 52 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 166 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-4. Servicing Configuration of Maskable Interrupt INT input INTC acknowledged xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 167: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0.
Page 168: Priorities Of Maskable Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.3 Priorities of maskable interrupts The V850E/IA1 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 169 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Servicing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the (level 3) (level 2) priority of b is higher than that of a and interrupts are...
Page 170 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Servicing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 171 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Servicing Interrupt Requests Generated Simultaneously Main routine Interrupt request a (level 2) Interrupt request b (level 1) Servicing of interrupt request b Interrupt requests b and c are Interrupt request c (level 1) acknowledged first according to their priorities.
Page 172: Interrupt Control Register (Xxicn)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read/written in 8-bit or 1-bit units. Caution Read the xxIFn bit of the xxICn register in the interrupt disabled (DI) state.
Page 173 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (1/2) Address Register <7> <6> <2> <1> <0> FFFFF110H P0IC0 P0IF0 P0MK0 P0PR02 P0PR01 P0PR00 FFFFF112H P0IC1 P0IF1 P0MK1 P0PR12 P0PR11 P0PR10 FFFFF114H P0IC2 P0IF2 P0MK2 P0PR22 P0PR21 P0PR20...
Page 174 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (2/2) Address Register <7> <6> <2> <1> <0> FFFFF164H CSIIC1 CSIIF1 CSIMK1 CSIPR12 CSIPR11 CSIPR10 FFFFF166H SRIC0 SRIF0 SRMK0 SRPR02 SRPR01 SRPR00 FFFFF168H STIC0 STIF0 STMK0 STPR02 STPR01 STPR00...
Page 175: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR3 registers is equivalent to the xxMKn bit of the xxICn register. IMRm can be read/written in 16-bit units (m = 0 to 3).
Page 176: In-Service Priority Register (Ispr)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 177: Maskable Interrupt Status Flag (Id)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.7 Maskable interrupt status flag (ID) The ID flag is bit 5 of the PSW and this controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt requests. Initial value 00000020H Bit position Bit name...
Page 178 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt mode registers 1, 2 (INTM1, INTM2) These registers specify the valid edge for external interrupt requests (INTP0 to INTP6), input via external pins. The correspondence between each register and the external interrupt requests that register controls is shown below.
Page 179 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Signal edge selection registers 10, 11 (SESA10, SESA11) These registers specify the valid edge of external interrupt requests (INTP100, INTP101, INTP110, INTP111, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, and TCLR11), input via external pins. The correspondence between each register and the external interrupt requests that register controls is shown below.
Page 180 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1/2) Address Initial value SESA10 TESUD01 TESUD00 CESUD01 CESUD00 IES1011 IES1010 IES1001 IES1000 FFFFF5EDH TIUD10, TCUD10 TCLR10 INTP101 INTP100 Address Initial value SESA11 TESUD11 TESUD10 CESUD11 CESUD10 IES1111 IES1110 IES1101 IES1100 FFFFF60DH TIUD11, TCUD11 TCLR11 INTP111 INTP110 Bit position...
Page 181 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2/2) Bit position Bit name Function 3, 2 IES1n11, Specifies the valid edge of the pin selected using the CSLn bit of the CSL1n register IES1n10 (INTP1n1, INTP1n0). IES1n11 IES1n10 Valid edge Falling edge Rising edge Setting prohibited Both rising and falling edges 1, 0...
Page 182 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) Valid edge selection register (SESC) This register specifies the valid edge for external interrupt requests (INTP30, INTP31, TCLR3, and TI3), input via external pins. The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and falling edges).
Page 183 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (4) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5) These registers specify the valid edge for external interrupt requests input to timer 2 (INTP20 to INTP25). The correspondence between each register and the external interrupt request that register controls is shown below.
Page 184 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1/2) Address Initial value FEM0 DFEN00 EDGE010 EDGE000 TMS010 TMS000 FFFFF630H INTP20 Address Initial value FEM1 DFEN01 EDGE011 EDGE001 TMS011 TMS001 FFFFF631H INTP21 Address Initial value FEM2 DFEN02 EDGE012 EDGE002 TMS012 TMS002 FFFFF632H INTP22 Address Initial value FEM3 DFEN03...
Page 185 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2/2) Bit position Bit name Function Note 1, 0 TMS01n, Selects the capture input TMS00n TMS01n TMS00n Operation Used as a pin Digital filter (noise eliminator specification) Timer-based capture to sub-channel 1 Timer-based capture to sub-channel 2 Note Selection of capture input based on INTCM100 and INTCM101 is valid only for the FEM1 and FEM2 registers.
Page 186: Software Exception
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 7.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.
Page 187: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. (1) Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. (2) Transfers control to the address of the restored PC and PSW.
Page 188: Exception Status Flag (Ep)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.3 Exception status flag (EP) The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Initial value 00000020H Bit position Bit name...
Page 189: Exception Trap
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5 Exception Trap An exception trap is an interrupt that is requested when an illegal execution of an instruction takes place. In the V850E/IA1, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 7.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B.
Page 190 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-10. Exception Trap Processing Exception trap (ILGOP) occurs DBPC restored PC DBPSW PSW.NP PSW.EP CPU processing PSW.ID 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 191: Debug Trap
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. (1) Operation (1) Saves the restored PC to DBPC.
Page 192 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Restoration from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW.
Page 193: Multiple Interrupt Servicing Control
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.6 Multiple Interrupt Servicing Control Multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can be interrupted during servicing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is acknowledged and serviced first.
Page 194: Interrupt Response Time
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Generation of exception in service program Service program of maskable interrupt or exception • EIPC saved to memory or register • EIPSW saved to memory or register • TRAP instruction ← Exception such as TRAP instruction acknowledged. •...
Page 195 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-14. Pipeline Operation at Interrupt Request Acknowledgement (Outline) 4 system clocks Internal clock Interrupt request Instruction 1 Instruction 2 Interrupt acknowledgment operation INT1 INT2 INT3 INT4 Instruction (start instruction of interrupt servicing routine) Interleave Note access Note For details of interleave access, refer to 8.1.2 2-clock branch in V850E1 Architecture User’s Manual...
Page 196: Periods In Which Cpu Does Not Acknowledge Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.8 Periods in Which CPU Does Not Acknowledge Interrupts The CPU acknowledges an interrupt while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sampling instruction and the next instruction (interrupt is held pending).
Page 197: Chapter 8 Clock Generation Function
CHAPTER 8 CLOCK GENERATION FUNCTION The clock generator (CG) generates and controls the internal system clock (f ) that is supplied to each internal unit, such as the CPU. 8.1 Features • Multiplier function using a phase locked loop (PLL) synthesizer •...
Page 198: Input Clock Selection
CHAPTER 8 CLOCK GENERATION FUNCTION 8.3 Input Clock Selection The clock generator consists of an oscillator and a PLL synthesizer. For example, connecting a 5.0 MHz crystal resonator or ceramic resonator to pins X1 and X2 enables a 50 MHz internal system clock (f ) to be generated when the multiplier is 10.
Page 199: Peripheral Command Register (Phcmd)
CHAPTER 8 CLOCK GENERATION FUNCTION (4 to 5 MHz) value for which 10 × f Caution When using the PLL mode, only an f does not exceed the system clock maximum frequency (50 MHz) can be used for the oscillation frequency or external clock frequency.
Page 200: Clock Control Register (Ckc)
CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.4 Clock control register (CKC) The clock control register is an 8-bit register that controls the internal system clock (f ) in PLL mode. It can be written to only by a specific sequence combination so that it cannot easily be overwritten by mistake due to erroneous program execution.
Page 201 CHAPTER 8 CLOCK GENERATION FUNCTION Data is set in the clock control register (CKC) according to the following sequence. <1> Disable interrupts (set the NP bit of PSW to 1). <2> Prepare data in any one of the general-purpose registers to set in the specific register. <3>...
Page 202: Peripheral Status Register (Phs)
CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.5 Peripheral status register (PHS) If a write operation is not performed in the correct sequence including access to the command register for the protection-targeted internal registers, writing is not performed and a protection error is generated, setting the status flag (PRERR) to 1.
Page 203: Pll Lockup
CHAPTER 8 CLOCK GENERATION FUNCTION 8.4 PLL Lockup The lockup time (frequency stabilization time) is the time from when the power is turned on or the software STOP mode is released until the phase locks at the prescribed frequency. The state until this stabilization occurs is called a lockup state, and the stabilized state is called a lock state.
Page 204: Power Save Control
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5 Power Save Control 8.5.1 Overview The power save function has the following three modes. (1) HALT mode In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU’s operation clock stops. Since the supply of clocks to on-chip peripheral functions other than the CPU continues, operation continues.
Page 205 CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-1 shows the operation of the clock generator in normal operation mode, HALT mode, IDLE mode, and software STOP mode. An effective low power consumption system can be realized by combining these modes and switching modes according to the required use.
Page 206 CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-1. Clock Generator Operation Using Power Save Control Clock Clock Clock Source Power Save Mode Oscillator Synthesizer Supply to Supply Peripheral to CPU √ √ √ √ PLL mode Oscillation with Normal operation resonator √...
Page 207: Control Registers
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.2 Control registers (1) Power save mode register (PSMR) This is an 8-bit register that controls power save mode. It is effective only when the STB bit of the PSC register is set to 1. Writing to the PSMR register is executed by the store instruction (ST/SST instruction) and a bit manipulation instruction (SET1/CLR1/NOT1 instruction).
Page 208 CHAPTER 8 CLOCK GENERATION FUNCTION (3) Power save control register (PSC) This is an 8-bit register that controls the power save function. If releasing of interrupts are enabled by the setting of the NMIM and INTM bits, the software STOP mode can be released by an interrupt request (except when interrupt servicing is disabled by the interrupt mask registers (IMR0 to IMR3)).
Page 209 CHAPTER 8 CLOCK GENERATION FUNCTION [Sample coding] <1> ST.B r11, PSMR [r0] ; Set PSMR register <2> MOV 0x07, r10 ; Prepare data for setting specific register in arbitrary general-purpose register <3> ST.B r10, PRCMD [r0] ; Write PRCMD register <4>...
Page 210: Halt Mode
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.3 HALT mode (1) Setting and operation status In HALT mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the operation clock of the CPU is stopped. Since the supply of clocks to on-chip peripheral I/O units other than the CPU continues, operation continues.
Page 211 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of HALT mode HALT mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (INTPn), or RESET pin input (n = 0 to 6, 20 to 25, 30, 31, 100, 101, 110, 111). (a) Release by a non-maskable interrupt request or an unmasked maskable interrupt request HALT mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request regardless of the priority.
Page 212: Idle Mode
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.4 IDLE mode (1) Setting and operation status In IDLE mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the supply of internal system clocks is stopped which causes the overall system to stop. When IDLE mode is released, the system can be switched to normal operation mode quickly because the oscillator’s oscillation stabilization time or the PLL lockup time need not be secured.
Page 213 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of IDLE mode IDLE mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request Note (INTPn) , or RESET pin input (n = 0 to 6, 20 to 25). Note When a digital filter using clock sampling is selected as the noise eliminator for INTP20 to INTP25, the IDLE mode cannot be released.
Page 214: Software Stop Mode
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.5 Software STOP mode (1) Setting and operation status In software STOP mode, the clock generator (oscillator and PLL synthesizer) is stopped. The overall system is stopped, and ultra-low power consumption is achieved in which only leak current is lost. The system is switched to software STOP mode by using a store instruction (ST or SST instruction) or bit manipulation instruction (SET1, CLR1, or NOT1 instruction) to set the PSC and PSMR registers (see 8.5.2 Control registers).
Page 215 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of software STOP mode Software STOP mode is released by a non-maskable interrupt request, an unmasked maskable interrupt Note request (INTPn) , or RESET pin input. Also, to release software STOP mode when PLL mode (CKSEL pin = low level) and resonator connection mode (CESEL bit of CKC register = 0) are used, the oscillator’s oscillation stabilization time must be secured (n = 0 to 6, 20 to 25).
Page 216: Securing Oscillation Stabilization Time
CHAPTER 8 CLOCK GENERATION FUNCTION 8.6 Securing Oscillation Stabilization Time 8.6.1 Oscillation stabilization time security specification Two specification methods can be used to secure the time from when software STOP mode is released until the stopped oscillator stabilizes. (1) Securing the time using an on-chip time base counter Software STOP mode is released when a valid edge is input to the NMI pin or a maskable interrupt request is input (INTPn).
Page 217: Time Base Counter (Tbc)
CHAPTER 8 CLOCK GENERATION FUNCTION (2) Securing the time according to the signal level width (RESET pin input) Software STOP mode is released due to falling edge input to the RESET pin. The time until the clock output from the oscillator stabilizes is secured according to the low level width of the signal that is input to the pin.
Page 218: Chapter 9 Timer/Counter Function
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1 Timer 0 9.1.1 Features (timer 0) Timers 00, 01 (TM00, TM01) are 16-bit timer/counters that are ideal for controlling high-speed inverters such as motors. • 3-phase PWM output function PWM mode 0 (symmetric triangular wave) PWM mode 1 (asymmetric triangular wave) PWM mode 2 (sawtooth wave) •...
Page 219: Function Overview (Timer 0)
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.2 Function overview (timer 0) • 16-bit timer (TM0n) for 3-phase PWM inverter control: 2 channels • Compare registers: 4 registers × 2 channels • 12-bit dead-time timers (DTMn0 to DTMn2): 3 timers × 2 channels •...
Page 220: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.3 Basic configuration The basic configuration is shown below. Figure 9-1. Block Diagram of Timer 0 (Mode 0: Symmetric Triangular Wave, Mode 1: Asymmetric Triangular Wave) BFCMn3 INTCM0n3 CM0n3 INTTM0n TM0n Output control by external input (ESOn), 1/16 TM0n timer operation 1/32...
Page 221 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-2. Block Diagram of Timer 0 (Mode 2: Sawtooth Wave) BFCMn3 INTCM0n3 CM0n3 Clear Output control by TM0n external input (ESOn), TM0n timer operation 1/16 1/32 ALVTO DTRRn BFCMn0 CM0n0 Underflow DTMn0 TO0n0 (U phase) TO0n1 (U phase) BFCMn1...
Page 222 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timers 00, 01 (TM00, TM01) TM0n operates as a 16-bit up/down timer or up timer. The cycle is controlled by compare register 0n3 (CM0n3) (n = 0, 1). TM0n start/stop is controlled by the TM0CEn bit of timer control register 0n (TMC0n). Division by the prescaler can be selected for the count clock from among f /2, f /4, f...
Page 223 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Dead-time timers 00 to 02, 10 to 12 (DTM00 to DTM02, DTM10 to DTM12) DTMn0 to DTMn2 are dedicated 12-bit down timers that generate dead time suitable for inverter control application. DTMn0 to DTMn2 operate as one-shot timers. Counting by a dead-time timer is enabled or disabled by the TM0CEDn bit of timer control register 0n (TMC0n) and cannot be controlled by software.
Page 224 CHAPTER 9 TIMER/COUNTER FUNCTION (5) Compare registers 003, 013 (CM003, CM013) CM0n3 is a 16-bit register that always compare its value with the value of TM0n. If the values match, CM0n3 outputs an interrupt signal (INTCM0n3). CM0n3 controls the maximum count value of TM0n, and if the values match, it performs the following operations at the next timer count clock.
Page 225 CHAPTER 9 TIMER/COUNTER FUNCTION (7) Buffer registers CM03, CM13 (BFCM03, BFCM13) BFCMn3 is a 16-bit register that transfers data to the compare register at any timing. Transfer enable or disable is controlled by the BFTE3 bit of the TMC0n register. BFCMn3 can be read/written in 16-bit units.
Page 226: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.4 Control registers (1) Timer 0 clock selection register (PRM01) The PRM01 register is used to select the base clock (f ) of timer 0 (TM0n). It can be read/written in 8-bit or 1-bit units. Caution Always set this register before using the timer. Address Initial value PRM01...
Page 227 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Timer control registers 00, 01 (TMC00, TMC01) TMC0n register is a 16-bit register that sets the operation of timer 0 (TM0n). The TMC0n register can be read/written in 16-bit units. If the higher 8 bits of the TMC0n register are used as the TMC0nH register and the lower 8 bits as the TMC0nL register, the register can be read/written in 8-bit or 1-bit units.
Page 228 CHAPTER 9 TIMER/COUNTER FUNCTION (2/4) Bit position Bit name Function 13 to 11 CUL02 to CUL00 Cautions 1. INTTM0n and INTCM0n3 interrupts can be culled with the same culling ratio (1/1, 1/2, 1/4, 1/8, 1/16). 2. Even when BFTE3 bit = 1, BFTEN bit = 1 (settings to transfer data from BFCMn0 to BFCMn3 registers to CM0n0 to CM0n3 registers), transfer is not performed with the generation timing of culled INTTM0n and INTCM0n3 interrupts if the MBFTE bit = 0.
Page 229 CHAPTER 9 TIMER/COUNTER FUNCTION (3/4) Bit position Bit name Function BFTE3 Specifies transfer of data from BFCMn3 register to CM0n3 register. 0: Transfer disabled 1: Transfer enabled The transfer timing from the BFCMn3 register to the CM0n3 register is as follows. BFCMn3 →...
Page 230 CHAPTER 9 TIMER/COUNTER FUNCTION (4/4) Bit position Bit name Function 1, 0 MOD01, Specifies the operation mode of TM0n. MOD00 BFCMn3 → Operation mode TM0n Timer clear BFCMn0 to BFCMn2 → operation source CM0n3 timing CM0n0 to CM0n2 timing − Up/down INTTM0n INTTM0n...
Page 231 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-5. Interrupt Culling Processing (a) PWM mode 0 (symmetric triangular wave) CM0n3 TM0n count value 0000H Interrupt request INTTM0n INTTM0n INTTM0n INTTM0n occurrence occurrence occurrence occurrence CUL02 to CUL00 Interrupt culling Interrupt culling 1/1 cycle 1/2 cycle Remark n = 0, 1...
Page 232 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-6. Interrupt Culling Ratio Change Timing (Relationship Between STINTn Bit Setting and CUL Bit Change): PWM Mode 1 (Asymmetric Triangular Wave) TM0CEn bit CM0n3 TM0n count value 0000H INTTM0n INTTM0n INTTM0n INTTM0n INTTM0n INTTM0n INTTM0n INTTM0n STINTn = 1 INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3...
Page 233 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer unit control registers 00, 01 (TUC00, TUC01) TUC0n register is an 8-bit register that controls TO0n0 to TO0n5 outputs. TUC0n can be read/written in 8-bit or 1-bit units. However, bit 0 is read-only. <1> <0>...
Page 234 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Timer output mode registers 0, 1 (TOMR0, TOMR1) The TOMRn register controls timer output from the TO0n0 to TO0n5 pins. To prevent abnormal output from pins TO0n0 to TO0n5 due to illegal access, data write to the TOMRn register consists of the following two sequences.
Page 235 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function ALVVB Specifies the output level of the TO0n3 pin. 0: Inverted level of active level set by ALVTO bit 1: Active level set by ALVTO bit When the ALVVB bit = 1, the output level of the TO0n3 output is the same as TO0n2.
Page 236 CHAPTER 9 TIMER/COUNTER FUNCTION Examples of the output waveforms of TO000 and TO001 when the higher 4 bits (ALVTO, ALVUB, ALVVB, and ALVWB) of the TOMRn register are set in PWM mode 0 (symmetric triangular waves) are shown below. Figure 9-7. Output Waveforms of TO000 and TO001 in PWM Mode 0 (Symmetric Triangular Waves) (Without Dead Time (TM0CED0 Bit = 1)) (a) TOMR0 register value = 80H TM00 = CM000...
Page 237 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-8. Output Waveforms of TO000 and TO001 in PWM Mode 0 (Symmetric Triangular Waves) (With Dead Time (TM0CED0 Bit = 0)) (a) TOMR0 register value = 80H TM00 = CM000 TM00 = CM000 TO000 TO001 Dead time period Dead time period (b) TOMR0 register value = 00H...
Page 238 CHAPTER 9 TIMER/COUNTER FUNCTION Data setting to timer output mode registers 0, 1 (TOMR0, TOMR1) is done in the following sequence. <1> Prepare the data to be set to timer output mode registers 0, 1 (TOMR0, TOMR1) in a general-purpose register.
Page 239 CHAPTER 9 TIMER/COUNTER FUNCTION (5) PWM output enable registers 0, 1 (POER0, POER1) The POERn register is used to make the external pulse output (TO0n0 to TO0n5) status inactive by software. POERn can be read/written in 8-bit or 1-bit units. <5>...
Page 240 CHAPTER 9 TIMER/COUNTER FUNCTION (6) PWM software timing output registers 0, 1 (PSTO0, PSTO1) The PSTOn register is used to perform settings to output the desired waveforms to the external pulse output pins (TO0n0 to TO0n5) by software. PSTOn can be read/written in 8-bit or 1-bit units. Cautions 1.
Page 241 CHAPTER 9 TIMER/COUNTER FUNCTION (1/2) <7> <2> <1> <0> Address Initial value PSTO0 TORTO0 UPORT0 VPORT0 WPORT0 FFFFF57EH <7> <2> <1> <0> Address Initial value PSTO1 TORTO1 UPORT1 VPORT1 WPORT1 FFFFF5BEH Bit position Bit name Function TORTOn Specifies TO0n0 to TO0n5 output control. 0: Timer output 1: Software output The change of the TO0n0 to TO0n5 signals during software output occurs when the...
Page 242 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function WPORTn Specifies the TO0n4 (W phase)/TO0n5 (W phase) pin output value. WPORTn Operation TO0n4 Inverted level of ALVTO bit setting TO0n5 When ALVWB = 0 Level of ALVTO bit setting When ALVWB = 1 Inverted level of ALVTO bit setting TO0n4...
Page 243 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-9. When UPORTn = 1 Is Set Immediately Before TORTOn = 0 (Switched by Active Value) CM0n3 CM0n3 CM0n3 CM0n3 TM0n Count value 0000H Note 1 Note 2 Note 2 Note 1 Note 2 Note 3 Note 4 INTCM0n3 INTTM0n...
Page 244 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-10. When UPORTn = 0 Is Set Immediately Before TORTOn = 0 (Switched by Inactive Value) CM0n3 CM0n3 CM0n3 CM0n3 TM0n Count value 0000H Note 2 Note 3 Note 1 Note 1 Note 2 Note 4 INTCM0n3 INTTM0n TO0n0...
Page 245 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-11. When UPORTn = 0 Is Set Immediately Before TORTOn = 1 CM0n3 CM0n3 CM0n3 CM0n3 TM0n Count value 0000H Note 2 Note 1 Note 1 Note 2 Note 1 Note 3 INTCM0n3 Note 4 INTTM0n TO0n0 TM0CEn...
Page 246 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-12. Software Output Waveforms of TO000 and TO001 (Without Dead Time (TM0CED0 = 1)) (a) TOMR0 register value = 80H UPORT0 ← 1 UPORT0 ← 0 TO000 TO001 (b) TOMR0 register value = 00H UPORT0 ← 1 UPORT0 ←...
Page 247 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-13. Software Output Waveforms of TO000 and TO001 (With Dead Time (TM0CED0 = 0)) (a) TOMR0 register value = 80H UPORT0 ← 1 UPORT0 ← 0 TO000 TO001 Dead-time period Dead-time period (b) TOMR0 register value = 00H UPORT0 ←...
Page 248 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-14. Software Output Waveforms of TO000 and TO001 When “1” Is Written to UPORT0 Bit While TORTO0 = 1 (When TOMR0 Register Value = 80H) (a) Without dead time (TM0CED0 = 1) UPORT0 ← 1 UPORT0 ←...
Page 249 CHAPTER 9 TIMER/COUNTER FUNCTION (7) TOMR write enable registers 0, 1 (SPEC0, SPEC1) The SPECn register enables write to the TOMRn register. Unless write to the TOMRn register is performed following immediately after write to the SPECn register (any data can be written), write processing to the TOMRn register is not performed normally.
Page 250: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.5 Operation Remarks 1. In the description of the operation in 9.1.5, it is assumed that each bit that affects the output of TO0n0 to TO0n5 is set as follows. ALVTO = 1, ALVUB = 0, ALVVB = 0, ALVWB = 0, TORTOn = 0 2.
Page 251 CHAPTER 9 TIMER/COUNTER FUNCTION (2) PWM mode 0: Triangular wave modulation (right-left symmetric waveform control) [Setting procedure] (a) Set PWM mode 0 (symmetric triangular wave) with bits MOD01 and MOD00 of the TMC0n register. Also set the active level of pins TO0n0 to TO0n5 with the ALVTO bit of the TOMRn register (n = 0, 1). (b) Set the count clock of TM0n with bits PRM02 to PRM00 of the TMC0n register.
Page 252 CHAPTER 9 TIMER/COUNTER FUNCTION [Operation] In PWM mode 0, TM0n performs up/down count operation. When TM0n = 0000H during down counting, an underflow interrupt (INTTM0n) is generated, and when TM0n = CM0n3 during up counting, a match interrupt (INTCM0n3) is generated (n = 0, 1). Switching from up counting to down counting is performed when TM0n and CM0n3 match (INTCM0n3), and switching from down counting to up counting is performed when TM0n underflow occurs after TM0n becomes 0000H.
Page 253 CHAPTER 9 TIMER/COUNTER FUNCTION [Output waveform width in respect to set value] • PWM cycle = BFCMn3 × 2 × T TM0n • Dead-time width = (DTRRn + 1)/f • Active width of positive phase (TO0n0, TO0n2, TO0n4 pins) = { (CM0n3 − CM0nX ) + (CM0n3 −...
Page 254 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-15. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave) CM0n3 (d) CM0n3 (e) TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match match BFCMnx CM0nx BFCMn3 CM0n3 Interrupt request INTCM0n3 INTTM0n INTCM0n3 INTTM0n DTMnx Positive phase...
Page 255 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-16. Overall Operation Image of PWM Mode 0 (Symmetric Triangular Wave) CM0n3 CM0n3 CM0n2 CM0n2 CM0n2 CM0n2 CM0n1 CM0n1 CM0n1 CM0n1 TM0n count value CM0n0 CM0n0 CM0n0 CM0n0 0000H TO0n0 output TO0n1 output TO0n2 output Without dead time TO0n3 output...
Page 256 CHAPTER 9 TIMER/COUNTER FUNCTION Next, an example of the operation timing, which depends on the values set to CM0n0 to CM0n2 (BFCMn0 to BFCMn2) is shown. (a) When CM0nx (BFCMnx) ≥ CM0n3 is set Figure 9-17. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave, BFCMnx ≥ CM0n3) CM0n3 CM0n3 TM0n...
Page 257 CHAPTER 9 TIMER/COUNTER FUNCTION (b) When CM0nx (BFCMnx) = 0000H is set Figure 9-18. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave, BFCMnx = 0000H) CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match BFCMnx 0000H 0000H 0000H CM0nx...
Page 258 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-19. Change Timing from 100% Duty State (PWM Mode 0) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value CM0nx CM0nx CM0nx CM0nx match match match match CM0nx match CM0nx match 0000H 0000H BFCM0nx 0000H 0000H CM0nx INTTM0n INTTM0n INTTM0n...
Page 259 CHAPTER 9 TIMER/COUNTER FUNCTION (3) PWM mode 1: Triangular wave modulation (right-left asymmetric waveform control) [Setting procedure] (a) Set PWM mode 1 (asymmetric triangular wave) with bits MOD01 and MOD00 of the TMC0n register. Also set the active level of pins TO0n0 to TO0n5 with the ALVTO bit of the TOMRn register (n = 0, 1). (b) Set the count clock of TM0n with bits PRM02 to PRM00 of the TMC0n register.
Page 260 CHAPTER 9 TIMER/COUNTER FUNCTION [Operation] In PWM mode 1, TM0n performs up/down count operation. When TM0n = 0000H during down counting, an underflow interrupt (INTTM0n) is generated, and when TM0n = CM0n3 during up counting, a match interrupt (INTCM0n3) is generated (n = 0, 1). Switching from up counting to down counting is performed when TM0n and CM0n3 match (INTCM0n3), and switching from down counting to up counting is performed by INTTM0n.
Page 261 CHAPTER 9 TIMER/COUNTER FUNCTION [Output waveform width in respect to set value] • PWM cycle = BFCMn3 × 2 × T TM0n • Dead-time width = (DTRRn + 1)/f • Active width of positive phase (TO0n0, TO0n2, TO0n4 pins) = { (CM0n3 − CM0nX ) + (CM0n3 −...
Page 262 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-20. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave) CM0n3 (f) CM0n3 (g) TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match match BFCMnx CM0nx BFCMn3 CM0n3 Interrupt request INTCM0n3 INTTM0n INTCM0n3 INTTM0n DTMnx Positive phase...
Page 263 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-21. Overall Operation Image of PWM Mode 1 (Asymmetric Triangular Wave) CM0n3 CM0n3 CM0n2 CM0n2 CM0n2 CM0n2 CM0n1 CM0n1 TM0n CM0n1 CM0n1 CM0n0 count value CM0n0 CM0n0 CM0n0 0000H TO0n0 output TO0n1 output TO0n2 output Without dead time TO0n3 output...
Page 264 CHAPTER 9 TIMER/COUNTER FUNCTION (a) When BFCMnx ≥ CM0n3 is set in software processing started by INTCM0n3 Figure 9-22. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx ≥ CM0n3) CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx match match BFCMnx CM0nx...
Page 265 CHAPTER 9 TIMER/COUNTER FUNCTION (b) When BFCMnx > CM0n3 is set in software processing started by INTTM0n Figure 9-23. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx > CM0n3) CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx CM0nx INTCM0n3 INTTM0n...
Page 266 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-24. Change Timing from 100% Duty State (PWM Mode 1) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match BFCM0nx CM0nx Interrupt request INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n Note DTMnx...
Page 267 CHAPTER 9 TIMER/COUNTER FUNCTION (c) When BFCMnx = 0000H is set in software processing started by INTCM0n3 Figure 9-25. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = 0000H) (1) CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx match match BFCMnx...
Page 268 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-26. Change Timing from 100% Duty State (1) (PWM Mode 1) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx CM0nx match match match match match BFCM0nx 0000H 0000H 0000H 0000H CM0nx 0000H 0000H 0000H 0000H Interrupt request INTCM0n3...
Page 269 CHAPTER 9 TIMER/COUNTER FUNCTION (d) When BFCMnx = 0000H is set in software processing started by INTTM0n Figure 9-27. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = 0000H) (2) CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx 0000H 0000H...
Page 270 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-28. Change Timing from 100% Duty State (2) (PWM Mode 1) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match BFCM0nx 0000H 0000H 0000H 0000H 0000H CM0nx 0000H 0000H 0000H 0000H 0000H Interrupt request INTCM0n3 INTTM0n...
Page 271 CHAPTER 9 TIMER/COUNTER FUNCTION (e) When BFCMnx = CM0n3 is set in software processing started by INTTM0n Figure 9-29. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = CM0n3) CM0n3 CM0n3 count value 0000H CM0nx CM0nx match match BFCMnx CM0nx INTCM0n3...
Page 272 CHAPTER 9 TIMER/COUNTER FUNCTION (4) PWM mode 2: Sawtooth wave modulation [Setting procedure] (a) Set PWM mode 2 (sawtooth wave) with bits MOD01 and MOD00 of the TMC0n register. Also set the active level of pins TO0n0 to TO0n5 with the ALVTO bit of the TOMRn register. (b) Set the count clock of TM0n with bits PRM02 to PRM00 of the TMC0n register.
Page 273 CHAPTER 9 TIMER/COUNTER FUNCTION [Operation] In PWM mode 2, TM0n performs up-count operation, and when it matches the value of CM0n3, match interrupt INTCM0n3 is generated and TM0n is cleared (n = 0, 1). The PWM cycle in this mode is ((BFCMn3 value + 1) × TM0n count clock). Concerning setting of data to CM0n3, the next PWM cycle width is set to BFCMn3.
Page 274 CHAPTER 9 TIMER/COUNTER FUNCTION [Output waveform width in respect to set value] • PWM cycle = (BFCMn3 + 1) × T TM0n • Dead-time width = (DTRRn + 1)/f • Active width of positive phase (TO0n0, TO0n2, TO0n4 pins) = (CM0nX + 1) × T −...
Page 275 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-30. Operation Timing in PWM Mode 2 (Sawtooth Wave) CM0n3 (d) CM0n3 (e) TM0n count value 0000H CM0nx CM0nx match match BFCMnx CM0nx BFCMn3 CM0n3 INTCM0n3 INTCM0n3 Interrupt request Set by rising edge of TM0CEn bit DTMnx Positive phase (TO0n0, TO0n2, TO0n4)
Page 276 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-31. Overall Operation Image of PWM Mode 2 (Sawtooth Wave) CM0n3 CM0n3 CM0n2 CM0n2 CM0n1 CM0n1 TM0n CM0n0 CM0n0 count value 0000H TO0n0 output TO0n1 output TO0n2 output Without dead time TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output...
Page 277 CHAPTER 9 TIMER/COUNTER FUNCTION (a) When BFCMnx > CM0n3 is set Figure 9-32. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx > CM0n3) CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx CM0nx Interrupt request INTCM0n3 INTCM0n3 INTCM0n3 Set by rising edge of TM0CEn bit DTMnx...
Page 278 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-33. Change Timing from 100% Duty State (PWM Mode 2) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx match match BFCM0nx CM0nx INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 Interrupt request Note DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) Note F/F is reset upon occurrence of match with CM0nx.
Page 279 CHAPTER 9 TIMER/COUNTER FUNCTION (b) When BFCMnx = CM0n3 is set Figure 9-34. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3) CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx CM0nx Interrupt request INTCM0n3 INTCM0n3 INTCM0n3 Set by rising edge of TM0CEn bit DTMnx...
Page 280 CHAPTER 9 TIMER/COUNTER FUNCTION (c) When BFCMnx = 0000H is set Figure 9-35. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = 0000H) CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match match BFCMnx CM0nx Interrupt request INTCM0n3...
Page 281 CHAPTER 9 TIMER/COUNTER FUNCTION (d) When BFCMnx = 0000H is set while DTMnx = 000H or TM0CEDn bit = 1 A pulse equivalent to one count clock of the timer is output. Figure 9-36. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = 0000H While DTMnx = 000H or TM0CEDn Bit = 1) CM0n3 CM0n3...
Page 282 CHAPTER 9 TIMER/COUNTER FUNCTION (e) When BFCMnx = CM0n3 = a is set Figure 9-37. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3 = a) (When DTRRn = 0000H, TM0CEDn Bit of TMC0n Register = 1, ALVTO Bit of TOMRn Register = 1 (PWM Driving, Active Level = High) Are Set) CM0n3 CM0n3...
Page 283 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-38. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3 = a) (When DTRRn = 0000H, TM0CEDn Bit of TMC0n Register = 1, ALVTO Bit of TOMRn Register = 0 (PWM Driving, Active Level = Low) Are Set) CM0n3 CM0n3 CM0n3...
Page 284: Operation Timing
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.6 Operation timing (1) TM0CEn bit write and TM0n timer operation timing Figure 9-39 shows the timing from write of the TM0CEn bit of the TMC0n register until the TM0n timer starts operating. Figure 9-39. TM0CEn Bit Write and TM0n Timer Operation Timing TM0CEn bit write timing Register write timing...
Page 285 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Interrupt generation timing The interrupt generation timing with the count clock setting (PRM02 to PRM00 bits of the TMC0n register) to TM0n in the various modes is described below. Figure 9-40. Interrupt Generation Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave) (a) When count clock = f CM0n3...
Page 286 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-41. Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave) (a) When count clock = f CM0n3 0002H TM0n 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H INTCM0n3 (b) When count clock = f 0002H...
Page 287 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Relationship between interrupt generation and STINTn bit of TMC0n register The interrupt generation timing for the setting of the STINTn bit of the TMC0n register and the interrupt culling ratio setting (bits CUL02 to CUL00) in the various modes is described below. If, to realize the INTTM0n and INTCM0n3 interrupt culling function for TM0n, bits CUL02 to CUL00 of the TMC0n register are set for a culling ratio other than 1/1, and count operation is started, the interrupt output order differs according to the setting of the STINTn bit when counting starts.
Page 288 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-43. Interrupt Generation Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave): In Case of Interrupt Culling Ratio of 1/2 (a) When STINTn bit = 0 TM0CEn bit 0004H CM0n3 TM0n 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H INTCM0n3...
Page 289 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-44. Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave): In Case of Interrupt Culling Ratio of 1/1 (a) When STINTn bit = 0 TM0CEn bit 0004H CM0n3 TM0n 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H INTCM0n3 (b) When STINTn bit = 1 TM0CEn bit...
Page 290 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-45. Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave): In Case of Interrupt Culling Ratio of 1/2 (a) When STINTn bit = 0 TM0CEn bit 0004H CM0n3 TM0n 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H INTCM0n3 (b) When STINTn bit = 1 TM0CEn bit...
Page 291 CHAPTER 9 TIMER/COUNTER FUNCTION (4) TO0n0 to TO0n5 output timing Figure 9-46. TO0n0 to TO0n5 Output Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave) TM0CEn bit 0008H CM0n3 CM0nx 0003H TM0n 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0002H DTRRn...
Page 292 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-47. TO0n0 to TO0n5 Output Timing in PWM Mode 2 (Sawtooth Wave) TM0CEn bit 000AH CM0n3 CM0nx 0005H TM0n 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0002H DTRRn DTMnx...
Page 293: Timer 1
CHAPTER 9 TIMER/COUNTER FUNCTION 9.2 Timer 1 9.2.1 Features (timer 1) Timers 10, 11 (TM10, TM11) are 16-bit up/down counters that perform the following operations. • General-purpose timer mode (See 9.2.5 (1) Operation in general-purpose timer mode.) Free-running timer PWM output •...
Page 294 CHAPTER 9 TIMER/COUNTER FUNCTION • PWM output function In the general-purpose timer mode, 16-bit resolution PWM output can be output from the TO1n pin. • Timer clear The following timer clear operations are performed according to the mode that is used. (a) General-purpose timer mode: Timer clear operation is possible upon occurrence of match with CM1n0 set value.
Page 295: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.3 Basic configuration The basic configuration is shown below. Table 9-4. Timer 1 Configuration List Timer Count Clock Register Read/Write Generated Capture Trigger Interrupt Signal Note 1 Note 2 − − Timer 1 TM10 Read/write /16, −...
Page 296 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-48. Block Diagram of Timer 1 Internal bus Edge INTP1n0/ detector CC1n0 Selector INTCC1n0 Note INTP1n1 CC1n1 Edge TM1UBDn Selector detector INTCC1n1 TCLR1n/ Edge TCLR INTP1n1 detector Clear TM1OVFn TM1UDFn TCUD1n/ Edge 1/2, 1/4, 1/8, 1/16, detector INTP1n0 1/32, 1/64, 1/128...
Page 297 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timers 10, 11 (TM10, TM11) TM1n is a general-purpose timer (in general-purpose mode) and 2-phase encoder input up/down counter (in UDC mode). This timer counts up in the general-purpose timer mode and counts up/down in the UDC mode. TM1n can be read/written in 16-bit units.
Page 298 CHAPTER 9 TIMER/COUNTER FUNCTION (b) Up/down counter mode (UDC mode) In the UDC mode, TM1n functions as a 16-bit up/down counter, counting based on the TCUD1n and TIUD1n input signals. This mode is divided into the UDC mode A and UDC mode B, depending on the condition of clearing TM1n.
Page 299: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.4 Control registers (1) Timer 1/timer 2 clock selection register (PRM02) The PRM02 register is used to select the base clock (f ) of timer 1 (TM1n) and timer 2 (TM2n). This register can be read/written in 8-bit or 1-bit units. Caution Always set this register before using the timers 1 and 2.
Page 300 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Timer unit mode registers 0, 1 (TUM0, TUM1) The TUMn register is an 8-bit register used to specify the TM1n operation mode or to control the operation of the PWM output pin. TUMn can be read/written in 8-bit or 1-bit units. Cautions 1.
Page 301 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer control registers 10, 11 (TMC10, TMC11) The TMC1n register is used to enable/disable TM1n operation and to set transfer and timer clear operations. TMC1n can be read/written in 8-bit or 1-bit units. Caution Changing the value of bits of the TMC1n register other than the TM1CEn bit during TM1n operation (TM1CEn bit = 1) is prohibited.
Page 302 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function 1, 0 CLR1, CLR0 Controls TM1n clear operation in UDC mode A. CLR1 CLR0 Specify TM1n clear source Clear only by external input (TCLR1n) Clear upon match of TM1n count value and CM1n0 set value Clear by TCLR1n input or upon match of TM1n count value and CM1n0 set value...
Page 303 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Capture/compare control registers 0, 1 (CCR0, CCR1) The CCRn register specifies the operation mode of the capture/compare registers (CC1n0, CC1n1). CCRn can be read/written in 8-bit or 1-bit units. Caution Overwriting the CCRn register during TM1n operation (TM1CEn bit = 1) is prohibited. Address Initial value CCR0...
Page 304 CHAPTER 9 TIMER/COUNTER FUNCTION (5) Signal edge selection registers 10, 11 (SESA10, SESA11) The SESA1n register is used to specify the valid edge of external interrupt requests from external pins (INTP100, INTP101, INTP110, INTP111, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, TCLR11). The correspondences between each register and the external interrupt requests it controls are as follows.
Page 305 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function 5, 4 CESUDn1, Specifies valid edge of pins TCLR10, TCLR11. CESUDn0 CESUDn1 CESUDn0 Valid edge Falling edge Rising edge Low level High level The set values of bits CESUDn1 and CESUDn0 and the TM1n operation are related as follows.
Page 306 CHAPTER 9 TIMER/COUNTER FUNCTION (6) Prescaler mode registers 10, 11 (PRM10, PRM11) The PRM1n register is used to perform the following selections. • Selection of count clock in the general-purpose timer mode (CMD bit of TUMn register = 0) • Selection of count operation mode in the UDC mode (CMD bit = 1) PRM1n can be read/written in 8-bit or 1-bit units.
Page 307 CHAPTER 9 TIMER/COUNTER FUNCTION (a) In general-purpose timer mode (CMD bit of TUMn register = 0) The count clock is specified with the PRM12 to PRM10 bits. (b) UDC mode (CMD bit of TUMn register = 1) The TM1n count sources in the UDC mode are as follows. Operation Mode TM1n Operation Mode 1...
Page 308 CHAPTER 9 TIMER/COUNTER FUNCTION (7) Status registers 0, 1 (STATUS0, STATUS1) The STATUSn register indicates the operating status of TM1n. STATUSn is read-only, in 8-bit or 1-bit units. <2> <1> <0> Address Initial value STATUS0 TM1UDF0 TM1OVF0 TM1UBD0 FFFFF5EFH <2> <1>...
Page 309 CHAPTER 9 TIMER/COUNTER FUNCTION (8) CC101 capture input selection register (CSL10) The CSL10 register is used to select the INTP101 or INTP100 pin to input a capture signal when the CC101 register is used as a capture register. CSL10 can be read/written in 8-bit or 1-bit units. Address Initial value CSL10...
Page 310 CHAPTER 9 TIMER/COUNTER FUNCTION (10) Compare registers 100, 110 (CM100, CM110) CM1n0 is a 16-bit register that always compares its value with the value of TM1n. When the value of a compare register matches the value of TM1n, an interrupt signal is generated. The interrupt generation timing in the various modes is described below.
Page 311 CHAPTER 9 TIMER/COUNTER FUNCTION (12) Capture/compare registers 100, 110 (CC100, CC110) CC1n0 is a 16-bit register. It can be used as a capture register or as a compare register through specification with capture/compare control register n (CCRn). CC1n0 can be read/written in 16-bit units. Cautions 1.
Page 312 CHAPTER 9 TIMER/COUNTER FUNCTION (13) Capture/compare registers 101, 111 (CC101, CC111) CC1n1 is a 16-bit register. It can be used as a capture register or as a compare register through specification with capture/compare control register n (CCRn). CC1n1 can be read/written in 16-bit units. Cautions 1.
Page 313: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.5 Operation (1) Operation in general-purpose timer mode TM1n can perform the following operations in the general-purpose timer mode. (a) Interval operation (when ENMD bit of TMC1n register = 1) TM1n and CM1n0 always compare their values and the INTCM1n0 interrupt is generated upon occurrence of a match.
Page 314 CHAPTER 9 TIMER/COUNTER FUNCTION Table 9-6. Capture Trigger Signal (TM1n) to 16-Bit Capture Register Capture Register Capture Trigger Signal CC1n0 INTP1n0 CC1n1 INTP1n0 or INTP1n1 Remarks 1. CC1n0 and CC1n1 are capture/compare registers. Which of these registers is used is specified with capture/compare control register n (CCRn).
Page 315 CHAPTER 9 TIMER/COUNTER FUNCTION (i) Description of operation The CM1n0 register is a compare register used to set the PWM output cycle. When the value of this register matches the value of TM1n, the INTCM1n0 interrupt is generated. Compare match is saved by hardware, and TM1n is cleared at the next count clock after the match.
Page 316 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Operation in UDC mode (a) Overview of operation in UDC mode The count clock input to TM1n in the UDC mode (CMD bit of TUMn register = 1) can only be external input from the TIUD1n and TCUD1n pins. Up/down count judgment in the UDC mode is determined based on the phase difference of the TIUD1n and TCUD1n pin inputs according to the PRM1n register setting (there is a total of four choices).
Page 317 CHAPTER 9 TIMER/COUNTER FUNCTION (b) Up/down count operation in UDC mode TM1n up/down count judgment in the UDC mode is determined based on the phase difference of the TIUD1n and TCUD1n pin inputs according to the PRM1n register setting. (i) Mode 1 (PRM1n register’s PRM12 bit = 1, PRM11 bit = 0, PRM10 bit = 0) In mode 1, the following count operations are performed based on the level of the TCUD1n pin upon detection of the valid edge of the TIUD1n pin.
Page 318 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-52. Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin): In Case of Simultaneous TIUD1n, TCUD1n Pin Edge Timing TIUD1n TCUD1n TM1n 0007H 0006H 0005H 0004H 0005H 0006H 0007H Down count Up count Remark n = 0, 1...
Page 319 CHAPTER 9 TIMER/COUNTER FUNCTION (iii) Mode 3 (PRM1n register’s PRM12 = 1, PRM11 = 1, PRM10 = 0) In mode 3, when two signals 90 degrees out of phase are input to the TIUD1n and TCUD1n pins, the level of the TCUD1n pin is sampled at the input of the valid edge of the TIUD1n pin (refer to Figure 9-54).
Page 320 CHAPTER 9 TIMER/COUNTER FUNCTION (iv) Mode 4 (PRM1n register’s PRM12 = 1, PRM11 = 1, PRM10 = 1) In mode 4, when two signals out of phase are input to the TIUD1n and TCUD1n pins, up/down operation is automatically judged and counting is performed according to the timing shown in Figure 9-56.
Page 321 CHAPTER 9 TIMER/COUNTER FUNCTION (c) Operation in UDC mode A (i) Interval operation The operations at the count clock following match of the TM1n count value and the CM1n0 set value are as follows. • In case of up-count operation: TM1n is cleared (0000H) and the INTCM1n0 interrupt is generated. •...
Page 322 CHAPTER 9 TIMER/COUNTER FUNCTION (d) Operation in UDC mode B (i) Basic operation The operations at the next count clock after the count value of TM1n and the CM1n0 set value match when TM1n is in UDC mode B are as follows. •...
Page 323: Supplementary Description Of Internal Operation
CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.6 Supplementary description of internal operation (1) Clearing of count value in UDC mode B When TM1n is in UDC mode B, the conditions to clear the count value are as follows. • In case of TM1n up-count operation: TM1n count value is cleared upon match with the CM1n0 register •...
Page 324 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-60. Clear Operation After Match of CM1n1 Register Set Value and TM1n Count Value (a) Down count → Down count TM1n cleared Count clock (Rising edge set as valid edge) TM1n 00FFH 00FEH 0000H FFFFH CM1n1 register 00FEH Down count...
Page 325 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Interrupt signal output upon compare match An interrupt signal is output when the count value of TM1n matches the set value of the CM1n0, CM1n1, Note Note CC1n0 , or CC1n1 register. The interrupt generation timing is as follows. Note When CC1n0 and CC1n1 are set to the compare register mode.
Page 326: Timer 2
CHAPTER 9 TIMER/COUNTER FUNCTION 9.3 Timer 2 9.3.1 Features (timer 2) Timers 20, 21 (TM20, TM21) are 16-bit general-purpose timer units that perform the following operations. • Pulse interval or frequency measurement and programmable pulse output • Interval timer • PWM output timer •...
Page 327 CHAPTER 9 TIMER/COUNTER FUNCTION • Interrupt request sources • Compare-match interrupt request: 6 types Perform comparison with sub-channel n capture/compare register and generate the INTCC2n interrupt upon compare match. • Timer/counter overflow interrupt request: 2 types The INTTM20 (INTTM21) interrupt is generated when the count value of TM20 (TM21) becomes FFFFH. •...
Page 328: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.3 Basic configuration The basic configuration is shown below. Table 9-8. Timer 2 Configuration List Timer Count Clock Register Read/Write Generated Capture Trigger Other Functions Interrupt Signal Note 1 Note 2 − − Timer 2 TM20 INTTM20 Note 3 /16,...
Page 329 CHAPTER 9 TIMER/COUNTER FUNCTION The following shows the capture/compare operation sources. Table 9-9. Capture/Compare Operation Sources Register Sub-channel Timer to Be Captured Timer to Be Compared Timer Captured in 32-Bit Cascade Connection − CVSE00 TM20 TM20 CVPEn0 TM21 when BFEEy bit of TM20 when TB1Ey, TB0Ey TM21 CMSEm0 register = 0...
Page 330 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-64. Block Diagram of Timer 2 ECLR 1/2, 1/4, 1/8, CNT = MAX. INTTM20 1/16, 1/32, TCOUNTE0 TM20 1/64, 1/128 edge selection CNT = 0 (16-bit) TCOUNTE1 edge selection INTCC20 TI2/ Input filter TINE0 INTP20 edge selection CVSE00 (16-bit)
Page 331 CHAPTER 9 TIMER/COUNTER FUNCTION Table 9-11. Meaning of Signals in Block Diagram Signal Name Meaning Note 1 CASC TM21 count signal input in 32-bit mode Count value of timer 2 (CNT = MAX.: Maximum value count signal output of timer 2 (generated when TM2n = FFFFH), CNT = 0: Zero count signal output of timer 2 (generated when TM2n = 0000H)) TM2n count signal input in 16-bit mode...
Page 332 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timers 20, 21 (TM20, TM21) The features of TM2n are listed below. • Free-running counter that enables counter clearing by compare match of sub-channel 0 and sub-channel 5 • Can be used as a 32-bit capture timer when TM20 and TM21 are connected in cascade. •...
Page 333 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 1 to 4) The CVPEn0 register is a sub-channel n 16-bit main capture/compare register. In the capture register mode, this register captures the value of TM21 when the BFEEn bit of the CMSEm0 register = 0 (m = 12, 34).
Page 334 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Timer 2 sub-channel n sub capture/compare register (CVSEn0) (n = 1 to 4) The CVSEn0 register is a sub-channel n 16-bit sub capture/compare register. In the compare register mode, this register can be used as a buffer. In the capture register mode, this register captures the value of TM20 when the BFEEn bit of the CMSEm0 register = 0 (m = 12, 34).
Page 335: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.4 Control registers (1) Timer 1/timer 2 clock selection register (PRM02) The PRM02 register is used to select the base clock (f ) of timer 1 and timer 2. This register can be read/written in 8-bit or 1-bit units. Caution Always set this register before using timer 1 and timer 2.
Page 336 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer 2 count clock/control edge selection register 0 (CSE0) The CSE0 register is used to specify the TM2n count clock and the control valid edge (n = 0, 1). This register can be read/written in 16-bit units. When the higher 8 bits of the CSE0 register are used as the CSE0H register, and the lower 8 bits are used as the CSE0L register, they can be read/written in 8-bit or 1-bit units.
Page 337 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Note Setting the TESnE1 and TESnE0 bits to 11B and the CSEn2 to CSEn0 bits to 000B for timer 2 count clock/control edge select register 0 (CSE0) is prohibited. Caution Set the VSWC register to 15H when the PRM2 bit of the timer 1/timer 2 clock selection register (PRM02) = 0B (f /4) and set the VSWC register to 12H when the PRM2 bit = 1B (f /2).
Page 338 CHAPTER 9 TIMER/COUNTER FUNCTION (5) Timer 2 time base control register 0 (TCRE0) The TCRE0 register controls the operation of TM2n (n = 0, 1). This register can be read/written in 16-bit units. When the higher 8 bits of the TCRE0 register are used as the TCRE0H register, and the lower 8 bits are used as the TCRE0L register, they can be read/written in 8-bit or 1-bit units.
Page 339 CHAPTER 9 TIMER/COUNTER FUNCTION (1/2) <14> <13> <6> <5> Address Initial value TCRE0 CASE1 CLRE1 CEE1 ECRE1 ECEE1 OSTE1 UDSE11 UDSE10 CLRE0 CEE0 ECRE0 ECEE0 OSTE0 UDSE01 UDSE00 FFFFF646H 0000H Bit position Bit name Function CASE1 Specifies 32-bit cascade operation mode for TM21 (TM21 counts upon overflow of TM20 (carry count)).
Page 340 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function 11, 3 ECEEn Specifies TM2n count operation enable/disable through ECLR signal input. 0: TM2n count operation not enabled 1: TM2n count operation enabled Cautions 1. In the 32-bit cascade operation mode (CASE1 = 1), the TM2n count operation using ECLR signal input is not performed.
Page 341 CHAPTER 9 TIMER/COUNTER FUNCTION (6) Timer 2 output control register 0 (OCTLE0) The OCTLE0 register controls timer output from the TO2n pin (n = 1 to 4). This register can be read/written in 16-bit units. When the higher 8 bits of the OCTLE0 register are used as the OCTLE0H register, and the lower 8 bits are used as the OCTLE0L register, they can be read/written in 8-bit or 1-bit units.
Page 342 CHAPTER 9 TIMER/COUNTER FUNCTION (a) Caution for PWM output change timing If the SWFEn bit is changed from 1 to 0 when the timer is operating while the internal PWM output operation is being performed, then the output level becomes active. After that, PWM output from the TO2n pin is performed upon a compare match at subchannel n.
Page 343 CHAPTER 9 TIMER/COUNTER FUNCTION (7) Timer 2 sub-channel 0, 5 capture/compare control register (CMSE050) The CMSE050 register controls timer 2 sub-channel 0 capture/compare register (CVSE00) and timer 2 sub- channel 5 capture/compare register (CVSE50). This register can be read/written in 16-bit units. Address Initial value CMSE050...
Page 344 CHAPTER 9 TIMER/COUNTER FUNCTION (8) Timer 2 sub-channel 1, 2 capture/compare control register (CMSE120) The CMSE120 register controls the timer 2 sub-channel n sub capture/compare register (CVSEn0) and the timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 1, 2). This register can be read/written in 16-bit units.
Page 345 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function 11, 3 LNKEn Selects capture event signal input from edge selection and specifies transfer operation in compare register mode. 0: Select ED1 signal input in capture register mode. In the compare register mode, the data of the CVSEn0 register is transferred to the CVPEn0 register upon occurrence of TM2x compare match (TM2x = timer/ counter selected with bits TB1En, TB0En).
Page 346 CHAPTER 9 TIMER/COUNTER FUNCTION (9) Timer 2 sub-channel 3, 4 capture/compare control register (CMSE340) The CMSE340 register controls the timer 2 sub-channel n sub capture/compare register (CVSEn0) and the timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 3, 4). This register can be read/written in 16-bit units.
Page 347 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function 11, 3 LNKEn Selects capture event signal input from edge selection and specifies transfer operation in compare register mode. 0: Select ED1 signal input in capture register mode. In the compare register mode, the data of the CVSEn0 register is transferred to the CVPEn0 register upon occurrence of TM2x compare match (TM2x = timer/ counter selected with bits TB1En, TB0En).
Page 348 CHAPTER 9 TIMER/COUNTER FUNCTION (10) Timer 2 time base status register 0 (TBSTATE0) The TBSTATE0 register indicates the status of TM2n (n = 0, 1). This register can be read/written in 16-bit units. When the higher 8 bits of the TBSTATE0 register are used as the TBSTATE0H register, and the lower 8 bits are used as the TBSTATE0L register, they can be read/written in 8-bit or 1-bit units.
Page 349 CHAPTER 9 TIMER/COUNTER FUNCTION (11) Timer 2 capture/compare 1 to 4 status register 0 (CCSTATE0) The CCSTATE0 register indicates the status of the timer 2 sub-channel sub capture/compare register (CVSEn0) and the timer 2 sub-channel main capture/compare register (CVPEn0) (n = 1 to 4). This register can be read/written in 16-bit units.
Page 350 CHAPTER 9 TIMER/COUNTER FUNCTION (12) Timer 2 output delay register 0 (ODELE0) The ODELE0 register sets the output delay operation synchronized with the clock to the TO2n pin’s output delay circuit (n = 1 to 4). This register can be read/written in 16-bit units. When the higher 8 bits of the ODELE0 register are used as the ODELE0H register, and the lower 8 bits are used as the ODELE0L register, they can be read/written in 8-bit or 1-bit units.
Page 351 CHAPTER 9 TIMER/COUNTER FUNCTION (13) Timer 2 software event capture register (CSCE0) The CSCE0 register sets capture operation by software in the capture register mode. This register can be read/written in 16-bit units. Address Initial value CSCE0 SEVE5 SEVE4 SEVE3 SEVE2 SEVE1 SEVE0...
Page 352: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.5 Operation (1) Edge detection The edge detection timing is shown below. Figure 9-66. Edge Detection Timing Note TINEx, TCLR2, TCOUNTEn MUXTB0 ED1, ED2 ECLR Note Set values of TESnE1, TESnE0 bits and CESE1, CESE0 bits of CSE0 register, and IESEx1, IESEx0 bits of SESE0 register.
Page 353 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Basic operation of timer 2 Figures 9-67 to 9-70 show the basic operation of timer 2. Figure 9-67. Timer 2 Up-Count Timing (When TCRE0 Register’s UDSEn1, UDSEn0 Bits = 00B, ECEEn Bit = 0, ECREn Bit = 0, CLREn Bit = 0, CASE1 Bit = 0) Note 1 OSTEn bit Note 1...
Page 354 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-68. External Control Timing of Timer 2 (When TCRE0 Register’s UDSEn1, UDSEn0 Bits = 00B, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 0) Note ECEEn bit Note ECREn bit Note CLREn bit ECLR 1234H 1235H...
Page 355 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-69. Operation in Timer 2 Up-/Down-Count Mode (When TCRE0 Register’s ECEEn Bit = 0, ECREn Bit = 0, CLREn Bit = 0, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 0) Note 1 UDSEn1, UDSEn0 bits don't care ECLR...
Page 356 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-70. Timing in 32-Bit Cascade Operation Mode (When TCRE0 Register’s UDSEn1, UDSEn0 Bits = 00B, ECEEn Bit = 0, ECREn Bit = 0, CLREn Bit = 0, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 1) Note CASC...
Page 357 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Operation of capture/compare register (sub-channels 1 to 4) Sub-channels 1 to 4 receive the count value of the timer 2 multiplex count generator. The multiplex count generator is an internal unit of TM2n that supplies the multiplex count value MUXCNT to sub-channels 1 to 4.
Page 358 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-72. Multiplex Count Timing CNT (0) FFFEH FFFFH 0000H 0001H 1234H 1235H CNT (1) MUXTB0 MUXTB1 MUXCNT FFFEH 1234H FFFFH 1234H FFFFH 1234H FFFFH 1234H 0000H 1235H 0000H 1235H 0000H 1235H 0001H 1235H 0001H 1235H 0001H Remarks 1.
Page 359 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-73. Capture Operation: 16-Bit Buffer-Less Mode (When Operation Is Delayed Through Setting of LNKEy Bit of CMSEx0 Register, and CMSEx0 Register’s CCSEy Bit = 0, BFEEy Bit = 0, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0) MUXTB0 MUXTB1 MUXCNT...
Page 360 CHAPTER 9 TIMER/COUNTER FUNCTION Note 1 Figure 9-74. Capture Operation: Mode with 16-Bit Buffer (When CMSEx0 Register’s TByE1 Bit = 0, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = 1, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0) MUXTB0 MUXTB1...
Page 361 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-75. Capture Operation: 32-Bit Cascade Operation Mode (When CMSEx Register’s TByE1 Bit = 1, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = Arbitrary, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0) TCOUNTE0 = TCOUNTE1...
Page 362 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-76. Capture Operation: Capture Control by Software and Trigger Timing (When CMSEx0 Register’s TByE1 Bit = 0, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = 1) MUXTB0 MUXTB1 MUXCNT Note 1 EEVEy bit...
Page 363 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-77. Compare Operation: Buffer-Less Mode (When CMSEx0 Register’s CCSEy Bit = 1, LNKEy Bit = Arbitrary, BFEEy Bit = 0) MUXTB0 MUXTB1 MUXCNT Note 1 TB0Ey bit Note 1 TB1Ey bit WRITE_ENABLE_S RELOAD_PRIMARY CVSEm0 register CVPEm0 register RELOAD1 Note 2...
Page 364 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-78. Compare Operation: Mode with Buffer (When Operation Is Delayed Through Setting of LNKEy Bit of CMSEx0 Register, CMSEx0 Register’s CCSEy Bit = 1, BFEEy Bit = 1) MUXTB0 MUXTB1 MUXCNT Note LNKEy bit WRITE_ENABLE_S RELOAD2A RELOAD1 RELOAD_PRIMARY...
Page 365 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Operation of capture/compare register (sub-channels 0, 5) Figures 9-79 and 9-80 show the operation of the capture/compare register (sub-channels 0, 5). Figure 9-79. Capture Operation: Timer 2 Count Value Read Timing (When CMSE050 Register’s CCSEy Bit = 0, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0) Note 1 LNKEy...
Page 366 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-80. Compare Operation: Timing of Compare Match and Write Operation to Register (When CMSE050 Register’s CCSEy Bit = 1, EEVEy Bit = Arbitrary, and CSCE0 Register’s SEVEy Bit = Arbitrary) CPU write C/C CVSEy0 register MATCH Note 1 Note 2...
Page 367 CHAPTER 9 TIMER/COUNTER FUNCTION (5) Operation of output circuit Figures 9-81 to 9-84 show the output circuit operation. Figure 9-81. Signal Output Operation: Toggle Mode 0 and Toggle Mode 1 (When OCTLE0 Register’s SWFEn Bit = 0, and ODELE0 Register’s ODLEn2 to ODLEn0 Bits = 0) Note 1 OTMEn1, OTMEn0 bits...
Page 368 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-82. Signal Output Operation: Toggle Mode 2 and Toggle Mode 3 (When OCTLE0 Register’s SWFEn Bit = 0, and ODELE0 Register’s ODLEn2 to ODLEn0 Bits = 0) Note 1 OTMEn1, OTMEn0 bits TO2n timer output Note 2 (ALVEn bit = 0 TO2n timer output...
Page 369 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-84. Signal Output Operation: During Delay Output Operation (When OCTLE0 Register’s OTMEn1, OTMEn0 Bits = 0, ALVEn = 0, SWFEn Bit = 0) Note ODELEn2 to ODELEn0 bits TO2n timer output Note ODELEn2 to ODELEn0 bits of OCTLE0 register Remarks 1.
Page 370: Pwm Output Operation When Timer 2 Operates In Compare Mode
CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.6 PWM output operation when timer 2 operates in compare mode (1) Operation when TO2n pin performs PWM output operation in toggle mode 1 In toggle mode 1, the TO2n output (internal) becomes inactive triggered by a signal when TM20 = 0, and becomes active triggered by a sub-channel 1 (CVPEn0 register) compare match signal.
Page 371 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Operation when TO2n pin output is controlled by manipulating OCTLE0.SWFEn bit in toggle mode 1 (a) When a sub-channel n compare match signal is output immediately after the SWFEn bit is cleared to 0 Figures 9-86 and 9-87 show the waveforms when output from the TO2n output pin is started or ended by manipulating the SWFEn bit in toggle mode 1.
Page 372 CHAPTER 9 TIMER/COUNTER FUNCTION (b) When the trigger signal of TM20 = 0 is output immediately after the SWFEn bit is cleared to 0 When the trigger signal of TM20 = 0 is output immediately after the SWFEn bit is cleared to 0, from when the SWFEn bit is cleared to 0 to when the trigger signal of TM20 = 0 is output is the first active period, so a pulse shorter than the active period of the ordinary TO2n output is output.
Page 373: Timer 3
CHAPTER 9 TIMER/COUNTER FUNCTION 9.4 Timer 3 9.4.1 Features (timer 3) Timer 3 (TM3) is a 16-bit timer/counter that can perform the following operations. • Interval timer function • PWM output • External signal cycle measurement 9.4.2 Function overview (timer 3) •...
Page 374: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.3 Basic configuration Table 9-12. Timer 3 Configuration List Timer Count Clock Register Read/Write Generated Capture Timer Output Interrupt Trigger Note 1 Note 2 Signal − − Timer 3 Read INTTM3 /16, CC30 Read/write INTCC30 INTP30 TO3 (S) /16, /32,...
Page 375 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timer 3 (TM3) TM3 functions as a 16-bit free-running timer or as an event counter for an external signal. Besides being mainly used for cycle measurement, TM3 can be used as pulse output. TM3 is read-only, in 16-bit units. Cautions 1.
Page 376 CHAPTER 9 TIMER/COUNTER FUNCTION (b) Selection of the internal count clock TM3 operates as a free-running timer. When an internal clock is specified as a count clock by timer control register 31 (TMC31), TM3 is counted up for each input clock cycle specified by the CS2 to CS0 bits of the TMC30 register. A division by the prescaler can be selected for the count clock from among f /2, f /4, f...
Page 377 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Capture/compare registers 30 and 31 (CC30 and CC31) These capture/compare registers 30 and 31 are 16-bit registers. They can be used as capture registers or compare registers according to the CMS1 and CMS0 bit specifications of timer control register 31 (TMC31). These registers can be read/written in 16-bit units (however, write operations can only be performed in compare mode).
Page 378 CHAPTER 9 TIMER/COUNTER FUNCTION (b) Setting these registers to compare registers (CMS1 and CMS0 of TMC31 = 1) When these registers are set to compare registers, the TM3 and register values are compared for each count clock, and an interrupt is generated by a match. If the CCLR bit of timer control register 31 (TMC31) is set (1), the TM3 value is cleared (0) at the same time as a match with the CC30 register (it is not cleared (0) by a match with the CC31 register).
Page 379: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.4 Control registers (1) Timer 3 clock selection register (PRM03) The PRM03 register is used to select the base clock (f ) of timer 3 (TM3). This register can be read/written in 8-bit or 1-bit units. Cautions 1.
Page 380 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Timer control register 30 (TMC30) The TMC30 register controls the operation of TM3. This register can be read/written in 8-bit or 1-bit units. Cautions 1. The TM3CAE bit and other bits cannot be set at the same time. Be sure to set the TM3CAE bit and then set the other bits and the other registers of TM3.
Page 381 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function 6 to 4 CS2 to CS0 Selects the internal count clock for TM3. Count clock /128 /256 Caution Do not change the CS2 to CS0 bits during timer operation. If they are to be changed, they must be changed after setting the TM3CE bit to “0”.
Page 382 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer control register 31 (TMC31) The TMC31 register controls the operation of TM3. This register can be read/written in 8-bit or 1-bit units. Cautions 1. Do not change the bits of the TMC31 register during timer operation. If they are to be changed, they must be changed after setting the TM3CE bit of the TMC30 register to “0”.
Page 383 CHAPTER 9 TIMER/COUNTER FUNCTION Address Initial value TMC31 ENT1 CCLR ECLR CMS1 CMS0 FFFFF688H Bit position Bit name Function Sets the operation when TM3 overflows. 0: Continue count operation after overflow (free-running mode) 1: After overflow, timer holds 0000H and stops count operation (overflow stop mode).
Page 384 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Valid edge selection register (SESC) This register specifies the valid edge of external interrupt requests (TI3, TCLR3, INTP30, INTP31) from an external pin. The rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin.
Page 385: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.5 Operation (1) Count operation Timer 3 can function as a 16-bit free-running timer or as an external signal event counter. The setting for the type of operation is specified by timer control register 3n (TMC3n) (n = 0, 1). When it operates as a free-running timer, if the CC30 or CC31 register and the TM3 count value match, an interrupt signal is generated and the timer output signal (TO3) can be set or reset.
Page 386 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Overflow When the TM3 register has counted the count clock from FFFFH to 0000H, the TM3OVF bit of the TMC30 register is set (1), and an overflow interrupt (INTTM3) is generated at the same time. However, if the CC30 register is set to compare mode (CMS0 bit = 1) and to the value FFFFH when match clearing is enabled (CCLR bit = 1), then the TM3 register is considered to be cleared and the TM3OVF bit is not set (1) when the TM3 register changes from FFFFH to 0000H.
Page 387 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Capture operation The TM3 register has two capture/compare registers. These are the CC30 register and the CC31 register. A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMS0 bits of the TMC31 register.
Page 388 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-93. TM3 Capture Operation Example (When Both Edges Are Specified) (TM3 count values) ∆ ∆ Count start Overflow TM3CE ← 1 TM3OVF ← 1 Interrupt request (INTP31) Capture register (CC31) Remark D0 to D2: TM3 count values User’s Manual U14492EJ5V0UD...
Page 389 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Compare operation The TM3 register has two capture/compare registers. These are the CC30 register and the CC31 register. A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMS0 bits of the TMC31 register.
Page 390 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-94. Compare Operation Example (2/2) (b) If CCLR bit = 1 and CC30 is 0000H Count up FFFFH 0000H 0000H 0001H Compare register 0000H (CC30) INTTM3 (output) Match detection (INTCC30) Remark The match is detected immediately after the count up, and the match detection signal is generated.
Page 391 CHAPTER 9 TIMER/COUNTER FUNCTION (5) External pulse output Timer 3 has one timer output pin (TO3). An external pulse output (TO3) is generated when a match of the two compare registers (CC30 and CC31) and the TM3 register is detected. If a match is detected when the TM3 count value and the CC30 value are compared, the output level of the TO3 pin is set.
Page 392: Application Examples
CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.6 Application examples (1) Interval timer By setting the TMC30 and TMC31 registers as shown in Figure 9-96, timer 3 operates as an interval timer that repeatedly generates interrupt requests with the value that was set in advance in the CC30 register as the interval.
Page 393 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-97. Interval Timer Operation Timing Example Count clock TM3 register 0000H 0001H 0000H 0001H 0000H 0001H Count start Clear Clear CC30 register INTCC30 interrupt Interval time Interval time Interval time Remark p: Setting value of CC30 register (0000H to FFFFH) Count clock cycle Interval time = (p + 1) ×...
Page 394 CHAPTER 9 TIMER/COUNTER FUNCTION (2) PWM output By setting the TMC30 and TMC31 registers as shown in Figure 9-98, timer 3 can output a PWM of the frequency determined by the setting of the CS2 to CS0 bits of the TMC30 register with the values that were set in advance in the CC30 and CC31 registers as the intervals.
Page 395 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-99. PWM Output Operation Timing Example Count clock 0000H 0001H FFFFH 0000H 0001H register Count start Clear CC30 register CC31 register INTCC30 interrupt INTCC31 interrupt (output) Remarks 1. p: Setting value of CC30 register (0000H to FFFFH) q: Setting value of CC31 register (0000H to FFFFH) p ≠...
Page 396 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Cycle measurement By setting the TMC30 and TMC31 registers as shown in Figure 9-100, timer 3 can measure the cycle of signals input to the INTP30 pin or INTP31 pin. The valid edge of the INTP30 pin is selected according to the IES301 and IES300 bits of the SESC register, and the valid edge of the INTP31 pin is selected according to the IES311 and IES310 bits of the SESC register.
Page 397 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-101. Cycle Measurement Operation Timing Example Count clock 0000H 0001H FFFFH 0000H 0001H register Count start Clear INTP30 (input) CC30 register INTCC30 interrupt INTTM3 interrupt (D1 – D0) × t {(10000H – D1) + D2} × t (D3 –...
Page 398: Precautions
CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.7 Precautions Various precautions concerning timer 3 are shown below. (1) If a conflict occurs between the reading of the CC30 register and a capture operation when the CC30 register is used in capture mode, an external trigger (INTP30) valid edge is detected and an external interrupt request signal (INTCC30) is generated however, the timer value is not stored in the CC30 register.
Page 399: Timer 4
CHAPTER 9 TIMER/COUNTER FUNCTION 9.5 Timer 4 9.5.1 Features (timer 4) Timer 4 (TM4) functions as a 16-bit interval timer. 9.5.2 Function overview (timer 4) • 16-bit interval timer: 1 channel • Compare register: 1 • Count clock selected from divisions of internal system clock (set the frequency of the count clock to 16 MHz or less) •...
Page 400: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION 9.5.3 Basic configuration Table 9-14. Timer 4 Configuration List Timer Count Clock Register Read/Write Generated Capture Timer Output Other Interrupt Trigger Functions Signal − − − − Timer 4 /4, f /8, f /16, f /32, Read /64, f /128, f...
Page 401 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timer 4 (TM4) TM4 is a 16-bit timer. It is mainly used as an interval timer for software. Starting and stopping TM4 is controlled by the TM4CE0 bit of the timer control register 4 (TMC4). A division by the prescaler can be selected for the count clock from among f /4, f /8, f...
Page 402 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Compare register 4 (CM4) CM4 and the TM4 register count value are compared, and an interrupt request signal (INTCM4) is generated when a match occurs. TM4 is cleared, synchronized with this match. If the TM4CAE0 bit of the TMC4 register is set to 0, a reset is performed asynchronously, and the registers are initialized.
Page 403 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-103. Example of Timing During TM4 Operation (a) When TM4 < CM4 TM4CAE0 TM4CE0 INTCM4 Remark M = TM4 value when overwritten N = CM4 value when overwritten M < N (b) When TM4 > CM4 FFFFH TM4CAE0 TM4CE0...
Page 404: Control Register
CHAPTER 9 TIMER/COUNTER FUNCTION 9.5.4 Control register (1) Timer control register 4 (TMC4) The TMC4 register controls the operation of timer 4. This register can be read/written in 8-bit or 1-bit units. Caution The TM4CAE0 bit and other bits cannot be set at the same time. Be sure to set the TM4CAE0 bit and then set the other bits and the other registers of TM4.
Page 405: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION 9.5.5 Operation (1) Compare operation TM4 can be used for a compare operation in which the value that was set in a compare register (CM4) is compared with the TM4 count value. If a match is detected by the compare operation, an interrupt (INTCM4) is generated. The generation of the interrupt causes TM4 to be cleared (0) at the next count timing.
Page 406 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-104. TM4 Compare Operation Example (2/2) (b) When CM4 is set to 0 Count clock Count up TM4 clear Clear FFFFH Match detection (INTCM4) Overflow Interval time = (FFFFH + 2) × Count clock cycle Remark User’s Manual U14492EJ5V0UD...
Page 407: Application Example
CHAPTER 9 TIMER/COUNTER FUNCTION 9.5.6 Application example (1) Interval timer This section explains an example in which timer 4 is used as an interval timer with 16-bit precision. Interrupt requests (INTCM4) are output at equal intervals (refer to Figure 9-104 TM4 Compare Operation Example).
Page 408: Timer Connection Function
CHAPTER 9 TIMER/COUNTER FUNCTION 9.6 Timer Connection Function 9.6.1 Overview The V850E/IA1 provides a function to connect timer 1 and timer 2. Figure 9-105. Block Diagram of Timer Connection Function Timer connection selector Timer 2 Capture 0 CVSE10/ CVPE10 Capture 1 CVSE20/ CVPE20 Timer 1...
Page 409: Control Register
CHAPTER 9 TIMER/COUNTER FUNCTION 9.6.2 Control register (1) Timer connection selection register 0 (TMIC0) The TMIC0 register enables/disables input of the INTCM100, INTCM101 signals to the CVSEn0/CVPEn0 registers (n = 1, 2). This register can be read/written in 8-bit or 1-bit units. Address Initial value TMIC0...
Page 410: Chapter 10 Serial Interface Function
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.1 Features The serial interface function provides three types of serial interfaces combining a total of six transmit/receive channels. All six channels can be used simultaneously. The three interface formats are as follows. (1) Asynchronous serial interfaces (UART0 to UART2): 3 channels (2) Clocked serial interfaces (CSI0, CSI1): 2 channels (3) FCAN controller: 1 channel Remark...
Page 411: Asynchronous Serial Interface 0 (Uart0)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2 Asynchronous Serial Interface 0 (UART0) 10.2.1 Features • Transfer rate: 300 bps to 1562.5 Kbps (using a dedicated baud rate generator and an internal system clock of 50 MHz) • Full-duplex communications On-chip receive buffer register 0 (RXB0) On-chip transmit buffer register 0 (TXB0) •...
Page 412: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.2 Configuration UART0 is controlled by asynchronous serial interface mode register 0 (ASIM0), asynchronous serial interface status register 0 (ASIS0), and asynchronous serial interface transmit status register 0 (ASIF0). Receive data is maintained in receive buffer register 0 (RXB0), and transmit data is written to transmit buffer register 0 (TXB0). Figure 10-1 shows the configuration of asynchronous serial interface 0 (UART0).
Page 413 CHAPTER 10 SERIAL INTERFACE FUNCTION (8) Transmit buffer register 0 (TXB0) This is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to TXB0. (9) Addition of transmission control parity A transmit operation is controlled by adding a start bit, parity bit, or stop bit to the data that is written to the TXB0 register, according to the contents that were set in the ASIM0 register.
Page 414: Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.3 Control registers (1) Asynchronous serial interface mode register 0 (ASIM0) The ASIM0 register is an 8-bit register that controls the UART0 transfer operation. This register can be read/written in 8-bit or 1-bit units. Cautions 1. When using UART0, be sure to set the external pins related to the UART0 function to the control mode before setting clock selection register 0 (CKSR0) and baud rate generator control register 0 (BRGC0), and then set the UARTCAE0 bit to 1.
Page 415 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/3) Bit position Bit name Function RXE0 Enables/disables reception. Note 0: Disable reception 1: Enable reception Cautions 1. Set the RXE0 bit to 1 after setting the UARTCAE0 bit to 1 at startup. Set the UARTCAE0 bit to 0 after setting the RXE0 bit to 0 to stop.
Page 416 CHAPTER 10 SERIAL INTERFACE FUNCTION (3/3) Bit position Bit name Function • 0 parity 4, 3 PS1, PS0 During transmission, the parity bit is cleared (0) regardless of the transmit data. During reception, no parity error is generated because no parity bit is checked. •...
Page 417 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status register 0 (ASIS0) The ASIS0 register, which consists of 3-bit error flags (PE, FE, and OVE), indicates the error status when UART0 reception is completed. The ASIS0 register is cleared to 00H by a read operation. When a reception error occurs, receive buffer register 0 (RXB0) should be read and the error flag should be cleared after the ASIS0 register is read.
Page 418 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Asynchronous serial interface transmit status register 0 (ASIF0) The ASIF0 register, which consists of 2-bit status flags, indicates the status during transmission. By writing the next data to the TXB0 register after data is transferred from the TXB0 register to the transmit shift register, transmit operations can be performed continuously without suspension even during an interrupt interval.
Page 419 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Receive buffer register 0 (RXB0) The RXB0 register is an 8-bit buffer register for storing parallel data that had been converted by the receive shift register. When reception is enabled (RXE0 bit = 1 in the ASIM0 register), receive data is transferred from the receive shift register to the RXB0 register, synchronized with the completion of the shift-in processing of one frame.
Page 420 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Transmit buffer register 0 (TXB0) The TXB0 register is an 8-bit buffer register for setting transmit data. When transmission is enabled (TXE0 bit = 1 in the ASIM0 register), the transmit operation is started by writing data to TXB0 register.
Page 421: Interrupt Requests
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.4 Interrupt requests The following three types of interrupt requests are generated from UART0. • Reception completion interrupt (INTSR0) • Transmission completion interrupt (INTST0) • Reception error interrupt (INTSER0) The default priorities among these three types of interrupt requests is, from high to low, reception completion interrupt, transmission completion interrupt, and reception error interrupt.
Page 422: Operation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.5 Operation (1) Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 10-2. The character bit length within one data frame, the type of parity, and the stop bit length are specified according to the asynchronous serial interface mode register 0 (ASIM0).
Page 423 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Transmission operation When UARTCAE0 bit is set to 1 in the ASIM0 register, a high level is output from the TXD0 pin. Then, when TXE0 bit is set to 1 in the ASIM0 register, transmission is enabled, and the transmit operation is started by writing transmit data to transmit buffer register 0 (TXB0).
Page 424 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-3. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 Start TXD0 (output) Parity Stop INTST0 (output) (b) Stop bit length: 2 Stop Parity TXD0 (output) Start INTST0 (output) User’s Manual U14492EJ5V0UD...
Page 425 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Continuous transmission operation UART0 can write the next transmit data to the TXB0 register at the timing that the transmit shift register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during the servicing of the transmission completion interrupt (INTST0) after the transmission of one data frame.
Page 426 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-4. Continuous Transmission Processing Flow Set registers Write transmit data to TXB0 register When reading ASIF0 register, TXBF0 = 0? Write 2nd byte of the transmit data to TXB0 Interrupt occurrence register Required number of transfers performed? When reading When reading...
Page 427 CHAPTER 10 SERIAL INTERFACE FUNCTION (a) Starting procedure The procedure to start continuous transmission is shown below. Figure 10-5. Continuous Transmission Starting Procedure Start Start Stop Stop TXD0 (output) Data (1) Data (2) <1> <2> <3> <4> <5> INTST0 (output) TXB0 register Data (1) Data (2)
Page 428 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Ending procedure The procedure for ending continuous transmission is shown below. Figure 10-6. Continuous Transmission End Procedure Start Start Stop Stop TXD0 (output) Data (m − 1) Data (m) <6> <7> <8> <9> <10> <11>...
Page 429 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Reception operation An awaiting reception state is set by setting UARTCAE0 bit to 1 in the ASIM0 register and then setting RXE0 bit to 1 in the ASIM0 register. To start the receive operation, start sampling at the falling edge when the falling of the RXD0 pin is detected.
Page 430 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-7. Asynchronous Serial Interface Reception Completion Interrupt Timing Start RXD0 (input) Parity Stop INTSR0 (output) RXB0 register Cautions 1. Even if a reception error occurs, be sure to read receive buffer register 0 (RXB0). If the RXB0 register is not read, an overrun error will occur at the next data reception, and the reception error state will continue indefinitely.
Page 431 CHAPTER 10 SERIAL INTERFACE FUNCTION (a) Separation of reception error interrupt A reception error interrupt can be separated from the INTSR0 signal and generated as an INTSER0 signal by clearing the ISRM bit of the ASIM0 register to 0. Figure 10-8. When Reception Error Interrupt Is Separated from INTSR0 Interrupt (ISRM Bit = 0) (a) No error occurs during reception (b) An error occurs during reception INTSR0 signal (output)
Page 432 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at the transmission and reception sides. (a) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value “1”...
Page 433 CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Receive data noise filter The RXD0 signal is sampled at the rising edge of the prescaler output base clock (f ). If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see Figure 10-11).
Page 434: Dedicated Baud Rate Generator 0 (Brg0)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.6 Dedicated baud rate generator 0 (BRG0) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception at UART0. The dedicated baud rate generator output can be selected as the serial clock for each channel.
Page 435 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Serial clock generation A serial clock can be generated according to the settings of the CKSR0 and BRGC0 registers. The base clock to the 8-bit counter is selected according to the TPS3 to TPS0 bits of the CKSR0 register. The 8-bit counter divisor value can be set according to the MDL7 to MDL0 bits of the BRGC0 register.
Page 436 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Baud rate generator control register 0 (BRGC0) The BRGC0 register is an 8-bit register that controls the baud rate (serial transfer speed) of UART0. This register can be read/written in 8-bit units. Caution If the MDL7 to MDL0 bits are to be overwritten, the TXE0 bit and RXE0 bit of the ASIM0 register should be set to 0 first.
Page 437 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Baud rate The baud rate is the value obtained according to the following formula. Baud rate = [bps] 2 × k = Frequency [Hz] of base clock selected according to TPS3 to TPS0 bits of CKSR0 register k = Value set according to MDL7 to MDL0 bits of BRGC0 register (k = 8, 9, 10, ..., 255) (d) Baud rate error The baud rate error is obtained according to the following formula.
Page 438 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Baud rate setting example Table 10-3. Baud Rate Generator Setting Data = 50 MHz = 40 MHz = 33 MHz = 10 MHz Baud Rate (bps) 0.15 0.16 –0.07 0.16 0.15 0.16 –0.07 0.16 1200 0.15 0.16...
Page 439 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 440 CHAPTER 10 SERIAL INTERFACE FUNCTION Therefore, the transfer destination’s maximum baud rate (BRmax) that can be received is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. −...
Page 441: Precautions
CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of base clock longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit.
Page 442: Asynchronous Serial Interfaces 1, 2 (Uart1, Uart2)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3 Asynchronous Serial Interfaces 1, 2 (UART1, UART2) 10.3.1 Features • Clocked (synchronous) mode/asynchronous mode can be selected • Operation clock Synchronous mode: Baud rate generator/external clock selectable Asynchronous mode: Baud rate generator • Transfer rate 600 bps to 153,600 bps (in asynchronous mode, f = 50 MHz) 4,800 bps to 1,000,000 bps (in synchronous mode)
Page 443: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.2 Configuration UART1 and UART2 are controlled by asynchronous serial interface mode registers 10, 11, 20, and 21 (ASIM10, ASIM11, ASIM20, ASIM21) and asynchronous serial interface status registers 1 and 2 (ASIS1, ASIS2). Receive data is held in the receive buffer registers (RXB1, RXBL1, RXB2, RXBL2), and transmit data is held in the transmit shift registers (TXS1, TXSL1, TXS2, TXSL2).
Page 444 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-15. Block Diagram of Asynchronous Serial Interfaces 1, 2 Internal bus PEn FEn OVEn Asynchronous Asynchronous Receive buffers n, Ln serial interface mode serial interface status (RXBn, RXBLn) registers n0, n1 register n (ASIMn0, ASIMn1) (ASISn) Transmit Receive...
Page 445: Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.3 Control registers (1) Asynchronous serial interface mode registers 10, 20 (ASIM10, ASIM20) The ASIMn0 register is an 8-bit register that controls the UART1, UART2 transfer operation (n = 1, 2). This register can be read/written in 8-bit or 1-bit units. Cautions 1.
Page 446 CHAPTER 10 SERIAL INTERFACE FUNCTION <6> Address Initial value ASIM10 RXE1 SCLS FFFFFA28H <6> Address Initial value ASIM20 RXE2 SCLS FFFFFA48H Bit position Bit name Function RXEn Enables/disables reception. 0: Disable reception 1: Enable reception 5, 4 PS1, PS0 Specifies parity bit length. Operation No parity, extension bit operation 0 parity...
Page 447 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface mode registers 11, 21 (ASIM11, ASIM21) The ASIMn1 register is an 8-bit register that controls the UART1 and UART2 transfer modes. This register can be read/written in 8-bit or 1-bit units. Address Initial value ASIM11...
Page 448 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Asynchronous serial interface status registers 1, 2 (ASIS1, ASIS2) The ASISn register is a register that is configured of a UARTn transmission status flag (SOTn), reception status flag (SIRn), a bit (RB8) indicating the 9th bit when extension bit addition is enabled, and 3-bit error flags (PEn, FEn, OVEn) that indicate the error status at reception end (n = 1, 2).
Page 449 CHAPTER 10 SERIAL INTERFACE FUNCTION <7> <6> <2> <1> <0> Address Initial value ASIS1 SOT1 SIR1 OVE1 FFFFFA2CH <7> <6> <2> <1> <0> Address Initial value ASIS2 SOT2 SIR2 OVE2 FFFFFA4CH Bit position Bit name Function Status flag indicating transmission status SOTn 0: Transmission end timing (when INTSTn is generated) Note...
Page 450 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) 2-frame continuous reception buffer registers 1, 2 (RXB1, RXB2)/receive buffer registers L1, L2 (RXBL1, RXBL2) The RXBn register is a 16-bit buffer register that holds receive data (during 2-frame continuous reception (UMSR bit of ASIMn1 register = 1), during 9-bit extended data reception (EBS bit of ASIMn1 register = 1)) (n = 1, 2).
Page 451 CHAPTER 10 SERIAL INTERFACE FUNCTION [2-frame continuous reception buffer register 1] Address Initial value RXB1 RXB15 RXB14 RXB13 RXB12 RXB11 RXB10 RXB9 RXB8 RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 FFFFFA20H Undefined [Receive buffer register L1] Address Initial value RXBL1 RXB7 RXB6...
Page 452 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Cautions <1> Operation upon occurrence of overrun error during 2-frame continuous reception • During normal reception Reception completion interrupt (INTSRn) generated upon end of reception of 2nd frame, no error RXDn Frame 1 Frame 2 •...
Page 453 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) 2-frame continuous transmission shift registers 1, 2 (TXS1, TXS2)/transmit shift registers L1, L2 (TXSL1, TXSL2) The TXSn register is a 9-bit/2-frame continuous transmission processing shift register (n = 1, 2). Transmission is started by writing data to this register. A transmission completion interrupt request (INTSTn) is generated in synchronization with the end of transmission of 1 frame or 2 frames including the TXSn data.
Page 454: Interrupt Requests
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.4 Interrupt requests The following two types of interrupt request are generated from UARTn (n = 1, 2). • Reception completion interrupt (INTSRn) • Transmission completion interrupt (INTSTn) The reception completion interrupt has higher default priority than the transmission completion interrupt. Table 10-5.
Page 455: Operation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.5 Operation (1) Data format Full-duplex serial data is transmitted and received. Figure 10-16 shows the format of transmit/receive data. One data frame consists of a start bit, character bits, a parity bit, and a stop bit(s). When 2 data frame transfer is set, both frames have the above-described format.
Page 456 CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-6. ASIMn0, ASIMn1 Register Settings and Data Format ASIMn0, ASIMn1 Register Settings Data Format CL Bit PS1 Bit PS0 Bit SL Bit EBS Bit D0 to D6    DATA Stop bit  ...
Page 457 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Transmission operation The transmission operation is started by writing data to 2-frame continuous transmission shift registers 1, 2 (TXS1, TXS2)/transmit shift registers L1, L2 (TXSL1, TXSL2). Following data write, the start bit is transmitted from the next shift timing. Since the UARTn does not have a CTS (transmission enable signal) input pin, use a port when the other party confirms the reception enabled status (n = 1, 2).
Page 458 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-17. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) When stop bit length = 1 bit TXDn (output) Start Parity Stop INTSTn interrupt Flag in transmission (SOTn) (b) When stop bit length = 2 bits TXDn (output) Start Parity...
Page 459 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Continuous transmission of 3 or more frames In addition to the 1-frame/2-frame transmission function, UARTn also enables continuous transmission of 3 or more frames, using the method shown below (n = 1, 2). (a) How to continuously transmit 3 or more frames (when the stop bit is 1 bit (SL bit = 0)) Three frames can be continuously transmitted by writing transmit data to the TXSn/TXSLn register in the period between the generation of the transmission completion interrupt request (INTSTn) and 4 ×...
Page 460 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Reception operation The reception wait status is entered by setting the RXEn bit of the ASIMn0 register to 1 (n = 1, 2). To start the reception operation, first perform start bit detection. Start bit detection is done by performing sampling of the RXDn pin.
Page 461 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Reception completion interrupt request When reception of one frame of data has been completed (stop bit detection) when the RXEn bit of the ASIMn0 register = 1, the receive data in the shift register is transferred to RXBn/RXBLn and a reception completion interrupt request (INTSRn) is generated after 1 frame or 2 frames of data have been transferred to RXBn/RXBLn.
Page 462 CHAPTER 10 SERIAL INTERFACE FUNCTION Cautions 1. Even if a reception error occurs, be sure to read 2-frame continuous reception buffer register n (RXBn)/receive buffer register n (RXBLn). If the RXBn or RXBLn register is not read, an overrun error will occur at the next data reception, and the reception error state will continue indefinitely.
Page 463 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Odd parity <1> During transmission In contrast to even parity, the parity bit is controlled so that the number of bits with the value “1” within the transmit data including the parity bit is odd. The parity bit value is as follows. •...
Page 464: Synchronous Mode
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.6 Synchronous mode The synchronous mode can be set with the ASCKn pin, which is the serial clock I/O pin (n = 1, 2). The synchronous mode is set with the MOD bit of the ASIMn1 register, and the serial clock to be used for synchronization is selected with the SCLS bit of the ASIMn0 register.
Page 465 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Transmission/Reception Timing Chart for Synchronous Mode (1/3) (a) In 1-frame transmission/reception mode Serial clock Transmit data Stop bit Transmission register write signal Flag in transmission (SOTn) Transmission completion interrupt (INTSTn) Flag in reception (SIRn) Reception completion interrupt...
Page 466 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Transmission/Reception Timing Chart for Synchronous Mode (2/3) (b) In 2-frame continuous transmission/reception mode Serial clock Transmit data Stop bit Stop bit Transmission register write signal Flag in transmission (SOTn) Transmission completion interrupt (INTSTn) Flag in reception (SIRn) Reception...
Page 467 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Transmission/Reception Timing Chart for Synchronous Mode (3/3) (c) Transmission/reception timing and transmit data timing during serial clock output Serial clock (output) System clock Transmit data Transmission timing Reception timing Note Note The transmit data is delayed by 1 system clock in relation to the serial clock. (d) Transmission/reception timing and transmit data timing using external serial clock External serial clock System clock...
Page 468 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Reception Completion Interrupt and Error Interrupt Generation Timing During Synchronous Mode Reception (a) During normal operation (in 1-frame reception mode) Receive data START STOP Flag in reception (SIRn) Reception completion interrupt (INTSRn) Error interrupt (b) In 2-frame continuous reception mode Receive data START...
Page 469: Dedicated Baud Rate Generators 1, 2 (Brg1, Brg2)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.7 Dedicated baud rate generators 1, 2 (BRG1, BRG2) (1) Configuration of baud rate generators 1, 2 (BRG1, BRG2) For UART1 and UART2, the serial clock can be selected from the dedicated baud rate generator output or internal system clock (f ) for each channel.
Page 470 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Dedicated baud rate generators 1, 2 (BRG1, BRG2) BRGn is configured of an 8-bit timer counter for baud rate signal generation, a prescaler mode register that controls the generation of the baud rate signal (PRSMn), a prescaler compare register that sets the value of the 8-bit timer counter (PRSCMn), and a prescaler (n = 1, 2).
Page 471 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Prescaler compare registers 1, 2 (PRSCM1, PRSCM2) PRSCMn is an 8-bit compare register that sets the value of the 8-bit timer counter (n = 1, 2). These registers can be read/written in 8-bit units. Cautions 1.
Page 472 CHAPTER 10 SERIAL INTERFACE FUNCTION (f) Baud rate setting value The formulas for calculating the baud rate in the asynchronous mode and the synchronous mode and the formula for calculating the error are as follows. <1> Formula for calculating baud rate in asynchronous mode Baud rate = [bps] 2 ×...
Page 473 CHAPTER 10 SERIAL INTERFACE FUNCTION <4> Baud rate setting example In an actual system, the output of a prescaler module, etc. is connected to input clock. Table 10-8 shows the baud rate generator setting data at this time. Table 10-8. Baud Rate Generator Setting Data (BRG = f /2) (1/2) (a) When f = 32 MHz...
Page 474 CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-8. Baud Rate Generator Setting Data (BRG = f /2) (2/2) (c) When f = 50 MHz Target Baud Rate Actual Baud Rate BGCSm Bit PRSCMn Error (m = 0, 1) Register Setting Synchronous Asynchronous Synchronous Asynchronous...
Page 475 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 476 CHAPTER 10 SERIAL INTERFACE FUNCTION Therefore, the transfer destination’s maximum receivable baud rate (BRmax) is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. − × × −...
Page 477: Clocked Serial Interfaces 0, 1 (Csi0, Csi1)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4 Clocked Serial Interfaces 0, 1 (CSI0, CSI1) 10.4.1 Features • High-speed transfer: Maximum 5 Mbps • Half-duplex communications • Master mode or slave mode can be selected • Transmission data length: 8 bits or 16 bits can be set •...
Page 478 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Clocked serial interface receive buffer registers 0, 1 (SIRB0, SIRB1) The SIRBn register is a 16-bit buffer register that stores receive data. (6) Clocked serial interface receive buffer registers L0, L1 (SIRBL0, SIRBL1) The SIRBLn register is an 8-bit buffer register that stores receive data. (7) Clocked serial interface read-only receive buffer registers 0, 1 (SIRBE0, SIRBE1) The SIRBEn register is a 16-bit buffer register that stores receive data.
Page 479: Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-25. Block Diagram of Clocked Serial Interface Serial clock controller SCKn Clock start/stop control Selector & clock phase control Interrupt INTCSIn controller BRG3 SCKn Transmission control Transmission data control Control signal Initial transmit SO selection buffer register (SOTBFn/SOTBFLn) Transmit...
Page 480 CHAPTER 10 SERIAL INTERFACE FUNCTION <7> <6> <4> <0> Address Initial value CSIM0 CSICAE0 TRMD0 DIR0 CSIT AUTO CSOT0 FFFFF900H <7> <6> <4> <0> Address Initial value CSICAE1 TRMD1 DIR1 CSIT AUTO CSOT1 CSIM1 FFFFF910H Bit position Bit name Function CSICAEn Enables/disables CSIn operation.
Page 481 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1) The CSICn register is an 8-bit register that controls the CSIn transfer operation (n = 0, 1). These registers can be read/written in 8-bit or 1-bit units. Caution The CSICn register can be overwritten only when the CSICAEn bit of the CSIMn register = 0.
Page 482 CHAPTER 10 SERIAL INTERFACE FUNCTION Address Initial value CSIC0 CKS2 CKS1 CKS0 FFFFF901H Address Initial value CSIC1 CKS2 CKS1 CKS0 FFFFF911H Bit position Bit name Function 4, 3 CKP, DAP Specifies operation mode. Operation mode SCKn (I/O) SOn (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIn (input) SCKn (I/O) SOn (output)
Page 483 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Clocked serial interface receive buffer registers 0, 1 (SIRB0, SIRB1) The SIRBn register is a 16-bit buffer register that stores receive data (n = 0, 1). When the receive-only mode is set (TRMDn bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBn register.
Page 484 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Clocked serial interface receive buffer registers L0, L1 (SIRBL0, SIRBL1) The SIRBLn register is an 8-bit buffer register that stores receive data (n = 0, 1). When the receive-only mode is set (TRMDn bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBLn register.
Page 485 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Clocked serial interface read-only receive buffer registers 0, 1 (SIRBE0, SIRBE1) The SIRBEn register is a 16-bit buffer register that stores receive data (n = 0, 1). These registers are read-only, in 16-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSICAEn bit of the CSIMn register.
Page 486 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Clocked serial interface read-only receive buffer registers L0, L1 (SIRBEL0, SIRBEL1) The SIRBELn register is an 8-bit buffer register that stores receive data (n = 0, 1). These registers are read-only, in 8-bit or 1-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSICAEn bit of the CSIMn register.
Page 487 CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Clocked serial interface transmit buffer registers 0, 1 (SOTB0, SOTB1) The SOTBn register is a 16-bit buffer register that stores transmit data (n = 0, 1). When the transmission/reception mode is set (TRMDn bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBn register.
Page 488 CHAPTER 10 SERIAL INTERFACE FUNCTION (8) Clocked serial interface transmit buffer registers L0, L1 (SOTBL0, SOTBL1) The SOTBLn register is an 8-bit buffer register that stores transmit data (n = 0, 1). When the transmission/reception mode is set (TRMDn bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBLn register.
Page 489 CHAPTER 10 SERIAL INTERFACE FUNCTION (9) Clocked serial interface initial transmit buffer registers 0, 1 (SOTBF0, SOTBF1) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFn register. These registers can be read/written in 16-bit units.
Page 490 CHAPTER 10 SERIAL INTERFACE FUNCTION (10) Clocked serial interface initial transmit buffer registers L0, L1 (SOTBFL0, SOTBFL1) The SOTBFLn register is an 8-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFLn register. These registers can be read/written in 8-bit or 1-bit units.
Page 491 CHAPTER 10 SERIAL INTERFACE FUNCTION (11) Serial I/O shift registers 0, 1 (SIO0, SIO1) The SIOn register is a 16-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOn register is read. These registers are read-only, in 16-bit units.
Page 492 CHAPTER 10 SERIAL INTERFACE FUNCTION (12) Serial I/O shift registers L0, L1 (SIOL0, SIOL1) The SIOLn register is an 8-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOLn register is read. These registers are read-only, in 8-bit or 1-bit units.
Page 493: Operation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.4 Operation (1) Single transfer mode (a) Usage Note 1 In the receive-only mode (TRMDn bit of CSIMn register = 0), transfer is started by reading the receive data buffer register (SIRBn/SIRBLn) (n = 0, 1). Note 2 In the transmission/reception mode (TRMDn bit of CSIMn register = 1), transfer is started by writing to the transmit data buffer register (SOTBn/SOTBLn).
Page 494 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-26. Timing Chart in Single Transfer Mode (1/2) (a) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKP bit = 0, DAP bit = 0 SCKn (I/O) (55H)
Page 495 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-26. Timing Chart in Single Transfer Mode (2/2) (b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKP bit = 0, DAP bit = 1 SCKn (I/O) (55H)
Page 496 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Clock phase selection The following shows the timing when changing the conditions for clock phase selection (CKP bit of CSICn register) and data phase selection (DAP bit of CSICn register) under the following conditions. •...
Page 497 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-27. Timing Chart According to Clock Phase Selection (2/2) (c) When CKP bit = 0, DAP bit = 1 SCKn (I/O) SIn (input) SOn (output) DO6 DO5 DO4 DO3 DO2 DO1 Reg_R/W INTCSIn interrupt CSOTn bit (d) When CKP bit = 1, DAP bit = 1 SCKn (I/O)
Page 498 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Transmission/reception completion interrupt request signals (INTCSI0, INTCSI1) INTCSIn is set (1) upon completion of data transmission/reception. Caution The delay mode (CSIT bit = 1) is valid only in the master mode (bits CKS2 to CKS0 of the CSICn register are not 111B).
Page 499 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-28. Timing Chart of Interrupt Request Signal Output in Delay Mode (2/2) (b) When CKP bit = 1, DAP bit = 1 Input clock SCKn (I/O) SIn (input) SOn (output) Reg_R/W INTCSIn interrupt CSOTn bit Delay Remarks 1.
Page 500 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Repeat transfer mode (a) Usage (receive-only) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the receive-only mode (TRMDn bit of CSIMn register = 0). <2> Read SIRBn register (start transfer with dummy read). <3>...
Page 501 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-29. Repeat Transfer (Receive-Only) Timing Chart SCKn (I/O) SIn (input) din-1 din-2 din-3 din-4 din-5 SIOLn din-5 register SIRBLn din-1 din-2 din-3 din-4 register SIRBEn (d4) Reg_RD SIRBn (dummy) SIRBn (d1) SIRBn (d2) SIRBn (d3) SIOn (d5) CSOTn bit INTCSIn...
Page 502 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Usage (transmission/reception) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the transmission/reception mode (TRMDn bit of CSIMn register = 1). <2> Write the first data to the SOTBFn register. <3>...
Page 503 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-30. Repeat Transfer (Transmission/Reception) Timing Chart SCKn (I/O) SOn (output) dout-1 dout-2 dout-3 dout-4 dout-5 din-1 din-2 din-3 din-4 din-5 SIn (input) SOTBFLn dout-1 register SOTBLn dout-2 dout-3 dout-4 dout-5 register SIOLn din-5 register SIRBLn din-1 din-2...
Page 504 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Next transfer reservation period In the repeat transfer mode, the next transfer must be prepared with the period shown in Figure 10-31. Figure 10-31. Timing Chart of Next Transfer Reservation Period (1/2) (a) When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 0 SCKn (I/O) INTCSIn...
Page 505 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-31. Timing Chart of Next Transfer Reservation Period (2/2) (c) When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 1 SCKn (I/O) INTCSIn interrupt Reservation period: 6.5 SCKn cycles (d) When data length: 16 bits, operation mode: CKP bit = 0, DAP bit = 1 SCKn (I/O)
Page 506 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Cautions To continue repeat transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is over, the following occurs.
Page 507 CHAPTER 10 SERIAL INTERFACE FUNCTION (ii) In case of contention between interrupt request and register access Since continuous transfer has stopped once, executed as a new repeat transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 10-33). In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal data is sent.
Page 508: Output Pins
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.5 Output pins (1) SCKn pin When the CSIn operation is disabled (CSICAEn bit of CSIMn register = 0), the SCKn pin output status is as follows (n = 0, 1). Table 10-9. SCKn Pin Output Status CKS2 CKS1 CKS0...
Page 509: Dedicated Baud Rate Generator 3 (Brg3)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.6 Dedicated baud rate generator 3 (BRG3) (1) Configuration of baud rate generator 3 (BRG3) The CSI0 and CSI1 serial clocks can be selected from the dedicated baud rate generator output or internal system clock (f The serial clock source is specified with registers CSIC0 and CSIC1.
Page 510 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Dedicated baud rate generator 3 (BRG3) BRG3 is configured of an 8-bit timer counter that generates the baud rate signal, a prescaler mode register 3 (PRSM3) that controls baud rate signal generation, a prescaler compare register 3 (PRSCM3) that sets the value of the 8-bit timer counter, and a prescaler.
Page 511 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Prescaler compare register 3 (PRSCM3) PRSCM3 is an 8-bit compare register that sets the value of the 8-bit timer counter. This register can be read/written in 8-bit units. Cautions 1. The internal timer counter is cleared by writing to the PRSM3 register. Therefore, do not write to the PRSCM3 register during transmission.
Page 512 CHAPTER 10 SERIAL INTERFACE FUNCTION (e) Baud rate setting value Table 10-11. Baud Rate Generator Setting Data (a) When f = 32 MHz BGCS1 BGCS0 PRSCM Register Value Clock (Hz) 4000000 2000000 1000000 500000 250000 100000 50000 25000 10000 5000 (b) When f = 40 MHz BGCS1...
Page 513: Chapter 11 Fcan Controller
CHAPTER 11 FCAN CONTROLLER The V850E/IA1 features a 1 channel on-chip FCAN (Full Controller Area Network) controller that complies with the CAN specification Ver. 2.0, PartB active. 11.1 Function Overview Table 11-1 presents an overview of V850E/IA1 functions. Table 11-1. Overview of Functions Function Description Protocol...
Page 514: Configuration
11.2 Configuration FCAN is composed of the following four blocks. (1) NPB interface This functional block provides an NPB (NEC peripheral I/O bus) interface as a means of transmitting and receiving signals. (2) MAC (Memory Access Controller) This functional block controls access to the CAN module and to the CAN RAM within the FCAN.
Page 515 CHAPTER 11 FCAN CONTROLLER Figure 11-1. Block Diagram of FCAN Interrupt request INTCREC CAN bus (NEC peripheral I/O bus) INTCTRX INTCERR INTCMAC FCAN controller CAN_H CTXD (Memory Access Controller) module interface transceiver CAN_L CRXD CAN RAM Message CMASK0 buffer 0...
Page 516: Configuration Of Messages And Buffers
CHAPTER 11 FCAN CONTROLLER 11.3 Configuration of Messages and Buffers Table 11-2. Configuration of Messages and Buffers Note Note Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) Register Name xxxxm800H to xxxxm81FH Message buffer 0 field xxxxmA00H to xxxxmA1FH Message buffer 16 field...
Page 517: Time Stamp Function
CHAPTER 11 FCAN CONTROLLER 11.4 Time Stamp Function The FCAN controller supports a time stamp function. This function is needed to build a global time system. The time stamp function is implemented using a 16-bit free-running time stamp counter. Two types of time stamp function can be selected for message reception in the FCAN controller. Use bit 3 (TMR) of the CAN1 control register (C1CTRL) to set the desired time stamp function.
Page 518 CHAPTER 11 FCAN CONTROLLER Figure 11-3. Time Stamp Function Setting for Message Reception (When C1CTRL Register’s TMR Bit = 1) ACK field Message CAN message buffer n <1> Time stamp M_TIMEn counter <Explanation> <1> When the EOF is detected on the CAN bus (a valid message is acknowledged), the captured time stamp counter value is copied to the M_TIMEn register in CAN message buffer n when a message is stored in CAN message buffer n.
Page 519 CHAPTER 11 FCAN CONTROLLER Figure 11-4. Time Stamp Function Setting for Message Transmission (When M_CTRL Register’s ATS Bit = 1) ACK field Message <2> <1> Time stamp Temporary counter buffer <Explanation> <1> The time stamp counter value is captured to the temporary buffer when the SOF is detected on the CAN bus. Note <2>...
Page 520: Message Processing
CHAPTER 11 FCAN CONTROLLER 11.5 Message Processing A modular system is used for the FCAN controller. Consequently, messages can be placed at any location within the message area. The messages can be linked to mask functions that are in turn linked to CAN modules. 11.5.1 Message transmission The FCAN system is a multiplexed communication system.
Page 521 CHAPTER 11 FCAN CONTROLLER Figure 11-5. Message Processing Example (When PBB Bit = 0) Message No. Message waiting to be transmitted ID = 120H ID = 229H CAN module transmits messages in the following sequence. 1. Message 6 2. Message 1 3.
Page 522: Message Reception
CHAPTER 11 FCAN CONTROLLER 11.5.2 Message reception When two or more message buffers of the CAN module receive a message, the storage priority of the received messages is as follows (the storage priority differs between data frames and remote frames). Table 11-4.
Page 523: Mask Function
CHAPTER 11 FCAN CONTROLLER 11.6 Mask Function A mask linkage function can be defined for each received message. This means that there is no need to distinguish between local masks and global masks. When the mask function is used, the received message’s identifier is compared with the message buffer’s identifier and the message can be stored in the defined message buffer regardless of whether the mask sets “0”...
Page 524 CHAPTER 11 FCAN CONTROLLER <3> Mask setting for mask 1 (example) (Using CAN1 address mask 1 registers L and H (C1MASKL1 and C1MASKH1)) CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9...
Page 525: Protocol
CHAPTER 11 FCAN CONTROLLER 11.7 Protocol FCAN is a high-speed multiplex communication protocol designed to enable real-time communications in automotive applications. The CAN specification is generally divided into two layers (physical layer and data link layer). The data link layer is further divided into logical link control and medium access control. The composition of these layers is illustrated below.
Page 526: Message Formats
CHAPTER 11 FCAN CONTROLLER 11.7.2 Message formats Four types of frames are used in CAN protocol messages. The output conditions for each type of frame are as follows. • Data frame: Frame used for transmit data • Remote frame: Frame used for transmit requests from receiving side •...
Page 527 CHAPTER 11 FCAN CONTROLLER <2> Remote frame A remote frame is transmitted when the receiving node issues a transmit request. A remote frame is similar to a data frame, except that the “data field” is deleted and the RTR bit of the “arbitration field”...
Page 528 CHAPTER 11 FCAN CONTROLLER <2> Arbitration field The arbitration field is used to set the priority, data frame or remote frame, and protocol mode. This field includes an identifier, frame setting (RTR bit), and protocol mode setting bit. Figure 11-11. Arbitration Field (In Standard Format Mode) Arbitration field (Control field) Identifier...
Page 529 CHAPTER 11 FCAN CONTROLLER <3> Control field The control field sets “N” as the number of data bytes in the data field (N = 0 to 8). r1 and r0 are fixed as dominant (D). The data length code bits (DLC3 to DLC0) set the byte count. Remark DLC3 to DLC0: Bits 3 to 0 in CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) (see 11.10 (2))
Page 530 CHAPTER 11 FCAN CONTROLLER <4> Data field The data field contains the amount of data set by the control field. Up to 8 units of data can be set. Remark Data units in the data field are each 8 bits long and are ordered MSB first. Figure 11-14.
Page 531 CHAPTER 11 FCAN CONTROLLER <6> ACK field The ACK field is used to confirm normal reception. It includes a 1-bit ACK slot and a 1-bit ACK delimiter. Figure 11-16. ACK Field (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit)
Page 532 CHAPTER 11 FCAN CONTROLLER <8> Interframe space The interframe space is inserted after the data frame, remote frame, error frame, and overload frame to separate one frame from the next one. • Error active node When the bus is idle, transmit enable mode is set for each node. Transmission then starts from a node that has received a transmit request.
Page 533 CHAPTER 11 FCAN CONTROLLER Table 11-10. Operation When Third Bit of Intermission Is “Dominant (D)” Transmit Status Operation No pending transmissions Receive operation is performed when start of frame output by other node is detected. Pending transmission exists Identifier is transmitted when start of frame output by local node is detected.
Page 534 CHAPTER 11 FCAN CONTROLLER <10> Overload frame An overload frame is output starting from the first bit in an intermission in cases where the receiving node is not yet ready to receive. If a bit error is detected in intermission mode, it is output starting from the bit following the bit where the bit error was detected.
Page 535: Functions
CHAPTER 11 FCAN CONTROLLER 11.8 Functions 11.8.1 Determination of bus priority (1) When one node has started transmitting • In bus idle mode, the node that outputs data first starts transmission. (2) When several nodes have started transmitting • The node that has the longest string of consecutive “dominant (D)” bits starting from the first bit in the arbitration field has top priority for bus access (“dominant (D)”...
Page 536: Can Sleep Mode/Can Stop Mode Function
CHAPTER 11 FCAN CONTROLLER 11.8.5 CAN sleep mode/CAN stop mode function The CAN sleep mode/CAN stop mode function is able to set the FCAN controller to sleep (standby) mode to reduce power consumption. The CAN sleep mode is set via the procedure stipulated in the CAN specification. The CAN sleep mode can be set to wake up by the bus operation, however the CAN stop mode cannot be set to wake up by the bus operation (this is controlled via CPU access).
Page 537 CHAPTER 11 FCAN CONTROLLER (4) Error statuses (a) Types of error statuses The three types of error statuses are listed below. Error active Error passive Bus off • Error status is controlled by the transmit error counter and receive error counter (see 11.10 (23) CAN1 error count register (C1ERC)).
Page 538 CHAPTER 11 FCAN CONTROLLER (b) Error counter The error counter value is incremented each time an error occurs and is decremented when a transmit or receive operation ends normally. The count-up/count-down timing occurs at the first bit of the error delimiter.
Page 539: Baud Rate Control Function
CHAPTER 11 FCAN CONTROLLER 11.8.7 Baud rate control function (1) Prescaler The FCAN controller of the V850E/IA1 includes a prescaler for dividing the clock supplied to the CAN (f MEM1 This prescaler generates a clock (f ) that is based on a division ratio ranging from 2 to 128 applied to the CAN base clock (f ) when the C1BRP register’s TLM bit = 0 and based on a division ratio ranging from 2 to 256 applied to the CAN base clock (f...
Page 540 CHAPTER 11 FCAN CONTROLLER (3) Data bit synchronization • Since the receiving node has no synchronization signal, synchronization is performed using level changes that occur on the bus. • As for the transmitting node, data is transmitted in sync with the transmitting node’s bit timing. (a) Hardware synchronization This is bit synchronization that is performed when the receiving node has detected a start of frame in bus idle mode.
Page 541 CHAPTER 11 FCAN CONTROLLER (b) Resynchronization Resynchronization is performed when a level change is detected on the bus (only when the previous sampling is at the recessive level) during a receive operation. • The edge’s phase error is produced by the relative positions of the detected edge and sync segment. <Phase error symbols>...
Page 542: Cautions On Bit Set/Clear Function
CHAPTER 11 FCAN CONTROLLER 11.9 Cautions on Bit Set/Clear Function The FCAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written to directly, so do not directly write (via bit manipulation, read/modify/write, or direct writing of target values) values to them.
Page 543 CHAPTER 11 FCAN CONTROLLER Figure 11-25. 16-Bit Data During Write Operation set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n Bit n status after bit set/clear operation...
Page 544: Control Registers
CHAPTER 11 FCAN CONTROLLER 11.10 Control Registers (1) FCAN clock selection register (PRM04) The PRM04 register is used to select the clock (f ) supplied to CAN1. MEM1 The clock is selected according to the clock frequency. This register can be read/written in 8-bit or 1-bit units. Caution Set this register before using FCAN.
Page 545 CHAPTER 11 FCAN CONTROLLER (2) CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) The M_DLCn register sets the byte count in the data field of CAN message buffer n (n = 00 to 31). When receiving, the receive data field’s byte count is set (to 1). These registers can be read/written in 8-bit units.
Page 546 CHAPTER 11 FCAN CONTROLLER Table 11-17. Addresses of M_DLCn (n = 00 to 31) Note Note Register Name Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) M_DLC00 xxxxm804H M_DLC16 xxxxmA04H M_DLC01 xxxxm824H M_DLC17 xxxxmA24H M_DLC02...
Page 547 CHAPTER 11 FCAN CONTROLLER (3) CAN message control registers 00 to 31 (M_CTRL00 to M_CTRL31) The M_CTRLn register is used to set the frame format of the data field in messages stored in CAN message buffer n (n = 00 to 31). These registers can be read/written in 8-bit units.
Page 548 CHAPTER 11 FCAN CONTROLLER (2/2) Bit position Bit name Function Specifies whether or not to add a time stamp when transmitting. 0: Time stamp not added when transmitting 1: Time stamp added when transmitting Cautions 1. The ATS bit is used only for transmit messages. 2.
Page 549 CHAPTER 11 FCAN CONTROLLER Table 11-18. Addresses of M_CTRLn (n = 00 to 31) Note Note Register Name Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) M_CTRL00 xxxxm805H M_CTRL16 xxxxmA05H M_CTRL01 xxxxm825H M_CTRL17 xxxxmA25H M_CTRL02...
Page 550 CHAPTER 11 FCAN CONTROLLER (4) CAN message time stamp registers 00 to 31 (M_TIME00 to M_TIME31) The M_TIMEn register is the register where the time stamp counter value is written upon completion of data reception (n = 00 to 31). These registers can be read/written in 16-bit units.
Page 551 CHAPTER 11 FCAN CONTROLLER (5) CAN message data registers n0 to n7 (M_DATAn0 to M_DATAn7) (n = 00 to 31) The M_DATAnx registers are areas where up to 8 bytes of transmit or receive data is stored (n = 00 to 31, x = 0 to 7).
Page 552 CHAPTER 11 FCAN CONTROLLER Table 11-20. Addresses of M_DATAnx (n = 00 to 31, x = 0 to 7) Register Note Note Note Note Note Note Note Note M_DATAn0 M_DATAn1 M_DATAn2 M_DATAn3 M_DATAn4 M_DATAn5 M_DATAn6 M_DATAn7 Name (m = 2, 6, A, E) (m = 2, 6, A, E) (m = 2, 6, A, E) (m = 2, 6, A, E)
Page 553 CHAPTER 11 FCAN CONTROLLER (6) CAN message ID registers L00 to L31 and H00 to H31 (M_IDL00 to M_IDL31 and M_IDH00 to M_IDH31) The M_IDLn and M_IDHn registers are areas used to set identifiers (n = 00 to 31). These registers can be read/written in 16-bit units. When in standard format mode, any data can be stored in the following areas.
Page 554 CHAPTER 11 FCAN CONTROLLER Table 11-21. Addresses of M_IDLn (n = 00 to 31) Note Note Register Name Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) M_IDL00 xxxxm810H M_IDL16 xxxxmA10H M_IDL01 xxxxm830H M_IDL17 xxxxmA30H M_IDL02...
Page 555 CHAPTER 11 FCAN CONTROLLER (7) CAN message configuration registers 00 to 31 (M_CONF00 to M_CONF31) The M_CONFn register is used to set the message buffer type and mask (n = 00 to 31). These registers can be read/written in 8-bit units. Address Initial value M_CONFn...
Page 556 CHAPTER 11 FCAN CONTROLLER Table 11-23. Addresses of M_CONFn (n = 00 to 31) Note Note Register Name Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) M_CONF00 xxxxm814H M_CONF16 xxxxmA14H M_CONF01 xxxxm834H M_CONF17 xxxxmA34H M_CONF02...
Page 557 CHAPTER 11 FCAN CONTROLLER (8) CAN message status registers 00 to 31 (M_STAT00 to M_STAT31) The M_STATn register indicates the transmit/receive status information of each message buffer (n = 00 to 31). These registers are read-only, in 8-bit units. Cautions 1. Writing directly to M_STATn register cannot be performed. Writing must be performed using CAN status set/clear register n (SC_STATn).
Page 558 CHAPTER 11 FCAN CONTROLLER Table 11-24. Addresses of M_STATn (n = 00 to 31) Note Note Register Name Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) M_STAT00 xxxxm815H M_STAT16 xxxxmA15H M_STAT01 xxxxm835H M_STAT17 xxxxmA35H M_STAT02...
Page 559 CHAPTER 11 FCAN CONTROLLER (9) CAN status set/clear registers 00 to 31 (SC_STAT00 to SC_STAT31) The SC_STATn register is used to set/clear the transmit/receive status information (n = 00 to 31). These registers are write-only, in 16-bit units. Address Initial value SC_STATn clear clear...
Page 560 CHAPTER 11 FCAN CONTROLLER Table 11-25. Addresses of SC_STATn (n = 00 to 31) Note Note Register Name Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) SC_STAT00 xxxxm816H SC_STAT16 xxxxmA16H SC_STAT01 xxxxm836H SC_STAT17 xxxxmA36H SC_STAT02...
Page 561 CHAPTER 11 FCAN CONTROLLER (10) CAN interrupt pending register (CCINTP) The CCINTP register is used to confirm the pending status of various interrupts. This register is read-only, in 16-bit units. Address Initial value Note 1 CAN1 CAN1 CAN1 xxxxmC00H 0000H CCINTP INTMAC Bit position...
Page 562 CHAPTER 11 FCAN CONTROLLER (11) CAN global interrupt pending register (CGINTP) The CGINTP register is used to confirm the pending status of MAC error interrupts. This register can be read/written in 8-bit units. Cautions 1. When “1” is written to a bit in the CGINTP register, that bit is cleared (to 0). When “0” is written to it, the bit’s value does not change.
Page 563 CHAPTER 11 FCAN CONTROLLER (12) CAN1 interrupt pending register (C1INTP) The C1INTP register is used to confirm the pending status of interrupts issued to FCAN. This register can be read/written in 8-bit units. Cautions 1. When “1” is written to a bit in the C1INTP register, that bit is cleared (to 0). When “0” is written to it, the bit’s value does not change.
Page 564 CHAPTER 11 FCAN CONTROLLER (13) CAN stop register (CSTOP) The CSTOP register controls clock supply to the entire CAN system. This register can be read/written in 16-bit units. Cautions 1. Be sure to set the CSTP bit (to 1) if the FCAN function will not be used. 2.
Page 565 CHAPTER 11 FCAN CONTROLLER (14) CAN global status register (CGST) The CGST register indicates global status information. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the CGST register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function.
Page 566 CHAPTER 11 FCAN CONTROLLER (2/3) (a) Read (2/2) Bit position Bit name Function Note Indicates the operation status of the time stamp counter 0: Time stamp counter is stopped 1: Time stamp counter is operating Note See 11.10 (17) CAN time stamp count register (CGTSC) Indicates the status of the global operation mode.
Page 567 CHAPTER 11 FCAN CONTROLLER (3/3) (b) Write Bit position Bit name Function Sets/clears the EFSD bit. set EFSD, 11, 3 clear EFSD set EFSD clear EFSD Operation EFSD bit cleared (to 0) EFSD bit set (to 1) Other than above No change in EFSD bit value Sets/clears the TSM bit.
Page 568 CHAPTER 11 FCAN CONTROLLER (15) CAN global interrupt enable register (CGIE) The CGIE register is used to issue interrupt requests for global interrupts. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the CGIE register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function.
Page 569 CHAPTER 11 FCAN CONTROLLER (16) CAN main clock selection register (CGCS) The CGCS register is used to select the main clock. This register can be read/written in 16-bit units. Caution When the GOM bit of the CGST register is 1, write accessing the CGCS register is prohibited.
Page 570 CHAPTER 11 FCAN CONTROLLER (2/2) Bit position Bit name Function 3 to 0 MCP3 to Specifies the clock to memory access controller (f ) (see Figure 11-26). MCP0 MCP3 MCP2 MCP1 MCP0 Selection of clock to memory access controller (f MEM1 MEM1 MEM1...
Page 571 CHAPTER 11 FCAN CONTROLLER Figure 11-26. FCAN Clocks FCAN CAN main clock selection register (CGCS) CGTS7 CGTS6 CGTS5 CGTS4 CGTS3 CGTS2 CGTS1 CGTS0 GTCS1 GTCS0 MCP3 MCP2 MCP1 MCP0 MEM1 GTS1 Global timer Global timer Prescaler Time stamp counter clock prescaler system clock PRM04 CAN1 synchronization...
Page 572 CHAPTER 11 FCAN CONTROLLER (18) CAN message search start/result register (CGMSS (during write)/CGMSR (during read)) The CGMSS/CGMSR register indicates the message search start/result status. Messages in the message buffer that match the specified search criteria can be searched quickly. These registers can be read/written in 16-bit units. Caution Execute a search by writing the CGMSS register only once.
Page 573 CHAPTER 11 FCAN CONTROLLER (2/2) (b) Write Bit position Bit name Function CIDE Checks message identifier (ID) format flag. 0: Message identifier format flag not checked 1: Only message with standard format identifier checked CTRQ Checks transmit request and message ready flag. 0: Transmit request and message ready flag not checked 1: Transmit request and message ready flag checked CMSK...
Page 574 CHAPTER 11 FCAN CONTROLLER (19) CAN1 address mask a registers L and H (C1MASKLa and C1MASKHa) The C1MASKLa and C1MASKHa registers are used to extend the number of receivable messages by masking part of the message’s identifier (ID) and then ignoring the masked parts (a = 0 to 3). These registers can be read/written in 16-bit units.
Page 575 CHAPTER 11 FCAN CONTROLLER Table 11-26. Addresses of C1MASKLa and C1MASKHa (a = 0 to 3) Note Register Name Address (m = 2, 6, A, E) C1MASKL0 xxxxmC40H C1MASKH0 xxxxmC42H C1MASKL1 xxxxmC44H C1MASKH1 xxxxmC46H C1MASKL2 xxxxmC48H C1MASKH2 xxxxmC4AH C1MASKL3 xxxxmC4CH C1MASKH3 xxxxmC4EH Note CAN message buffer registers can be allocated to the xxxx addresses as...
Page 576 CHAPTER 11 FCAN CONTROLLER (20) CAN1 control register (C1CTRL) The C1CTRL register is used to control the operation of the CAN module. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the C1CTRL register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function.
Page 577 CHAPTER 11 FCAN CONTROLLER (2/4) (a) Read (2/3) Bit position Bit name Function BOFF This is the bus off status flag. 0: Transmit error counter < 256 (not bus off status) 1: Transmit error counter ≥ 256 (bus off status) TSTAT This is the transmit status flag.
Page 578 CHAPTER 11 FCAN CONTROLLER (3/4) (a) Read (3/3) Bit position Bit name Function SLEEP This is the CAN sleep mode control bit. 0: Normal operation mode 1: Switch to CAN sleep mode. Change in CAN bus performs wake-up. Cautions 1. CAN sleep mode can be set only when the CAN bus is in the idle state. 2.
Page 579 CHAPTER 11 FCAN CONTROLLER (4/4) (b) Write (2/2) Bit position Bit name Function 12, 4 set OVM, Sets/clears the OVM bit. clear OVM clear Operation OVM bit cleared (to 0) OVM bit set (to 1) Other than above OVM bit not changed 11, 3 set TMR, Sets/clears the TMR bit.
Page 580 CHAPTER 11 FCAN CONTROLLER (21) CAN1 definition register (C1DEF) The C1DEF register is used to define the operation of the CAN module. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the C1DEF register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function.
Page 581 CHAPTER 11 FCAN CONTROLLER (2/4) (a) Read (2/3) Bit position Bit name Function Specifies the CAN module operation mode. 0: Normal operating mode 1: Diagnostic processing mode Cautions 1. When in diagnostic processing mode (MOM bit = 1), the C1BRP register can be accessed only when the CAN module has been set to initialization mode (i.e., when the C1CTRL register’s ISTAT bit = INIT bit = 1).
Page 582 CHAPTER 11 FCAN CONTROLLER (3/4) (a) Read (3/3) Bit position Bit name Function WAKE Indicates CAN sleep mode cancellation status. 0: Normal operation 1: CAN sleep mode canceled Cautions 1. The WAKE bit is set (1) only when the CAN sleep mode is released due to a change in the CAN bus and an error interrupt occurs.
Page 583 CHAPTER 11 FCAN CONTROLLER (4/4) (b) Write Bit position Bit name Function 15, 7 set DGM, Sets/clears the DGM bit. clear DGM set DGM clear DGM Operation DGM bit cleared (to 0) DGM bit set (to 1) Other than above DGM bit not changed 14, 6 set MOM,...
Page 584 CHAPTER 11 FCAN CONTROLLER (22) CAN1 information register (C1LAST) The C1LAST register indicates the CAN module’s error information and the number of the message buffer received last. This register is read-only, in 16-bit units. Address Initial value Note C1LAST LERR3 LERR2 LERR1 LERR0...
Page 585 CHAPTER 11 FCAN CONTROLLER (23) CAN1 error count register (C1ERC) The C1ERC register indicates the count values of the transmission/reception error counters. This register is read-only, in 16-bit units. Address Initial value Note C1ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7...
Page 586 CHAPTER 11 FCAN CONTROLLER (24) CAN1 interrupt enable register (C1IE) The C1IE register is used to enable/disable the CAN module’s interrupts. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the C1IE register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function.
Page 587 CHAPTER 11 FCAN CONTROLLER (2/3) (a) Read (2/2) Bit position Bit name Function This is the receive completion interrupt enable flag. E_INT1 0: Interrupt disabled 1: Interrupt enabled • When IE bit of the M_CTRLn register is 1, a reception completion interrupt occurs regardless of the setting of the E_INT1 bit if the transmit message buffer receives a remote frame while the auto response function is not set (RMDE0 bit of the M_CTRLn register = 0) (n = 00 to 31).
Page 588 CHAPTER 11 FCAN CONTROLLER (3/3) (b) Write (2/2) Bit position Bit name Function 10, 2 Sets/clears the E_INT2 bit. E_INT2, set E_INT2 clear E_INT2 Operation clear E_INT2 interrupt cleared (to 0) E_INT2 E_INT2 interrupt set (to 1) Other than above E_INT2 interrupt not changed 9, 1 Sets/clears the E_INT1 bit.
Page 589 CHAPTER 11 FCAN CONTROLLER (25) CAN1 bus active register (C1BA) The C1BA register indicates frame information output via the CAN bus. This register is read-only, in 16-bit units. Address Initial value Note C1BA CACT4 CACT3 CACT2 CACT1 CACT0 TMNO7 TMNO6 TMNO5 TMNO4 TMNO3...
Page 590 CHAPTER 11 FCAN CONTROLLER (26) CAN1 bit rate prescaler register (C1BRP) The C1BRP register is used to set the transmission baud rate for the CAN module. Use the C1BRP register to select the CAN protocol layer base system clock (f ).
Page 591 CHAPTER 11 FCAN CONTROLLER (1/2) Address Initial value C1BRP Note BTYPE BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 xxxxmC5CH 0000H (TLM = 0) C1BRP BTYPE BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 (TLM = 1) (a) When TLM = 0 Bit position Bit name Function...
Page 592 CHAPTER 11 FCAN CONTROLLER (2/2) (b) When TLM = 1 Bit position Bit name Function Specifies transfer layer mode. 1: 8-bit prescaler mode BTYPE Specifies CAN bus type. 0: Low speed (≤ 125 kbps) 1: High speed (> 125 kbps) 7 to 0 BRP7 to Specifies CAN protocol layer base system clock (f...
Page 593 CHAPTER 11 FCAN CONTROLLER (27) CAN1 bus diagnostic information register (C1DINF) The C1DINF register indicates all CAN bus bits, including stuff bits, delimiters, etc. This information is used only for diagnostic purposes. Because the number of bits starting from SOF is added at each frame, the actual number of bits is the value obtained by subtracting the previous data.
Page 594 CHAPTER 11 FCAN CONTROLLER (28) CAN1 synchronization control register (C1SYNC) The C1SYNC register controls the data bit time for transmission speed. This register can be read/written in 16-bit units. Cautions 1. The CPU is able to read the C1SYNC register at any time. 2.
Page 595 CHAPTER 11 FCAN CONTROLLER (2/3) Bit position Bit name Function 9 to 5 SPT4 to Specifies position of sampling points. SPT0 SPT4 SPT3 SPT2 SPT1 SPT0 Position of sampling point BTL × 3 Note BTL × 4 Note BTL × 5 BTL ×...
Page 596: Operations
CHAPTER 11 FCAN CONTROLLER (3/3) Bit position Bit name Function 4 to 0 DBT4 to Sets data bit time. DBT0 DBT4 DBT3 DBT2 DBT1 DBT0 Data bit time BTL × 8 BTL × 9 BTL × 10 BTL × 11 BTL ×...
Page 597 CHAPTER 11 FCAN CONTROLLER Figure 11-27. Initialization Processing START CSTP = 1? (CSTOP) CSTP = 0 (CSTOP) Set CAN main clock selection register : See Figure 11-28 CAN Main Clock Selection Register (CGCS) Settings (CGCS) Set CAN global interrupt enable register : See Figure 11-29 CAN Global Interrupt Enable Register (CGIE) Settings (CGIE) Set CAN global status register...
Page 598 CHAPTER 11 FCAN CONTROLLER Figure 11-28. CAN Main Clock Selection Register (CGCS) Settings START Select clock for memory access controller /(n + 1) MEM1 (MCP0 to MCP3) n = 0 to 15 (set using bits MCP0 to MCP3) GTCS1, GTCS0 = 00: f GTS1 Select global timer clock GTCS1, GTCS0 = 01: f...
Page 599 CHAPTER 11 FCAN CONTROLLER Figure 11-30. CAN Global Status Register (CGST) Settings START Start FCAN operation set GOM = 1 clear GOM = 0 Use time stamp function? set TSM = 1 clear TSM = 0 Figure 11-31. CAN1 Bit Rate Prescaler Register (C1BRP) Settings START Transfer speed is 125 kbps or less...
Page 600 CHAPTER 11 FCAN CONTROLLER Figure 11-32. CAN1 Synchronization Control Register (C1SYNC) Settings START 1 bit time = BTL × (m + 1) Set data bit time (DBT4 to DBT0) m = 7 to 24 (set using bits DBT4 to DBT0) Sampling point = BTL ×...
Page 601 CHAPTER 11 FCAN CONTROLLER Figure 11-33. CAN1 Interrupt Enable Register (C1IE) Settings START Interrupt enable flag Enable interrupt for end of transmission for E_INT0? clear E_INT0 = 1 set E_INT0 = 1 set E_INT0 = 0 clear E_INT0 = 0 Interrupt enable flag Enable interrupt for end of reception...
Page 602 CHAPTER 11 FCAN CONTROLLER Figure 11-34. CAN1 Definition Register (C1DEF) Settings START Set to diagnostic processing mode? clear MOM = 1 set MOM = 1 Normal operation mode Diagnostic processing mode set MOM = 0 clear MOM = 0 Note Store to buffer used for diagnostic processing mode?
Page 603 CHAPTER 11 FCAN CONTROLLER Figure 11-35. CAN1 Control Register (C1CTRL) Settings START Set time stamp for Store timer value receiving when SOF occurs? Store timer value when clear TMR = 1 set TMR = 1 EOF occurs set TMR = 0 clear TMR = 0 Set overwrite for Store message...
Page 604 CHAPTER 11 FCAN CONTROLLER Figure 11-36. CAN1 Address Mask a Registers L and H (C1MASKLa and C1MASKHa) (a = 0 to 3) Settings START Standard frame Mask setting for extended frame (x = 0 to 28) (y = 0 to 17) CMIDy = 1 Mask setting for standard frame (x = 18 to 28)
Page 605 CHAPTER 11 FCAN CONTROLLER Figure 11-37. Message Buffer Settings START Set message Standard frame? ID type IIDE = 0 (standard) IDE = 1 (extended) (M_IDHn) (M_IDHn) Set identifier (standard, extended) See Figure 11-38 CAN Message Configuration Set message configuration Registers 00 to 31 (M_CONF00 to M_CONF31) Settings Set message length See Figure 11-39 CAN Message Control...
Page 606 CHAPTER 11 FCAN CONTROLLER Figure 11-38. CAN Message Configuration Registers 00 to 31 (M_CONF00 to M_CONF31) Settings START Release CAN Use message buffer? message buffer MA = 0 MA = 1 MT2 to MT0 = 000 Transmit message Receive message MT2 to MT0 = 001 (no mask setting) Receive message...
Page 607 CHAPTER 11 FCAN CONTROLLER Figure 11-39. CAN Message Control Registers 00 to 31 (M_CTRL00 to M_CTRL31) Settings START Transmit/receive data frame? RTR = 0 RTR = 1 Transmit/receive remote frame Disable interrupt? IE = 0 IE = 1 Enable interrupt Remote frame auto Set remote frame auto acknowledge function...
Page 608 CHAPTER 11 FCAN CONTROLLER Figure 11-40. CAN Message Status Registers 00 to 31 (M_STAT00 to M_STAT31) Settings START Clear DN flag clear DN = 1, set DN = 0 (SC_STATm) Clear TRQ flag clear TRQ = 1, set TRQ = 0 (SC_STATm) Clear RDY flag clear RDY = 1, set RDY = 0...
Page 609: Transmit Setting
CHAPTER 11 FCAN CONTROLLER 11.11.2 Transmit setting Transmit messages are output from the target message buffer. Figure 11-41. Transmit Setting START Select transmit message buffer Set data (M_DATAnm) Set RDY flag set RDY = 1, clear RDY = 0 (SC_STATn) Set transmit request flag set TRQ = 1, clear TRQ = 0 (SC_STATn)
Page 610: Receive Setting
CHAPTER 11 FCAN CONTROLLER 11.11.3 Receive setting Receive messages are retrieved from the target message buffer. Figure 11-42. Setting of Receive Completion Interrupt and Reception Operation Using Reception Polling START Set RDY flag set RDY = 1, clear RDY = 0 (SC_STATn) Receive completion interrupt occurs...
Page 611 CHAPTER 11 FCAN CONTROLLER Figure 11-43. CAN Message Search Start/Result Register (CGMSS/CGMSR) Settings START Check DN flag (CDN = 1) Check masked messages? CMSK = 0 Search non mask- Search all messages CMSK = 1 (CGMSS) linked messages only (regardless of mask setting) (CGMSS) Check message ID? CIDE = 1...
Page 612: Can Sleep Mode
CHAPTER 11 FCAN CONTROLLER 11.11.4 CAN sleep mode In CAN sleep mode, the FCAN controller can be set to standby mode. A wake-up occurs when there is a bus operation. Figure 11-44. CAN Sleep Mode Settings START set SLEEP = 1 clear SLEEP = 0 (C1CTRL) SLEEP = 1...
Page 613: Can Stop Mode
CHAPTER 11 FCAN CONTROLLER Figure 11-46. Clearing of CAN Sleep Mode by CPU START clear SLEEP = 1 set SLEEP = 0 (C1CTRL) SLEEP = 0 (C1CTRL) End of CAN sleep mode clearing operation 11.11.5 CAN stop mode In CAN stop mode, the FCAN controller can be set to standby mode. No wake-up occurs when there is a bus operation (stop mode is controlled by CPU access only).
Page 614 CHAPTER 11 FCAN CONTROLLER Figure 11-48. Clearing of CAN Stop Mode START clear STOP = 1 set STOP = 0 clear SLEEP = 1 set SLEEP = 0 (C1CTRL) STOP = 0 SLEEP = 0 (C1CTRL) End of CAN stop mode clearing operation User’s Manual U14492EJ5V0UD...
Page 615: Rules For Correct Setting Of Baud Rate
CHAPTER 11 FCAN CONTROLLER 11.12 Rules for Correct Setting of Baud Rate The CAN protocol limit values for ensuring correct operation of FCAN are described below. If these limit values are exceeded, a CAN protocol violation may occur, which can result in operation faults. Always make sure that settings are within the range of limit values.
Page 616 CHAPTER 11 FCAN CONTROLLER Given the above limit values, the following four settings are possible. Prescaler SPT (MAX.) Calculated SPT 5/8 = 62.5% 9/12 = 75% 13/16 = 81% 17/24 = 71% 16 MHz/83 kbps ≅ 192 = 64 × 3 <1>...
Page 617 CHAPTER 11 FCAN CONTROLLER (ii) DBT (data bit time) setting DBT is calculated as below. • DBT = BTL × (a + 1) : [7 ≤ a ≤ 24] Value a is set using bits 4 to 0 (DBT4 to DBT0) of the C1SYNC register. DBT = BTL ×...
Page 618 CHAPTER 11 FCAN CONTROLLER Figure 11-49. C1SYNC Register Settings C1SYNC SAMP SJW1 SJW0 SPT4 SPT3 Setting SPT2 SPT1 SPT0 DBT4 DBT3 DBT2 DBT1 DBT0 Setting User’s Manual U14492EJ5V0UD...
Page 619: Ensuring Data Consistency
CHAPTER 11 FCAN CONTROLLER 11.13 Ensuring Data Consistency When the CPU reads data from CAN message buffers, it is essential for the read data to be consistent. Two methods are used to ensure data consistency: sequential data read and burst read mode. 11.13.1 Sequential data read When the CPU performs sequential access of a CAN message buffer, data is read from the buffer in the order shown in Figure 11-50 below.
Page 620: Burst Read Mode
CHAPTER 11 FCAN CONTROLLER 11.13.2 Burst read mode Burst read mode is implemented in the FCAN to enable faster access to complete messages and secure the synchrony of data. Burst read mode starts up automatically each time the CPU reads the M_DLCn register and data is then copied from the message buffer area to a temporary read buffer.
Page 621: Interrupt Conditions
CHAPTER 11 FCAN CONTROLLER 11.14 Interrupt Conditions 11.14.1 Interrupts that are generated for FCAN controller When interrupts are enabled (condition <1>: M_CTRLn register’s IE bit = 1, conditions other than <1>: C1IE register’s interrupt enable flag = 1), interrupts will be generated under the following conditions (n = 00 to 31). <1>...
Page 622: How To Shut Down Fcan Controller
CHAPTER 11 FCAN CONTROLLER 11.15 How to Shut Down FCAN Controller The following procedure should be used to stop CAN bus operations in order to stop the clock supply to the CAN interface (to set low power mode). <1> FCAN controller’s initialization mode setting •...
Page 623: Cautions On Use
CHAPTER 11 FCAN CONTROLLER 11.16 Cautions on Use <1> Bit manipulation is prohibited for all FCAN controller registers. Note <2> Be sure to properly clear (0) all interrupt request flags in the interrupt routine. If these flags are not cleared (0), subsequent interrupt requests may not be generated. Note also that if an interrupt is generated at the same time as a CPU clear operation, that interrupt request flag will not be cleared (0).
Page 624 CHAPTER 11 FCAN CONTROLLER <6> If the OS (OSEK/COM) is not used, be sure to execute the following processing. [When CAN communication is performed using an interrupt routine] • Clear (0) the following interrupt pending bits at the start of the corresponding interrupt routine. •...
Page 625: Chapter 12 Nbd Function
µ CHAPTER 12 NBD FUNCTION ( PD70F3116) The V850E/IA1 provides the Non Break Debug (NBD) function for on-chip data tuning. 12.1 Overview The NBD function encompasses the following functions. (1) RAM monitoring function This function makes an arbitrary RAM area readable or writable using an NBD tool via DMA. [Corresponding RAM area] XFFFC000H to XFFFE7FFH If executed using an address outside the above, the function instantly returns “ready”.
Page 626: Nbd Function Register Map
µ CHAPTER 12 NBD FUNCTION ( PD70F3116) Figure 12-1. Image of NBD Space V850E/IA1 possible NBD dedicated interface (7 ways) unit tool NBD : Non Break Debug Caution The debug function does not operate under the following conditions. • During reset period •...
Page 627: Nbd Function Protocol
µ CHAPTER 12 NBD FUNCTION ( PD70F3116) 12.3 NBD Function Protocol The basic protocol of the NBD function is shown below. (1) Basic protocol Figure 12-2. Basic Protocol (1) On a read CLK_DBG SYNC AD0_DBG to Control Address section section AD3_DBG Command packet Flag sense...
Page 628 µ CHAPTER 12 NBD FUNCTION ( PD70F3116) (2) Command packet NBD Bus Line AD3_DBG AD2_DBG AD1_DBG AD0_DBG aux3 aux2 aux1 aux0 SIZ1 SIZ0 10th 11th 12th 13th 14th 15th 16th Caution Values are for command packet maximum setup. • Access to NBD space Address: 12 bits (A0 to A11) [Fixed] Data: 8 bits (D0 to D7) •...
Page 629 µ CHAPTER 12 NBD FUNCTION ( PD70F3116) (d) SIZ0, SIZ1: Access data size specification SIZ1 SIZ0 Target Space Access NBD Space Access Note 1 8-bit length 8-bit length Note 1 Note 2 16-bit length Setting prohibited 32-bit length Note 2 Setting prohibited Notes 1.
Page 630: Nbd Function
µ CHAPTER 12 NBD FUNCTION ( PD70F3116) 12.4 NBD Function 12.4.1 RAM monitoring, accessing NBD space The NBD function performs reading and writing of internal RAM data for addresses in internal RAM via the DMA (direct memory access) controller. It also performs reading or writing to the NBD space. (1) RAM monitoring The following are the commands for reading and writing to internal RAM areas from the NBD tool.
Page 631 µ CHAPTER 12 NBD FUNCTION ( PD70F3116) (2) Access to NBD space The following are the commands for reading or writing to the NBD space from the NBD tool. For the NBD space, the access address length is fixed to 12 bits and the access data length is fixed to 8 bits. (a) Write command The address (NBD space address: 12 bits) at which write to the NBD space is to be performed and the data sent from the NBD tool are received as a command packet.
Page 632: Event Detection Function
µ CHAPTER 12 NBD FUNCTION ( PD70F3116) Table 12-8. Data Packet ADn_DBG AD3_DBG AD2_DBG AD1_DBG AD0_DBG Caution The length of the read data is fixed to 8 bits. 12.4.2 Event detection function By having a comparator (24-bit address setting) for match detection on-chip, this function detects match of the address setting registers shown below and outputs a match trigger (falling edge) to the NBD tool.
Page 633: Chip Id Registers (Tid0 To Tid2)
The chip ID registers (TID0 to TID2) are read-only registers. NBD space address TID0 000H • MC7 to MC0: Semiconductor manufacturer classification code NEC Electronics: 4EH NBD space address TID1 001H • FC7 to FC0: CPU classification code V850E1 CPU: 01H...
Page 634: Control Registers
µ CHAPTER 12 NBD FUNCTION ( PD70F3116) 12.5 Control Registers (1) RAM access data buffer register L (NBDL) The NBDL register operates as the buffer between the DMA controller and the NBD tool when reading or writing RAM from the NBD tool via the DMA controller. This register can be read/written in 16-bit units.
Page 635 µ CHAPTER 12 NBD FUNCTION ( PD70F3116) (3) DMA source address setting register SL (NBDMSL) The NBDMSL register specifies a DMA source address. This register can be written from the NBD tool and read by the DMA controller (CPU). This register is read-only, in 16-bit units. Address Initial value NBDMSL...
Page 636 µ CHAPTER 12 NBD FUNCTION ( PD70F3116) (5) DMA destination address setting register DL (NBDMDL) The NBDMDL register specifies a DMA destination address. This register can be written from the NBD tool and read by the DMA controller (CPU). This register is read-only, in 16-bit units. Address Initial value NBDMDL...
Page 637: Restrictions On Nbd
µ CHAPTER 12 NBD FUNCTION ( PD70F3116) 12.6 Restrictions on NBD 12.6.1 General restrictions (1) CLK_DBG operates at less than half the speed of the internal system clock (f ) and is 12.5 MHz maximum. (2) If a command packet is sent during a reset period, “ready” is not returned afterwards. Reset again. 12.6.2 Restrictions related to read or write of RAM by NBD (1) Initialize the DMA controller in user software.
Page 638: Initialization Required For Dma (2 Channels)
µ CHAPTER 12 NBD FUNCTION ( PD70F3116) 12.7 Initialization Required for DMA (2 Channels) (1) The DMA initialization in a setting change request must be performed by user software. (2) Assign DMA two channels in NBD. At this time, assign an NBDAD interrupt to a higher priority channel than an NBDREW interrupt. (3) Initialize registers of the channel to which the NBDAD interrupt is assigned.
Page 639 µ CHAPTER 12 NBD FUNCTION ( PD70F3116) Examples of DMA initialization on 32-bit transfer, 16-bit transfer, and 8-bit transfer are shown below. (a) Example of 32-bit transfer DMA initialization -- DMA INITIAL -– 0x0000FA64 , r24 -- DMACH0 Source Address –- st.h r24 , DSAL0[r0] 0x00000FFF ,...
Page 640 µ CHAPTER 12 NBD FUNCTION ( PD70F3116) (b) Example of 16-bit transfer DMA initialization -- DMA INITIAL -– 0x0000FA64 , r24 -- DMACH0 Source Address –- st.h r24 , DSAL0[r0] 0x00000FFF , r24 –- DMACH0 Source Address –- st.h r24 , DSAH0[r0] 0x0000F088 , r24 –- DMACH0 Destination Address –- st.h...
Page 641 µ CHAPTER 12 NBD FUNCTION ( PD70F3116) (c) Example of 8-bit transfer DMA initialization -- DMA INITIAL -– 0x0000FA64 , r24 -- DMACH0 Source Address –- st.h r24 , DSAL0[r0] 0x00000FFF , r24 –- DMACH0 Source Address –- st.h r24 , DSAH0[r0] 0x0000F088 , r24 –- DMACH0 Destination Address –- st.h...
Page 642: Chapter 13 A/D Converter
CHAPTER 13 A/D CONVERTER 13.1 Features • Two 10-bit resolution on-chip A/D converters (A/D converter 0 and 1) Simultaneous sampling by two circuits is possible. • Analog input: 8 channels per circuit • On-chip A/D conversion result registers 0n, 1n (ADCR0n, ADCR1n) 10 bits ×...
Page 643 CHAPTER 13 A/D CONVERTER (6) A/D conversion result registers 0n, 1n (ADCR0n, ADCR1n) ADCR0n and ADCR1n are 10-bit registers that hold A/D conversion results (n = 0 to 7). Whenever an A/D conversion terminates, the conversion result from the successive approximation register (SAR) is loaded. RESET input sets these registers to 0000H.
Page 644 CHAPTER 13 A/D CONVERTER Figure 13-1. Block Diagram of A/D Converter 0 or 1 ANIn0 ANIn1 ANIn2 ANIn3 Comparator Sample and and D/A ANIn4 hold circuit REFn converter ANIn5 ANIn6 ANIn7 SAR (10) INTADn ADCRn0 ITRG0 Controller ADCRn1 ADCRn2 ADTRGn INTDETn ADCRn3 Trigger source switching...
Page 645 CHAPTER 13 A/D CONVERTER Figure 13-2. Block Diagram of Trigger Source Switching Circuit in Timer Trigger Mode ADTRG0 A/D converter 0 ITRG0 INTCM003 INTCM013 ADTRG1 A/D converter 1 ITRG0 INTTM00 INTTM01 ITRG0 ITRG22 ITRG21 ITRG20 ITRG12 ITRG11 ITRG10 Internal bus Caution For the selection of the trigger source in timer trigger mode, refer to 13.3 (5) A/D internal trigger selection register (ITRG0).
Page 646: Control Registers
CHAPTER 13 A/D CONVERTER 13.3 Control Registers (1) A/D scan mode registers 00 and 10 (ADSCM00, ADSCM10) The ADSCMn0 registers are 16-bit registers that select analog input pins, specify operation modes, and control conversion operation. The ADSCMn0 register can be read/written in 16-bit units. When the higher 8 bits of the ADSCMn0 register are used as the ADSCMn0H register, and the lower 8 bits are used as the ADSCMn0L register, they can be read/written in 8-bit or 1-bit units.
Page 647 CHAPTER 13 A/D CONVERTER (1/2) <15> <14> <12> <11> Address Initial value ADSCM00 ADCE0 ADCS0 ADMS0 ADPLM0 TRG2 TRG1 TRG0 SANI3 SANI2 SANI1 SANI0 ANIS3 ANIS2 ANIS1 ANIS0 FFFFF200H 0000H <15> <14> <12> <11> Address Initial value ADSCM10 FFFFF240H 0000H ADCE1 ADCS1 ADMS1...
Page 648 CHAPTER 13 A/D CONVERTER (2/2) Bit position Bit name Function 7 to 4 SANI3 to Specifies conversion start analog input pin in scan mode. SANI0 These bits are ignored in select mode. SANI3 SANI2 SANI1 SANI0 Scan start analog input pin ANIn0 ANIn1 ANIn2...
Page 649 CHAPTER 13 A/D CONVERTER (2) A/D scan mode registers 01 and 11 (ADSCM01, ADSCM11) The ADSCMn1 registers are 16-bit registers that set the conversion time of the A/D converter. The ADSCMn1 register can be read/written in 16-bit units. When the higher 8 bits of the ADSCMn1 register are used as the ADSCMn1H register, and the lower 8 bits are used as the ADSCMn1L register, the ADSCMn1H register can be read/written in 8-bit or 1-bit units, and the ADSCMn1L register is read-only, in 8-bit units.
Page 650 CHAPTER 13 A/D CONVERTER (3) A/D voltage detection mode registers 0 and 1 (ADETM0, ADETM1) The ADETMn registers are 16-bit registers that set voltage detection mode. In voltage detection mode, the analog input pin for which voltage detection is being performed and a reference voltage value are compared and an interrupt is set in response to the comparison result.
Page 651 CHAPTER 13 A/D CONVERTER (4) A/D conversion result registers 00 to 07 and 10 to 17 (ADCR00 to ADCR07, ADCR10 to ADCR17) The ADCR0n and ADCR1n registers are 10-bit registers that hold the results of A/D conversions (n = 0 to 7). One A/D converter is equipped with eight 10-bit registers for 8 channels, and A/D converters 0 and 1 together have sixteen 10-bit registers.
Page 652 CHAPTER 13 A/D CONVERTER The correspondence between each analog input pin and the ADCR0n and ADCR1n registers is shown below. Table 13-3. Correspondence Between Each Analog Input Pin and ADCR0n and ADCR1n Registers A/D Converter Analog Input Pin A/D Conversion Result Register A/D converter 0 ANI00 ADCR00...
Page 653 CHAPTER 13 A/D CONVERTER The relationship between the analog voltage input to an analog input pin (ANI0n or ANI1n) and the value of the A/D conversion result register (ADCR0n or ADCR1n) is as follows (n = 0 to 7): ADCR = INT ( ×...
Page 654 CHAPTER 13 A/D CONVERTER (5) A/D internal trigger selection register (ITRG0) The ITRG0 register is the register that switches the trigger source in timer trigger mode. The timer trigger source of A/D converters 0 and 1 can be set using the ITRG0 register. This register can be read/written in 8-bit or 1-bit units.
Page 655: Interrupt Requests
CHAPTER 13 A/D CONVERTER 13.4 Interrupt Requests A/D converters 0 and 1 generate two kinds of interrupts. • A/D conversion termination interrupts (INTAD0, INTAD1) • Voltage detection interrupts (INTDET0, INTDET1) (1) A/D conversion termination interrupts (INTAD0, INTAD1) In A/D conversion enabled status, an A/D conversion termination interrupt is generated when a specified number of A/D conversions have terminated.
Page 656: A/D Converter Operation
CHAPTER 13 A/D CONVERTER 13.5 A/D Converter Operation 13.5.1 A/D converter basic operation A/D conversion is performed using the following procedure. (1) Set the analog input selection and the operation mode and trigger mode specifications using the ADSCM00 Note 1 or ADSCM10 register .
Page 657: Operation Modes And Trigger Modes
CHAPTER 13 A/D CONVERTER 13.5.2 Operation modes and trigger modes Diverse conversion operations can be specified for A/D converters 0 and 1 by specifying operation modes and trigger modes. Operation modes and trigger modes are set using the ADSCM00 or ADSCM10 register. The relationship between operation modes and trigger modes is shown below.
Page 658 CHAPTER 13 A/D CONVERTER (2) Operation modes The two operation modes, which are the modes that set the ANI00 to ANI07 and ANI10 to ANI17 pins, are select mode and scan mode. These modes are set using the ADSCM00 and ADSCM10 registers. (a) Select mode Select mode A/D converts one analog input specified in the ADSCM00 or ADSCM10 register.
Page 659 CHAPTER 13 A/D CONVERTER (b) Scan mode Scan mode sequentially selects and A/D converts pins from the A/D conversion start analog input pin through the A/D conversion termination analog input pin specified in the ADSCM00 or ADSCM10 register. It stores the A/D conversion result in the ADCR0n or ADCR1n register corresponding to the analog input (n = 0 to 7).
Page 660: Operation In A/D Trigger Mode
CHAPTER 13 A/D CONVERTER 13.6 Operation in A/D Trigger Mode Setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1 starts A/D conversion. 13.6.1 Operation in select mode One analog input specified in the ADSCM00 or ADSCM10 register is A/D converted at a time and the result is stored in an ADCR0n or ADCR1n register.
Page 661: Operation In Scan Mode
CHAPTER 13 A/D CONVERTER 13.6.2 Operation in scan mode Pins from the conversion start analog input pin through the conversion termination analog input pin specified in the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted. An A/D conversion result is stored in the ADCR0n or ADCR1n register corresponding to the analog input (n = 0 to 7).
Page 662: Operation In A/D Trigger Polling Mode
CHAPTER 13 A/D CONVERTER 13.7 Operation in A/D Trigger Polling Mode Setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1 starts A/D conversion. Both select mode and scan mode are available in A/D trigger polling mode. Since the ADCS0 or ADCS1 bit of the ADSCM00 or ADSCM10 register remains 1 after an INTAD0 or INTAD1 interrupt in this mode, it is not necessary to write 1 in the ADCE0 or ADCE1 bit as an A/D conversion restart operation.
Page 663: Operation In Scan Mode
CHAPTER 13 A/D CONVERTER 13.7.2 Operation in scan mode Pins from the conversion start analog input pin through the conversion termination analog input pin specified in the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted. An A/D conversion result is stored in the ADCR0n or ADCR1n register corresponding to the analog input (n = 0 to 7).
Page 664: Operation In Timer Trigger Mode
CHAPTER 13 A/D CONVERTER 13.8 Operation in Timer Trigger Mode The A/D converter can set an interrupt signal specified by the A/D internal trigger selection register 0 (ITRG0) as a conversion trigger for up to 8 channels (a total of 16 channels in 2 circuits) of analog input (ANI00 to ANI07, ANI10 to ANI17).
Page 665: Operation In Scan Mode
CHAPTER 13 A/D CONVERTER 13.8.2 Operation in scan mode Using the interrupt signal specified by the A/D internal trigger selection register 0 (ITRG0) as a trigger, the conversion start analog input pin through the conversion termination analog input pin specified by the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted.
Page 666: Operation In External Trigger Mode
CHAPTER 13 A/D CONVERTER 13.9 Operation in External Trigger Mode In external trigger mode, analog input (ANI00 to ANI07, ANI10 to ANI17) is A/D converted on ADTRG0 or ADTRG1 pin input timing. The valid edge of an external input signal in external trigger mode can be specified as a rising edge, a falling edge, or a rising or falling edge in the ES21 or ES20 bit of the INTM1 register for A/D converter 0 and in the ES31 or ES30 bit of the INTM1 register for A/D converter 1.
Page 667: Operation In Scan Mode
CHAPTER 13 A/D CONVERTER 13.9.2 Operation in scan mode Using an ADTRG0 or ADTRG1 signal as a trigger, pins from the conversion start analog input pin through the conversion termination analog input pin specified by the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted.
Page 668: Precautions On Operation
CHAPTER 13 A/D CONVERTER 13.10 Precautions on Operation 13.10.1 Stopping A/D conversion operation If 0 is written in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register during A/D conversion operation, it stops A/D conversion operation and an A/D conversion result is not stored in the ADCR0n or ADCR1n register (n = 0 to 7).
Page 669: Compare Match Interrupt In Timer Trigger Mode
CHAPTER 13 A/D CONVERTER 13.10.5 Compare match interrupt in timer trigger mode A TM0n timer 0 register underflow interrupt (INTTM00 or INTTM01) and CM003 or CM013 interrupt (INTCM003 or INTCM013) is an A/D conversion start trigger that starts conversion operation (n = 0, 1). At this time, the CM003 or CM013 match interrupt (INTCM003 or INTCM013) also functions as a compare register match interrupt for the CPU.
Page 670: How To Read A/D Converter Characteristics Table
CHAPTER 13 A/D CONVERTER 13.11 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 671 CHAPTER 13 A/D CONVERTER (3) Quantization error When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot be avoided.
Page 672 CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full scale − 3/2LSB) when the digital output changes from 1……110 to 1……111. Figure 13-19. Full-Scale Error Full-scale error (n = 0, 1) –0...
Page 673 CHAPTER 13 A/D CONVERTER (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0.
Page 674: Chapter 14 Port Functions
CHAPTER 14 PORT FUNCTIONS 14.1 Features • Input dedicated ports : 8 I/O ports: 75 • Ports alternate as I/O pins of other peripheral functions • Input or output can be specified in bit units 14.2 Basic Configuration of Ports The V850E/IA1 has a total of 83 on-chip input/output ports (ports 0 to 4, DH, DL, CS, CT, CM), of which 8 are input-only ports.
Page 675 CHAPTER 14 PORT FUNCTIONS Port Name Pin Name Port Function Function in Control Mode Block Type Port 0 P00 to P07 8-bit input NMI input, timer/counter output stop signal input, external interrupt input, A/D converter (ADC) external trigger input Port 1 P10 to P15 6-bit I/O Timer/counter I/O...
Page 676 CHAPTER 14 PORT FUNCTIONS (2) Functions of each port pin after reset and registers that set port or control mode Port Name Pin Name Pin Function After Reset Mode-Setting Register Single-Chip Single-Chip ROMless ROMless Mode 0 Mode 1 Mode 0 Mode 1 −...
Page 677 CHAPTER 14 PORT FUNCTIONS Port Name Pin Name Pin Function After Reset Mode-Setting Register Single-Chip Single-Chip ROMless ROMless Mode 0 Mode 1 Mode 0 Mode 1 Port 4 P40/SI0 P40 (Input mode) PMC4 P41/SO0 P41 (Input mode) P42/SCK0 P42 (Input mode) P43/SI1 P43 (Input mode) P44/SO1...
Page 678 CHAPTER 14 PORT FUNCTIONS (3) Port block diagrams Figure 14-1. Type A Block Diagram PMCmn PMmn Output signal in PORT control mode Address Remark m: Port number n: Bit number User’s Manual U14492EJ5V0UD...
Page 679 CHAPTER 14 PORT FUNCTIONS Figure 14-2. Type B Block Diagram PMCmn PMmn PORT Address Noise elimination Input signal in Edge detection control mode Remark m: Port number n: Bit number User’s Manual U14492EJ5V0UD...
Page 680 CHAPTER 14 PORT FUNCTIONS Figure 14-3. Type C Block Diagram PMCmn PMmn PORT Address Input signal in control mode Remark m: Port number n: Bit number User’s Manual U14492EJ5V0UD...
Page 681 CHAPTER 14 PORT FUNCTIONS Figure 14-4. Type D Block Diagram MODE0 to MODE2 PMCmn PMmn PORT Address Input signal in control mode Remark m: Port number n: Bit number Figure 14-5. Type E Block Diagram PMmn PORT Address Remark m: Port number n: Bit number User’s Manual U14492EJ5V0UD...
Page 682 CHAPTER 14 PORT FUNCTIONS Figure 14-6. Type F Block Diagram Noise elimination Address Input signal in Edge detection control mode Figure 14-7. Type G Block Diagram PMCmn PMmn Output signal in PORT control mode Address Remark m: Port number n: Bit number User’s Manual U14492EJ5V0UD...
Page 683 CHAPTER 14 PORT FUNCTIONS Figure 14-8. Type H Block Diagram PMCmn PMmn PORT Address Input signal in control mode Remark m: Port number n: Bit number User’s Manual U14492EJ5V0UD...
Page 684 CHAPTER 14 PORT FUNCTIONS Figure 14-9. Type J Block Diagram MODE0 to MODE2 PMCmn PMmn Output signal in PORT control mode Address Remark m: Port number n: Bit number User’s Manual U14492EJ5V0UD...
Page 685 CHAPTER 14 PORT FUNCTIONS Figure 14-10. Type M Block Diagram SCKx, ASCKy output enable signal PMCmn PMmn Output signal in control mode PORT Address Input signal in control mode Remark mn: 34, 37, 42, 45 0 (When mn = 42) 1 (When mn = 45) 1 (When mn = 34) 2 (When mn = 37)
Page 686 CHAPTER 14 PORT FUNCTIONS Figure 14-11. Type N Block Diagram PFCmn PMCmn PMmn Output signal in PORT control mode Address Input signal in Noise elimination control mode Edge detection Remark m: Port number n: Bit number User’s Manual U14492EJ5V0UD...
Page 687 CHAPTER 14 PORT FUNCTIONS Figure 14-12. Type O Block Diagram MODE0 to MODE2 I/O control PMCmn PMmn Output signal in control mode PORT Address Input signal in control mode I/O control Remark m: Port number n: Bit number User’s Manual U14492EJ5V0UD...
Page 688 CHAPTER 14 PORT FUNCTIONS Figure 14-13. Type P Block Diagram MODE0 to MODE2 I/O control PMCmn PMmn Output signal in PORT control mode Address Remark m: Port number n: Bit number User’s Manual U14492EJ5V0UD...
Page 689: Pin Functions Of Each Port
CHAPTER 14 PORT FUNCTIONS 14.3 Pin Functions of Each Port 14.3.1 Port 0 Port 0 is an 8-bit input dedicated port in which all pins are fixed for input. Address Initial value FFFFF400H Undefined Besides functioning as an input port, in control mode, it also can operate as the timer/counter output stop signal input, external interrupt request input, and A/D converter (ADC) external trigger input.
Page 690: Port 1
CHAPTER 14 PORT FUNCTIONS 14.3.2 Port 1 Port 1 is a 6-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value – – FFFFF402H Undefined Bit position Bit name Function 5 to 0 I/O port (n = 5 to 0) Besides functioning as a port, in control mode, it also can operate as the timer/counter I/O and external interrupt...
Page 691 CHAPTER 14 PORT FUNCTIONS (b) Port 1 mode control register (PMC1) This register can be read/written in 8-bit or 1-bit units. Write 0 in bits 6 and 7. Caution The PMC11, PMC12, PMC14, and PMC15 bits also serve as external interrupts (INTP100, INTP101, INTP110, and INTP111).
Page 692 CHAPTER 14 PORT FUNCTIONS (c) Port 1 function control register (PFC1) This register can be read/written in 8-bit or 1-bit units. Write 0 in bits other than 0 and 3. Caution When port mode is specified by the port 1 mode control register (PMC1), the setting of this register is invalid.
Page 693: Port 2
CHAPTER 14 PORT FUNCTIONS 14.3.3 Port 2 Port 2 is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value FFFFF404H Undefined Bit position Bit name Function 7 to 0 I/O port (n = 7 to 0) Besides functioning as a port, in control mode, it also can operate as the timer/counter I/O and external interrupt request input.
Page 694 CHAPTER 14 PORT FUNCTIONS (b) Port 2 mode control register (PMC2) This register can be read/written in 8-bit or 1-bit units. Caution The PMC20, PMC25, and PMC26 bits also serve as external interrupts (INTP20, INTP25, and INTP30). When not using them as external interrupts, mask interrupt requests (refer to 7.3.4 Interrupt control register (xxICn)).
Page 695 CHAPTER 14 PORT FUNCTIONS (c) Port 2 function control register (PFC2) This register can be read/written in 8-bit or 1-bit units. Write 0 in bits 0, 5, and 6. Caution When port mode is specified by the port 2 mode control register (PMC2), the setting of this register is invalid.
Page 696: Port 3
CHAPTER 14 PORT FUNCTIONS 14.3.4 Port 3 Port 3 is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value FFFFF406H Undefined Bit position Bit name Function 7 to 0 I/O port (n = 7 to 0) Besides functioning as a port, in control mode, it also can operate as the serial interface (UART0 to UART2) I/O.
Page 697 CHAPTER 14 PORT FUNCTIONS (b) Port 3 mode control register (PMC3) This register can be read/written in 8-bit or 1-bit units. Address Initial value PMC3 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 FFFFF446H Bit position Bit name Function PMC37 Specifies operation mode of P37 pin.
Page 698: Port 4
CHAPTER 14 PORT FUNCTIONS 14.3.5 Port 4 Port 4 is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value FFFFF408H Undefined Bit position Bit name Function 7 to 0 I/O port (n = 7 to 0) Besides functioning as a port, in control mode, it also can operate as the serial interface (CSI0, CSI1, FCAN) I/O.
Page 699 CHAPTER 14 PORT FUNCTIONS (b) Port 4 mode control register (PMC4) This register can be read/written in 8-bit or 1-bit units. Address Initial value PMC4 PMC47 PMC46 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 FFFFF448H Bit position Bit name Function PMC47 Specifies operation mode of P47 pin.
Page 700: Port Dh
CHAPTER 14 PORT FUNCTIONS 14.3.6 Port DH Port DH is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value PDH7 PDH6 PDH5 PDH4 PDH3 PDH2 PDH1 PDH0 FFFFF006H Undefined Bit position Bit name Function 7 to 0...
Page 701 CHAPTER 14 PORT FUNCTIONS (b) Port DH mode control register (PMCDH) This register can be read/written in 8-bit or 1-bit units. Note Address Initial value PMCDH PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 FFFFF046H 00H/FFH Note 00H: Single-chip mode 0 FFH: Single-chip mode 1, ROMless mode 0 or 1 Bit position Bit name...
Page 702: Port Dl
CHAPTER 14 PORT FUNCTIONS 14.3.7 Port DL Port DL is a 16-bit or 8-bit I/O port in which input or output can be specified in 1-bit units. When using the higher 8 bits of PDL as PDLH and the lower 8 bits as PDLL, it can be used as an 8-bit I/O port that can specify input or output in 1-bit units.
Page 703 CHAPTER 14 PORT FUNCTIONS (a) Port DL mode register (PMDL) The PMDL register can be read/written in 16-bit units. When using the higher 8 bits of the PMDL register as the PMDLH register and the lower 8 bits as the PMDLL register, it can be read/written in 8-bit or 1-bit units.
Page 704: Port Cs
CHAPTER 14 PORT FUNCTIONS 14.3.8 Port CS Port CS is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 FFFFF008H Undefined Bit position Bit name Function 7 to 0...
Page 705 CHAPTER 14 PORT FUNCTIONS (2) Setting in I/O mode and control mode Port CS is set in I/O mode using the port CS mode register (PMCS). In control mode, it is set using the port CS mode control register (PMCCS). (a) Port CS mode register (PMCS) This register can be read/written in 8-bit or 1-bit units.
Page 706: Port Ct
CHAPTER 14 PORT FUNCTIONS 14.3.9 Port CT Port CT is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value PCT7 PCT6 PCT5 PCT4 PCT3 PCT2 PCT1 PCT0 FFFFF00AH Undefined Bit position Bit name Function 7 to 0...
Page 707 CHAPTER 14 PORT FUNCTIONS (b) Port CT mode control register (PMCCT) This register can be read/written in 8-bit or 1-bit units. Note Address Initial value PMCCT PMCCT6 PMCCT4 PMCCT1 PMCCT0 FFFFF04AH 00H/53H Note 00H: Single-chip mode 0 53H: Single-chip mode 1, ROMless mode 0 or 1 Bit position Bit name Function...
Page 708: Port Cm
CHAPTER 14 PORT FUNCTIONS 14.3.10 Port CM Port CM is a 5-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value – – – PCM4 PCM3 PCM2 PCM1 PCM0 FFFFF00CH Undefined Bit position Bit name Function 4 to 0...
Page 709 CHAPTER 14 PORT FUNCTIONS (b) Port CM mode control register (PMCCM) This register can be read/written in 8-bit or 1-bit units. Note Address Initial value PMCCM PMCCM3 PMCCM2 PMCCM1 PMCCM0 FFFFF04CH 00H/0FH Note 00H: Single-chip mode 0 0FH: Single-chip mode 1, ROMless mode 0 or 1 Bit position Bit name Function...
Page 710: Operation Of Port Function
CHAPTER 14 PORT FUNCTIONS 14.4 Operation of Port Function The operation of a port differs depending on whether it is set in the input or output mode, as follows. 14.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch (Pn) by writing it to the port n register (Pn). The contents of the output latch are output from the pin.
Page 711: Noise Eliminator
CHAPTER 14 PORT FUNCTIONS 14.5 Noise Eliminator 14.5.1 Interrupt pins A timing controller to guarantee the noise elimination times shown below is added to the pins that operate as NMI and valid edge inputs in port control mode. Signal input that changes in less than these elimination times is not accepted internally.
Page 712: Timer 10, Timer 11, Timer 3 Input Pins
CHAPTER 14 PORT FUNCTIONS 14.5.2 Timer 10, timer 11, timer 3 input pins Noise filtering using the clock sampling shown below is added to the pins that operate as valid edge inputs to timer 10, timer 11, and timer 3. A signal input that changes in less than these elimination times is not accepted internally. Noise Elimination Time Sampling Clock Timer 10...
Page 713 CHAPTER 14 PORT FUNCTIONS Figure 14-14. Example of Noise Elimination Timing Noise elimination clock Input signal 2 clocks 2 clocks 3 clocks 3 clocks 4 clocks 4 clocks 5 clocks 5 clocks Internal signal Timers 1 to 3 rising edge detection Timers 1 to 3 falling edge detection Caution If there are three or less noise elimination clocks while the timers 1 to 3 input signals...
Page 714 CHAPTER 14 PORT FUNCTIONS (1) Timer 10 noise elimination time selection register (NRC10) The NRC10 register is used to set the clock source of timer 10 input pin noise elimination times. This register can be read/written in 8-bit or 1-bit units. Caution The noise elimination function starts operating by setting the TM1CE0 bit of the TMC10 register to 1 (enabling count operations).
Page 715 CHAPTER 14 PORT FUNCTIONS (3) Timer 3 noise elimination time selection register (NRC3) The NRC3 register is used to set the clock source of timer 3 input pin noise elimination times. This register can be read/written in 8-bit or 1-bit units. Caution The noise elimination function starts operating by setting the TM3CE bit of the TMC30 register to 1 (enabling count operations).
Page 716: Timer 2 Input Pins
CHAPTER 14 PORT FUNCTIONS 14.5.3 Timer 2 input pins A noise eliminator using analog filtering and digital filtering using clock sampling are added to the timer 2 input pins. A signal input that changes in less than these elimination times is not accepted internally. Analog Filter Noise Digital Filter Elimination Time...
Page 717 CHAPTER 14 PORT FUNCTIONS (1) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5) The FEMn registers are used to specify timer 2 input pin filtering and to set the clock source of noise elimination times and the input valid edge. These registers can be read/written in 8-bit or 1-bit units.
Page 718 CHAPTER 14 PORT FUNCTIONS (2/2) Bit position Bit name Function 3, 2 EDGE01n, Specifies the INTP2n pin valid edge. EDGE00n EDGE01n EDGE00n Operation Note Interrupt due to INTCC2n Rising edge Falling edge Both rising and falling edges Note Specify when selecting INTCC2n according to match of TM20, TM21 and sub-channel compare registers (TMS01n, TMS00n bit settings) (n = 0 to 5).
Page 719: Chapter 15 Reset Function
CHAPTER 15 RESET FUNCTION When a low level is input to the RESET pin, there is a system reset and each hardware item of the V850E/IA1 is initialized to its initial status. When the RESET pin changes from low level to high level, reset status is released and the CPU starts program execution.
Page 720 CHAPTER 15 RESET FUNCTION (1) Reset signal acknowledgment RESET Analog Analog Analog delay delay delay Elimination as noise Internal system Note reset signal Reset acknowledgment Reset release Note The internal system reset signal continues in active status for a period of at least 4 system clocks after the timing of a reset release by the RESET pin.
Page 721: Initialization
CHAPTER 15 RESET FUNCTION 15.3 Initialization Initialize the contents of each register as needed within a program. Table 15-2 shows the initial values of the CPU, internal RAM, and on-chip peripheral I/O after reset. Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (1/6) On-Chip Hardware Register Name Initial Value After Reset...
Page 722 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (2/6) On-Chip Hardware Register Name Initial Value After Reset On-chip Interrupt/exception Signal edge selection register n (SESA1n) (n = 10, 11) peripheral control function Valid edge selection register (SESC) Timer 2 input filter mode register n (FEMn) (n = 0 to 5)
Page 723 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (3/6) On-Chip Hardware Register Name Initial Value After Reset On-chip Timer 2 Timer 2 clock stop register 0 (STOPTE0) 0000H peripheral Timer 2 clock stop register 0L (STOPTE0L) Timer 2 clock stop register 0H (STOPTE0H) Timer 2 count clock/control edge selection register 0 (CSE0) 0000H...
Page 724 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (4/6) On-Chip Hardware Register Name Initial Value After Reset On-chip Timer 3 Valid edge selection register (SESC) peripheral Timer 3 clock selection register (PRM03) Timer 3 noise elimination time selection register (NRC3) Timer 4 Timer 4 (TM4)
Page 725 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (5/6) On-Chip Hardware Register Name Initial Value After Reset On-chip Serial interface Transmit shift register Ln (TXSLn) (n = 1, 2) Undefined peripheral function (UART1, Prescaler mode register n (PRSMn) (n = 1, 2)
Page 726 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (6/6) On-Chip Hardware Register Name Initial Value After Reset On-chip A/D converter A/D voltage detection mode register n (ADETMn) (n = 0, 1) 0000H peripheral A/D voltage detection mode register nL (ADETMnL) (n = 0, 1)
Page 727: Chapter 16 Flash Memory
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) µ PD70F3116 is the flash memory version of the V850E/IA1 and it has an on-chip 256 KB flash memory configured as two 128 KB areas. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions.
Page 728 µ CHAPTER 16 FLASH MEMORY ( PD70F3116) When the flash programming adapter (FA-144GJ-8EU) is used for writing, connect the pins as follows. Table 16-1. Connection of V850E/IA1 Flash Programming Adapter (FA-144GJ-8EU) FA-144GJ-8EU V850E/IA1 Silk Name UART0 CSI0 Pin Name Pin No. Pin Name Pin No.
Page 729: Programming Environment
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.3 Programming Environment The following shows the environment required for writing programs to the flash memory of the V850E/IA1. Figure 16-1. Environment for Writing Program to Flash Memory Regulator RS-232C Axxxx Bxxxxx Regulator Cxxxxxx STATVE PG-FP4...
Page 730 µ CHAPTER 16 FLASH MEMORY ( PD70F3116) (2) CSI0 Transfer rate: up to 2 MHz (MSB first) Figure 16-3. Communication with Dedicated Flash Programmer (CSI0) Regulator Regulator Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 RESET RESET V850E/IA1 Dedicated flash programmer SCK0 Caution Supply the operating clock of the V850E/IA1 via the oscillator configured on the V850E/IA1 board using a resonator and a capacitor.
Page 731: Pin Connection
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.5 Pin Connection When performing on-board writing, install a connector on the target system to connect to the dedicated flash programmer. Also, install a function on-board to switch from the normal operation mode (single-chip modes 0, 1 or ROMless modes 0, 1) to the flash memory programming mode.
Page 732 µ CHAPTER 16 FLASH MEMORY ( PD70F3116) Figure 16-6. Conflict of Signals (Serial Interface Input Pin) V850E/IA1 Conflict of signals Dedicated flash programmer connection pin Input pin Other device Output pin In the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals the other device outputs.
Page 733: Reset Pin
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.5.3 RESET pin When connecting the reset signals of the dedicated flash programmer to the RESET pin, which is connected, to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator.
Page 734: Power Supply
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.5.8 Power supply Supply the power supply (V , AV , AV , AV , AV , CV , and CV ) the same as in REF0 REF1 Note normal operation mode. Connect V and GND of the dedicated flash programmer to V , and V of the dedicated flash programmer is provided with a power supply monitoring function).
Page 735: Flash Memory Programming Mode
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.6.2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer, set the V850E/IA1 in the flash memory programming mode. To switch to this mode, set the MODE0, MODE1, MODE2, and V pins before canceling reset.
Page 736: Communication Commands
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.6.4 Communication commands The V850E/IA1 communicates with the dedicated flash programmer by means of commands. A command sent from the dedicated flash programmer to the V850E/IA1 is called a “command”. The response signal sent from the V850E/IA1 to the dedicated flash programmer is called the “response command”.
Page 737: Flash Memory Programming By Self-Programming
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) The V850E/IA1 sends back response commands for the commands issued from the dedicated flash programmer. The following shows the response commands the V850E/IA1 sends out. Table 16-5. Response Commands Response Command Name Function ACK (acknowledge) Acknowledges command/data, etc.
Page 738: Self-Programming Function
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.2 Self-programming function µ PD70F3116 provides self-programming functions, as shown in Table 16-6. By combining these functions, erasing/writing flash memory becomes possible. Table 16-6. Function List Type Function Name Function Erase Area erase Erases the specified area.
Page 739: Hardware Environment
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) The self-programming interface is outlined below. Figure 16-13. Outline of Self-Programming Interface Application program RAM parameter Entry program Self-programming interface Device internal processing Flash-memory manipulation Flash memory 16.7.4 Hardware environment To write or erase the flash memory, a high voltage must be applied to the V pin.
Page 740 µ CHAPTER 16 FLASH MEMORY ( PD70F3116) The voltage applied to the V pin must satisfy the following conditions: • Hold the voltage applied to the V pin at 0 V in the normal operation mode and hold the V voltage only while the flash memory is being manipulated.
Page 741: Software Environment
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.5 Software environment The following conditions must be satisfied before using the entry program to call the device internal processing. Table 16-7. Software Environmental Conditions Item Description Location of entry Execute the entry program in memory other than the block 0 space and flash memory area. program The device internal processing cannot be directly called by the program that is executed on the flash memory.
Page 742: Self-Programming Function Number
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.6 Self-programming function number To identify a self-programming function, the following numbers are assigned to the respective functions. These function numbers are used as parameters when the device internal processing is called. Table 16-8. Self-Programming Function Number Function No.
Page 743: Calling Parameters
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.7 Calling parameters The arguments used to call the self-programming function are shown in the table below. In addition to these arguments, parameters such as the write time and erase time are set to the RAM parameters indicated by ep (r30). Table 16-9.
Page 744: Contents Of Ram Parameters
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.8 Contents of RAM parameters Reserve the following 48-byte area in the internal RAM or external RAM for the RAM parameters, and set the parameters to be input. Set the base addresses of these parameters to ep (r30). Table 16-10.
Page 745: Errors During Self-Programming
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.9 Errors during self-programming The following errors related to manipulation of the flash memory may occur during self-programming. An error occurs if the return value (r10) of each function is not 0. Table 16-11. Errors During Self-Programming Error Function Description...
Page 746: Area Number
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.11 Area number µ The area numbers and memory map of the PD70F3116 are shown below. Figure 16-16. Area Configuration 0 x 3 F F F F (End address of area 1) Area 1 (128 KB) 0 x 2 0 0 0 0 (Start address of area 1) 0 x 1 F F F F (End address of area 0)
Page 747: Flash Programming Mode Control Register (Flpmc)
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.12 Flash programming mode control register (FLPMC) The flash programming mode control register (FLPMC) is a register used to enable/disable writing to flash memory and to specify the self-programming mode. This register can be read/written in 8-bit or 1-bit units (the VPP bit (bit 2) is read-only). Cautions 1.
Page 748 µ CHAPTER 16 FLASH MEMORY ( PD70F3116) Setting data to the flash programming mode control register (FLPMC) is performed in the following sequence. <1> Disable interrupts (set the NP bit and ID bit of the PSW to 1). <2> Prepare the data to be set in the specific register in a general-purpose register. <3>...
Page 749: Calling Device Internal Processing
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.13 Calling device internal processing This section explains the procedure to call the device internal processing from the entry program. Before calling the device internal processing, make sure that all the conditions of the hardware and software environments are satisfied and that the necessary arguments and RAM parameters have been set.
Page 750 µ CHAPTER 16 FLASH MEMORY ( PD70F3116) (4) Program example An example of a program in which the entry program is executed as a subroutine is shown below. In this example, the return address is saved to the stack and then the device internal processing is called. This program must be located in memory other than the block 0 space and flash memory area.
Page 751 µ CHAPTER 16 FLASH MEMORY ( PD70F3116) (5) Internal manipulation setup parameter µ If the self-programming mode is switched to the normal operation mode, the PD70F3116 must wait for 100 µ s before it accesses the flash memory. In the program example in (4) above, the elapse of this wait time is ensured by setting ISETUP to “130”...
Page 752: Erasing Flash Memory Flow
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.14 Erasing flash memory flow The procedure to erase the flash memory is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-17. Erasing Flash Memory Flow Erase Set RAM parameter.
Page 753: Continuous Writing Flow
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.15 Continuous writing flow The procedure to write data all at once to the flash memory by using the function to continuously write data in word units is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure.
Page 754: Internal Verify Flow
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.16 Internal verify flow The procedure of internal verification is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-19. Internal Verify Flow Internal verify Set RAM parameter.
Page 755: Acquiring Flash Information Flow
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.17 Acquiring flash information flow The procedure to acquire the flash information is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-20. Acquiring Flash Information Flow Acquiring flash information Set RAM parameter.
Page 756: Self-Programming Library
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.7.18 Self-programming library V850 Series Flash Memory Self-Programming User’s Manual is available for reference when executing self- programming. In this manual, the library uses the self-programming interface of the V850 Series and can be used in C as a utility and as part of the application program.
Page 757 µ CHAPTER 16 FLASH MEMORY ( PD70F3116) The configuration of the self-programming library is outlined below. Figure 16-22. Outline of Self-Programming Library Configuration Application program C interface Self-programming library Entry program RAM parameter Self-programming interface Device internal processing Flash memory manipulation Flash memory User’s Manual U14492EJ5V0UD...
Page 758: How To Distinguish Flash Memory And Mask Rom Versions
µ CHAPTER 16 FLASH MEMORY ( PD70F3116) 16.8 How to Distinguish Flash Memory and Mask ROM Versions µ µ It is possible to distinguish a flash memory version ( PD70F3116) and a mask ROM version ( PD703116) by means of software, using the methods shown below. <1>...
Page 759: Chapter 17 Turning On/Off Power
CHAPTER 17 TURNING ON/OFF POWER The V850E/IA1 has three types of power supply pins: 3.3 V power supply pins for internal units (V and CV ), 5 Note V power supply pins for external pins (V and AV ), and a flash programming power supply pin (V This chapter explains the I/O pin status when power is turned ON/OFF.
Page 760 CHAPTER 17 TURNING ON/OFF POWER [Other timing] • If power is supplied to the V and AV pins before the voltage on the V pins rises to the level at which the Note operation is guaranteed (3.0 to 3.6 V), the status of the I/O pin is undefined until the voltage on the V reaches 3.0 V.
Page 761: Chapter 18 Electrical Specifications
CHAPTER 18 ELECTRICAL SPECIFICATIONS 18.1 Normal Operation Mode Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.5 to +4.6 Power supply voltage −0.5 to +7.0 −0.5 to +4.6 −0.5 to +0.5 −0.5 to V Note 1 + 0.5 −0.5 to +0.5 −0.5 to V Note 2...
Page 762 CHAPTER 18 ELECTRICAL SPECIFICATIONS Notes 1. Be sure not to exceed the absolute maximum ratings (MAX. value) of each power supply voltage. µ CLK_DBG, SYNC, AD0_DBG to AD3_DBG pins ( PD70F3116 only) Make sure that the following conditions of the V voltage application timing are satisfied when the flash memory is written.
Page 763 CHAPTER 18 ELECTRICAL SPECIFICATIONS Capacitance (T = 25°C, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance = 1 MHz I/O capacitance Unmeasured pins returned to 0 V. Output capacitance Operating Conditions Operation Mode Internal System Clock Frequency (f Operating Ambient Power Supply Voltage Temperature (T...
Page 764 CHAPTER 18 ELECTRICAL SPECIFICATIONS µ = −40 to +85°C: Clock Oscillator Characteristics (T PD703116, 703116(A), 70F3116, 70F3116(A), = −40 to +110°C: µ PD703116(A1), 70F3116(A1)) (a) Ceramic resonator or crystal resonator connection Parameter Symbol Conditions MIN. TYP. MAX. Unit Oscillation frequency Remarks 1.
Page 765 CHAPTER 18 ELECTRICAL SPECIFICATIONS Recommended Oscillator Constant (a) Ceramic resonator µ = −40 to +85°C: (i) Murata Mfg. Co., Ltd (T PD703116, 703116(A), 70F3116, 70F3116(A), µ = −40 to +110°C: PD703116(A1), 70F3116(A1)) Type Product Name Oscillation Recommended Circuit Constant Recommended Voltage Frequency Range (MHz)
Page 766 CHAPTER 18 ELECTRICAL SPECIFICATIONS µ DC Characteristics (T = –40 to +85°C: PD703116, 703116(A), 70F3116, 70F3116(A), µ = –40 to +110°C: PD703116(A1), 70F3116(A1), = CV = 3.0 to 3.6 V, V = 5 V ±0.5 V, V = CV = 0 V) (1/2) Parameter Symbol Conditions...
Page 767 CHAPTER 18 ELECTRICAL SPECIFICATIONS µ DC Characteristics (T = –40 to +85°C: PD703116, 703116(A), 70F3116, 70F3116(A), µ = –40 to +110°C: PD703116(A1), 70F3116(A1), = CV = 3.0 to 3.6 V, V = 5 V ±0.5 V, V = CV = 0 V) (2/2) Parameter Symbol Conditions...
Page 768 CHAPTER 18 ELECTRICAL SPECIFICATIONS µ = –40 to +85°C: Data Retention Characteristics (T PD703116, 703116(A), 70F3116, 70F3116(A), µ = –40 to +110°C: PD703116(A1), 70F3116(A1)) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage STOP mode, V DDDR DDDR STOP mode, V = HV DDDR DDDR...
Page 769 CHAPTER 18 ELECTRICAL SPECIFICATIONS µ = –40 to +85°C: AC Characteristics (T PD703116, 703116(A), 70F3116, 70F3116(A), µ = –40 to +110°C: PD703116(A1), 70F3116(A1), = 5 V ±0.5 V, V = CV = 3.0 to 3.6 V, V = CV = 0 V, output pin load capacitance: C = 50 pF) AC test input test points...
Page 770 CHAPTER 18 ELECTRICAL SPECIFICATIONS AC test output test points Pins other than (b) below 0.8V 0.8V Test points 0.2V 0.2V µ AD0_DBG to AD3_DBG, TRIG_DBG pins ( PD70F3116 only) 0.8V 0.8V Test points 0.2V 0.2V Load conditions (Device under test) = 50 pF Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert a buffer or other element to reduce the device’s load capacitance to 50 pF or lower.
Page 771 CHAPTER 18 ELECTRICAL SPECIFICATIONS (1) Clock timing (1/2) µ = –40 to +85°C: PD703116, 703116(A), 70F3116, 70F3116(A), µ = –40 to +110°C: PD703116(A1), 70F3116(A1), = 5 V ±0.5 V, V = CV = 3.0 to 3.6 V, V = CV = 0 V, output pin load capacitance: C = 50 pF)
Page 772 CHAPTER 18 ELECTRICAL SPECIFICATIONS (1) Clock timing (2/2) <1> <2> <3> <5> <4> (PLL mode) <1> <2> <3> <4> <5> (direct mode) <11> <11> CLKOUT (output) <9> <10> <7> <8> <6> (2) Output waveform (except for CLKOUT) µ = –40 to +85°C: PD703116, 703116(A), 70F3116, 70F3116(A), µ...
Page 773 CHAPTER 18 ELECTRICAL SPECIFICATIONS (3) Reset timing µ = –40 to +85°C: PD703116, 703116(A), 70F3116, 70F3116(A), µ = –40 to +110°C: PD703116(A1), 70F3116(A1), = 5 V ±0.5 V, V = CV = 3.0 to 3.6 V, V = CV = 0 V, C = 50 pF) Parameter Symbol...
Page 774 CHAPTER 18 ELECTRICAL SPECIFICATIONS (4) Multiplex bus timing µ = –40 to +85°C: (a) CLKOUT asynchronous (T PD703116, 703116(A), 70F3116, 70F3116(A), µ = –40 to +110°C: PD703116(A1), 70F3116(A1), = 5 V ±0.5 V, V = CV = 3.0 to 3.6 V, V = CV = 0 V, output pin load capacitance: C...
Page 775 CHAPTER 18 ELECTRICAL SPECIFICATIONS Remarks 1. T = t 2. w: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 3. i: Number of idle states inserted after the read cycle (0 or 1) 4.
Page 776 CHAPTER 18 ELECTRICAL SPECIFICATIONS (c) Read cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <45> A16 to A23 (output) CS0 to CS7 (output) <19> <49> <50> <46> Hi-Z AD0 to AD15 (I/O) Address Data <47> <47> <16> <17> <22> ASTB (output) <27>...
Page 777 CHAPTER 18 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <45> A16 to A23 (output) CS0 to CS7 (output) <51> AD0 to AD15 (I/O) Address Data <47> <47> <16> <17> ASTB (output) <27> <24> <48> <48> <28> <21>...
Page 778 CHAPTER 18 ELECTRICAL SPECIFICATIONS (e) Bus hold CLKOUT (output) <54> <54> <55> <39> HLDRQ (input) <56> <56> <43> <44> HLDAK (output) <41> <42> <40> <57> Hi-Z A16 to A23 (output) CS0 to CS7 (output) Data Hi-Z AD0 to AD15 (I/O) Hi-Z ASTB (output) Hi-Z...
Page 779 CHAPTER 18 ELECTRICAL SPECIFICATIONS (5) Interrupt timing µ = –40 to +85°C: PD703116, 703116(A), 70F3116, 70F3116(A), µ = –40 to +110°C: PD703116(A1), 70F3116(A1), = 5 V ±0.5 V, V = CV = 3.0 to 3.6 V, V = CV = 0 V, C = 50 pF) Parameter Symbol...
Page 780 CHAPTER 18 ELECTRICAL SPECIFICATIONS (6) Timer input timing µ = –40 to +85°C: PD703116, 703116(A), 70F3116, 70F3116(A), µ = –40 to +110°C: PD703116(A1), 70F3116(A1), = 5 V ±0.5 V, V = CV = 3.0 to 3.6 V, V = CV = 0 V, C = 50 pF) Parameter...
Page 781 CHAPTER 18 ELECTRICAL SPECIFICATIONS (7) Timer operating frequency µ = –40 to +85°C: PD703116, 703116(A), 70F3116, 70F3116(A), µ = –40 to +110°C: PD703116(A1), 70F3116(A1), = 5 V ±0.5 V, V = CV = 3.0 to 3.6 V, V = CV = 0 V, output pin load capacitance: C = 50 pF)
Page 782 CHAPTER 18 ELECTRICAL SPECIFICATIONS (8) CSI timing (2/2) (b) Slave mode µ = –40 to +85°C: PD703116, 703116(A), 70F3116, 70F3116(A), = –40 to +110°C: µ PD703116(A1), 70F3116(A1), = 5 V ±0.5 V, V = CV = 3.0 to 3.6 V, V = CV = 0 V, output pin load capacitance: C...
Page 783 CHAPTER 18 ELECTRICAL SPECIFICATIONS (9) UART0 timing µ = –40 to +85°C: PD703116, 703116(A), 70F3116, 70F3116(A), µ = –40 to +110°C: PD703116(A1), 70F3116(A1), = 5 V ±0.5 V, V = CV = 3.0 to 3.6 V, V = CV = 0 V, output pin load capacitance: C = 50 pF) Parameter...
Page 784 CHAPTER 18 ELECTRICAL SPECIFICATIONS (10) UART1, UART2 timing (2/2) (b) Clocked slave mode µ = –40 to +85°C: PD703116, 703116(A), 70F3116, 70F3116(A), = –40 to +110°C: µ PD703116(A1), 70F3116(A1), = 5 V ±0.5 V, V = CV = 3.0 to 3.6 V, V = CV = 0 V, output pin load capacitance: C...
Page 785 CHAPTER 18 ELECTRICAL SPECIFICATIONS µ (11) NBD timing ( PD70F3116 only) = 0 to +40°C, V = CV = 3.0 to 3.6 V, V = 5 V ±0.5 V, V = CV = 0 V, output pin load capacitance: C = 100 pF) Parameter Symbol...
Page 786 CHAPTER 18 ELECTRICAL SPECIFICATIONS A/D Converter Characteristics µ = –40 to +85°C: PD703116, 703116(A), 70F3116, 70F3116(A), µ = −40 to +110°C: PD703116(A1), 70F3116(A1), = 5 V ±0.5 V, AV = CV = 3.0 to 3.6 V, AV = CV = 0 V, C = 50 pF) Parameter Symbol...
Page 787: Flash Memory Programming Mode ( Pd70F3116 Only)
CHAPTER 18 ELECTRICAL SPECIFICATIONS µ 18.2 Flash Memory Programming Mode ( PD70F3116 only) Basic Characteristics (T = 0 to 70°C (during rewrite), µ = −40 to +85°C (except during rewrite): PD70F3116, 70F3116(A), µ = −40 to +110°C (except during rewrite): PD70F3116(A1), = 5 V ±0.5 V, V = CV...
Page 788 CHAPTER 18 ELECTRICAL SPECIFICATIONS Serial Write Operation Characteristics (T = 0 to 70°C, V = CV = 3.0 to 3.6 V, = 5 V ±0.5 V, V = CV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ ↑...
Page 789: Chapter 19 Package Drawing
CHAPTER 19 PACKAGE DRAWING 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 22.0±0.2 its true position (T.P.) at maximum material condition. 20.0±0.2 20.0±0.2 22.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.)
Page 790: Chapter 20 Recommended Soldering Conditions
Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products with -A at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended above, consult an NEC Electronics sales representative.
Page 791: Appendix A Notes On Target System Design
APPENDIX A NOTES ON TARGET SYSTEM DESIGN The following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. Design your system making allowances for conditions such as the form of parts mounted on the target system based on this configuration.
Page 792: Appendix B Register Index
APPENDIX B REGISTER INDEX (1/11) Symbol Register Name Unit Page ADCR00 A/D conversion result register 00 ADCR01 A/D conversion result register 01 ADCR02 A/D conversion result register 02 ADCR03 A/D conversion result register 03 ADCR04 A/D conversion result register 04 ADCR05 A/D conversion result register 05 ADCR06...
Page 793 APPENDIX B REGISTER INDEX (2/11) Symbol Register Name Unit Page ASIM10 Asynchronous serial interface mode register 10 UART1 ASIM11 Asynchronous serial interface mode register 11 UART1 ASIM20 Asynchronous serial interface mode register 20 UART2 ASIM21 Asynchronous serial interface mode register 21 UART2 ASIS0 Asynchronous serial interface status register 0...
Page 794 APPENDIX B REGISTER INDEX (3/11) Symbol Register Name Unit Page CANIC1 Interrupt control register INTC CANIC2 Interrupt control register INTC CANIC3 Interrupt control register INTC CC100 Capture/compare register 100 TM10 CC101 Capture/compare register 101 TM10 CC10IC0 Interrupt control register INTC CC10IC1 Interrupt control register INTC...
Page 795 APPENDIX B REGISTER INDEX (4/11) Symbol Register Name Unit Page CM011 Compare register 011 TM01 CM012 Compare register 012 TM01 CM013 Compare register 013 TM01 CM03IC0 Interrupt control register INTC CM03IC1 Interrupt control register INTC CM100 Compare register 100 TM10 CM101 Compare register 101 TM10...
Page 796 APPENDIX B REGISTER INDEX (5/11) Symbol Register Name Unit Page CVSE40 Timer 2 subchannel 4 sub capture/compare register CVSE50 Timer 2 subchannel 5 capture/compare register DADC0 DMA addressing control register 0 DMAC DADC1 DMA addressing control register 1 DMAC DADC2 DMA addressing control register 2 DMAC DADC3...
Page 797 APPENDIX B REGISTER INDEX (6/11) Symbol Register Name Unit Page DTFR3 DMA trigger factor register 3 DMAC DTM00 Dead-time timer 00 TM00 DTM01 Dead-time timer 01 TM00 DTM02 Dead-time timer 02 TM00 DTM10 Dead-time timer 10 TM01 DTM11 Dead-time timer 11 TM01 DTM12 Dead-time timer 12...
Page 798 APPENDIX B REGISTER INDEX (7/11) Symbol Register Name Unit Page M_DATAn0 to CAN message data registers n0 to n7 (n = 00 to 31) FCAN M_DATAn7 M_DLC00 to CAN message data length registers 00 to 31 FCAN M_DLC31 M_IDH00 to CAN message ID registers H00 to H31 FCAN M_IDH31...
Page 799 APPENDIX B REGISTER INDEX (8/11) Symbol Register Name Unit Page Port 4 Port Port CM Port Port CS Port Port CT Port Port DH Port Port DL Port PDLH Port DLH Port PDLL Port DLL Port PFC1 Port 1 function control register Port PFC2 Port 2 function control register...
Page 800 APPENDIX B REGISTER INDEX (9/11) Symbol Register Name Unit Page PRM10 Prescaler mode register 10 TM10 PRM11 Prescaler mode register 11 TM11 PRSCM1 Prescaler compare register 1 UART1 PRSCM2 Prescaler compare register 2 UART2 PRSCM3 Prescaler compare register 3 CSI0, CSI1 PRSM1 Prescaler mode register 1 UART1...
Page 801 APPENDIX B REGISTER INDEX (10/11) Symbol Register Name Unit Page SOTBF1 Clocked serial interface initial transmit buffer register 1 CSI1 SOTBFL0 Clocked serial interface initial transmit buffer register L0 CSI0 SOTBFL1 Clocked serial interface initial transmit buffer register L1 CSI1 SOTBL0 Clocked serial interface transmit buffer register L0 CSI0...
Page 802 APPENDIX B REGISTER INDEX (11/11) Symbol Register Name Unit Page TMC01H Timer control register 01H TM01 TMC01L Timer control register 01L TM01 TMC10 Timer control register 10 TM10 TMC11 Timer control register 11 TM11 TMC30 Timer control register 30 TMC31 Timer control register 31 TMC4 Timer control register 4...
Page 803: Appendix C Instruction Set List
APPENDIX C INSTRUCTION SET LIST C.1 Functions (1) Symbols used in operand descriptions Symbol Explanation reg1 General-purpose register (Used as source register) reg2 General-purpose register (Usually used as destination register. Used as source register in some instructions.) reg3 General-purpose register (Usually stores remainder of division result or higher 32 bits of multiplication result.) bit#3 3-bit data for bit number specification...
Page 804 APPENDIX C INSTRUCTION SET LIST (3) Symbols used in operations Symbol Explanation ← Assignment GR [ ] General-purpose register SR [ ] System register zero-extend (n) Zero-extend n to word length. sign-extend (n) Sign-extend n to word length. load-memory (a, b) Read data of size “b”...
Page 805 APPENDIX C INSTRUCTION SET LIST (5) Symbols used in flag operations Symbol Explanation (Blank) No change Clear to 0. × Set or cleared according to result. Previously saved value is restored. (6) Condition codes Condition Name Condition Code Condition Expression Explanation (cond) (cccc)
Page 806: Instruction Set (Alphabetical Order)
APPENDIX C INSTRUCTION SET LIST C.2 Instruction Set (Alphabetical Order) (1/5) Mnemonic Operands Opcode Operation Execution Clock Flags × × × × r r r r r 0 0 1 1 1 0 R R R R R GR[reg2] ← GR[reg2] + GR[reg1] reg1, reg2 ×...
Page 807 APPENDIX C INSTRUCTION SET LIST (2/5) Mnemonic Operands Opcode Operation Execution Clock Flags sp ← sp + zero-extend (imm5 logically shift left by 2) DISPOSE imm5, list12 0 0 0 0 0 1 1 0 0 1 i i i i i L GR[reg in list12] ←...
Page 808 APPENDIX C INSTRUCTION SET LIST (3/5) Mnemonic Operands Opcode Operation Execution Clock Flags adr ← GR[reg1] + sign-extend (disp16) LD.W disp16[reg1], r r r r r 1 1 1 0 0 1 R R R R R Note 11 GR[reg2] ← Load-memory (adr, Word) reg2 d d d d d d d d d d d d d d d 1 Note 8...
Page 809 APPENDIX C INSTRUCTION SET LIST (4/5) Mnemonic Operands Opcode Operation Execution Clock Flags RETI if PSW.EP = 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 ← EIPC then PC 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 PSW ←...
Page 810 APPENDIX C INSTRUCTION SET LIST (5/5) Mnemonic Operands Opcode Operation Execution Clock Flags r r r r r 0 0 0 0 1 1 1 d d d d adr ← ep + zero-extend (disp5) SLD.HU disp5[ep], Note 9 GR[reg2] ← zero-extend (Load-memory (adr, reg2 Notes 18, 20 Halfword))
Page 811 APPENDIX C INSTRUCTION SET LIST Notes 1. dddddddd is the higher 8 bits of disp9. 4 if there is an instruction to overwrite the contents of the PSW immediately before If there is no wait state (3 + number of read access wait states) n is the total number of load registers in list12.
Page 812: Appendix D Revision History
APPENDIX D REVISION HISTORY D.1 Major Revisions in This Edition (1/2) Page Description • Addition of the following lead-free products Throughout µ PD703116GJ-xxx-UEN-A, 70F3116GJ-UEN-A, 703116GJ(A)-xxx-UEN-A, 70F3116GJ(A)-UEN-A, 703116GJ(A1)-xxx-UEN-A, 70F3116GJ(A1)-UEN-A p. 21 Change of number of instructions in 1.2 Features p. 51 Addition of Note to Table 3-2 System Register Numbers pp.
Page 813 APPENDIX D REVISION HISTORY (2/2) Page Description Addition of 9.1.5 (4) [Output waveform width in respect to set value] (d) When BFCMnx = 0000H is set p. 281 while DTMnx = 000H or TM0CEDn bit = 1 Addition of 9.1.5 (4) [Output waveform width in respect to set value] (e) When BFCMnx = CM0n3 = a is p.
Page 814: Revision History Up To Previous Edition
APPENDIX D REVISION HISTORY D.2 Revision History up to Previous Edition The following table shows the revision history up to the previous editions. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. (1/13) Edition Major Revision from Previous Edition Applied to:...
Page 815 APPENDIX D REVISION HISTORY (2/13) Edition Major Revision from Previous Edition Applied to: Addition of Caution in 4.3.1 (1) Chip area selection control registers 0, 1 (CSC0, CSC1) CHAPTER 4 edition BUS CONTROL Modification of description in table in 4.5.1 Number of access clocks FUNCTION Addition of Caution in 4.6.1 (2) Address wait control register (AWC) Modification of timing chart in Figure 4-2 Example of Wait Insertion...
Page 816 APPENDIX D REVISION HISTORY (3/13) Edition Major Revision from Previous Edition Applied to: Addition of Caution in 7.3.8 (3) Valid edge selection register (SESC) CHAPTER 7 edition INTERRUPT/ Addition of Caution and addition of Caution in bit description in 7.3.8 (4) Timer 2 input EXCEPTION filter mode registers 0 to 5 (FEM0 to FEM5) PROCESSING...
Page 817 APPENDIX D REVISION HISTORY (4/13) Edition Major Revision from Previous Edition Applied to: Addition of Caution, modification of bit names and bit descriptions, and addition of Figures CHAPTER 9 edition 9-9 to 9-14 in 9.1.4 (6) PWM software timing output registers 0, 1 (PSTO0, PSTO1) TIMER/COUNTER FUNCTION (REAL- Addition of Remark in 9.1.5 Operation...
Page 818 APPENDIX D REVISION HISTORY (5/13) Edition Major Revision from Previous Edition Applied to: Modification of Figure 9-88 Compare Operation Example CHAPTER 9 edition TIMER/COUNTER Addition of Note and deletion of Caution in Figure 9-95 Cycle Measurement Operation FUNCTION (REAL- Timing Example TIME PULSE UNIT) Modification of Figure 9-97 Example of Timing During TM4 Operation Modification of bit names in 9.5.4 (1) Timer control register 4 (TMC4)
Page 819 APPENDIX D REVISION HISTORY (6/13) Edition Major Revision from Previous Edition Applied to: Modification of description on bits that can be manipulated in 10.3.7 (2) (c) Prescaler CHAPTER 10 edition compare registers 1, 2 (PRSCM1, PRSCM2) SERIAL INTERFACE Addition of 10.3.7 (3) Allowable baud rate range during reception FUNCTION Addition of 10.3.7 (4) Transfer rate in 2-frame continuous reception Modification of bit names in 10.4.3 (1) Clocked serial interface mode registers 0, 1...
Page 820 APPENDIX D REVISION HISTORY (7/13) Edition Major Revision from Previous Edition Applied to: Addition of Caution and deletion of part of bit description in 11.10 (19) CAN1 address CHAPTER 11 edition mask a registers L and H (C1MASKLa and C1MASKHa) FCAN CONTROLLER Addition of Caution and addition of bit description in 11.10 (20) CAN1 control register...
Page 821 APPENDIX D REVISION HISTORY (8/13) Edition Major Revision from Previous Edition Applied to: Modification of description on bits that can be manipulated and modification of bit names in CHAPTER 13 A/D edition 13.3 (3) A/D voltage detection mode registers 0 and 1 (ADETM0, ADETM1) CONVERTER Addition of description in 13.10.4 (1) HALT mode Modification of description in 13.10.4 (2) IDLE mode, software STOP mode...
Page 822 APPENDIX D REVISION HISTORY (9/13) Edition Major Revision from Previous Edition Applied to: Addition of initial value 00H and modification of Caution in 16.7.12 Flash programming CHAPTER 16 edition mode control register (FLPMC) FLASH MEMORY µ PD70F3116) Addition of 16.7.13 Calling device internal processing Addition of 16.7.14 Erasing flash memory flow Addition of 16.7.15 Continuous writing flow Addition of 16.7.16 Internal verify flow...
Page 823 APPENDIX D REVISION HISTORY (10/13) Edition Major Revision from Previous Edition Applied to: Addition of Caution to 7.3.4 Interrupt control register (xxICn) CHAPTER 7 edition INTERRUPT/ EXCEPTION PROCESSING FUNCTION Addition of Caution to 7.3.6 In-service priority register (ISPR) Modification of description in Remark in 9.1.5 (2) PWM mode 0: Triangular wave CHAPTER 9 modulation (right-left symmetric waveform control) TIMER/COUNTER...
Page 824 APPENDIX D REVISION HISTORY (11/13) Edition Major Revision from Previous Edition Applied to: Addition of Caution 2 to 6.3.1 (1) DMA source address registers 0H to 3H (DSA0H to CHAPTER 6 DMA edition DSA3H) FUNCTIONS (DMA CONTROLLER) Addition of Caution 2 to 6.3.2 (1) DMA destination address registers 0H to 3H (DDA0H to DDA3H) Addition of Cautions 1 and 2 to 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)
Page 825 APPENDIX D REVISION HISTORY (12/13) Edition Major Revision from Previous Edition Applied to: Addition of Caution to Table 11-2 Configuration of Messages and Buffers CHAPTER 11 edition FCAN Addition of description to 11.5 Message Processing CONTROLLER Addition of description to Note in Figure 11-21 Nominal Bit Time Modification of description in 11.10 (2) CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) and addition of Note Modification of description in 11.10 (3) CAN message control registers 00 to 31...
Page 826 APPENDIX D REVISION HISTORY (13/13) Edition Major Revision from Previous Edition Applied to: Addition of description to 11.16 Cautions on Use CHAPTER 11 edition FCAN CONTROLLER Addition of 14.4 Operation of Port Function CHAPTER 14 PORT FUNCTIONS Addition of Caution to 18.1 (4) (c) Read cycle (CLKOUT synchronous/asynchronous, 1 CHAPTER 18 wait) ELECTRICAL...

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V850e/ia1 Upd703116(a)Upd703116(a1)Upd70f3116 Upd70f3116(a)Upd70f3116(a1)

NEC UPD703116 User Manual

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Function

Chapter 4 Bus Control Function

Chapter 5 Memory Access Control Function

Chapter 6 Dma Functions (Dma Controller)

Chapter 7 Interrupt/Exception Processing Function

Chapter 8 Clock Generation Function

Chapter 9 Timer/Counter Function

Chapter 10 Serial Interface Function

Chapter 11 Fcan Controller

Chapter 12 Nbd Function

Chapter 13 A/D Converter

Chapter 14 Port Functions

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Summary of Contents for NEC UPD703116