Page 1 Preliminary User’s Manual V850E/Dx3 32-bit Single-Chip Microcontroller Hardware µPD70F3420, µPD703420 µPD70F3421, µPD703421 µPD70F3422, µPD703422 µPD70F3423 µPD70F3424 µPD70F3425 µPD70F3426 µPD70F3427 Document No. U17566EE1V2UM00 Date Published 18/7/06 © NEC Electronics 2006 Printed in Germany Downloaded from Elcodis.com electronic components distributor...
Page 2 V850E/Dx3 Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 3 Notes for CMOS Devices 1. Precaution against ESD for semiconductors Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 4 “quality assurance program” for a specific application. The recommended applications of NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard":...
Page 5 The quality grade of NEC Electronics products is “Standard” unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact NEC Electronics sales representative in advance to determine NEC Electronics 's willingness to support a given application.
Page 6 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 7 Preface Readers This manual is intended for users who want to understand the functions of the concerned microcontrollers. Purpose This manual presents the hardware manual for the concerned microcontrollers. Organization This system specification describes the following sections: • Pin function •...
Page 8 V850E/Dx3 Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 9: Table Of Contents
Table of Contents Chapter 1 Introduction ..........23 1.1 General .
Page 10 Table of Contents 2.6 Pin Functions in Reset and Power Save Modes ... . 97 2.7 Recommended connection of unused pins ....98 2.8 Package Pins Assignment .
Page 11 Table of Contents 4.3.3 Power save mode activation ........179 4.3.4 CPU operation after power save mode release .
Page 12 Table of Contents 6.2 Flash Self-Programming ....... . . 234 6.2.1 Flash self-programming registers .
Page 13 Table of Contents 8.2 Peripheral and CPU Clock Settings ..... . . 310 8.3 DMAC Registers ......... 312 8.3.1 DMA Source address registers .
Page 14 Table of Contents 11.4 TMP Registers ......... . . 346 11.5 Operation .
Page 15 Table of Contents 14.3 Watch Timer Operation ........485 14.3.1 Timing of steady operation .
Page 16 Table of Contents 17.1 Features ..........541 17.2 Configuration .
Page 17 Table of Contents 18.10 Error Detection ......... . . 620 18.11 Extension Code .
Page 18 Table of Contents 19.9 Transition from Initialization Mode to Operation Mode ..713 19.9.1 Resetting error counter CNERC of CAN module ....714 19.10 Message Reception .
Page 19 Table of Contents 20.6 How to Read A/D Converter Characteristics Table ..790 Chapter 21 Stepper Motor Controller/Driver (Stepper-C/D) ..795 21.1 Overview ..........795 21.1.1 Driver overview .
Page 20 Table of Contents 24.3 Sound Generator Operation ......849 24.3.1 Generating the tone ......... . 849 24.3.2 Generating the volume information .
Page 21 28.3.3 N-Wire activation by RESET pin ....... . . 885 28.4 Connection to N-Wire Emulator .
Page 22 Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 23: Chapter 1 Introduction
Chapter 1 Introduction The V850E/Dx3 is a product line in NEC Electronics’ V850 family of single-chip microcontrollers designed for automotive applications. 1.1 General The V850E/Dx3 single-chip microcontroller devices make the performance gains attainable with 32-bit RISC-based controllers available for embedded control applications.
Page 24: Features Summary
1.2 Features Summary The following table provides a quick summary of the most outstanding features. Table 1-1 V850E/Dx3 features summary (1/4) Core V850E1 Number of instructions • 19.841 ns (@ φ = 50.4 MHz) (µPD70F3424, Minimum instruction execution time µPD70F3425, µPD70F3426, µPD70F3427)
Page 25 Introduction Chapter 1 Table 1-1 V850E/Dx3 features summary (2/4) Internal data RAM Size • 84 KB (µPD70F3426) • 60 KB (µPD70F3427) • 32KB (µPD70F3425) • 24 KB (µPD70F3424) • 20 KB (µPD70F3423) • 16 KB (µPD70(F)3422) • 12 KB (µPD70(F)3421) •...
Page 26 Chapter 1 Introduction Table 1-1 V850E/Dx3 features summary (3/4) A/D Converter Number of channels • 16 (µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427) • 12 (µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423) Resolution 10-bit Conversion modes • Continuous select mode • Continuous scan mode • Timer trigger mode •...
Page 27 Introduction Chapter 1 Table 1-1 V850E/Dx3 features summary (4/4) Sound Generator Number of channels Volume 9-bit volume level accuracy Sound frequency 245 Hz to 6 KHz with min. resolution of ± 20 Hz Sound duration 256 steps Interrupts and exceptions...
Page 28: Product Series Overview
Chapter 1 Introduction Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 29 Chapter 1 Introduction Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 30: Description
16 KB Unit On-Chip Debug Unit CRXD0, CRXD1 2 x CAN CTXD0, CTXD1 SDA0, SDA1 2 x I SCL0, SCL1 Bridge NPB (NEC Peripheral Bus) Control Interfaces Note 3 ANI0-ANI11 Ports 10-bit ADC 16/12 Note 3 ANI12-ANI15 channels SM11 to SM14...
Page 31 Introduction Chapter 1 Table 1-3 summarizes the different features of the of the V850E/DJ3 µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423, µPD70F3424, µPD70F3425, µPD70F3426 microcontrollers, marked as “Notes” in Figure 1-1. Table 1-3 Feature set differences Note Feature ‘F3426 ‘F3425 ‘F3424 ‘F3423 ‘F3422 ‘3422 ‘F3421 ‘3421...
Page 32 On-Chip Debug Unit WAIT CRXD0, CRXD1 2 x CAN BCLK CTXD0, CTXD1 SDA0, SDA1 2 x I SCL0, SCL1 Bridge NPB (NEC Peripheral Bus) Control Interfaces Ports 10-bit ADC ANI0-ANI15 channels SM11 to SM14 SM21 to SM24 Stepper SM31 to SM34...
Page 33 Structure of the This manual explains how to use the V850E/Dx3 microcontroller devices. It manual provides comprehensive information about the building blocks, their features, and how to set registers in order to enable or disable specific functions.
Page 34: Ordering Information
“Power Supply Scheme“ on page 855 “Reset“ on page 861 “Voltage Comparator“ on page 871 • Auxiliary functions “On-Chip Debug Unit“ on page 877 1.5 Ordering Information Table 1-4 V850E/Dx3 ordering information NEC order code Pin/package Memory size Remarks UPD703420GJ(A)-GAE-QS-AX 144 pin LQFP 128 KB ROM –...
Page 35: Chapter 2 Pin Functions
Chapter 2 Pin Functions This chapter lists the ports of the microcontroller. It presents the configuration of the ports for alternative functions. Noise elimination on input signals is explained and a recommendation for the connection of unused pins is given at the end of the chapter.
Page 36: Description
Chapter 2 Pin Functions 2.1.1 Description This microcontroller has the port groups shown below. Port group 0 Port group 7 P715 Port group 1 Port group 8 Port group 2 Port group 9 P100 Port group 3 Port group 10 P107 P110 Port group 4...
Page 37 Pin Functions Chapter 2 Port group overview Table 2-1 gives an overview of the port groups. For each port group it shows the supported functions in port mode and in alternative mode. Any port group can operate in 8-bit or 1-bit units. Port group 7 can additionally operate in 16-bit units.
Page 38 Chapter 2 Pin Functions Table 2-1 Functions of each port group (2/2) Port Function group Port mode Alternative mode name 8-bit input/output • Clocked Serial Interface CSIB2 data/clock line (µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427 only) • LCD controller segment signal output (µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 only) •...
Page 39: Terms
Pin Functions Chapter 2 2.1.2 Terms In this section, the following terms are used: • Pin Denotes the physical pin. Every pin is uniquely denoted by its pin number. A pin can be used in several modes. Depending on the selected mode, a pin name is allocated to the pin.
Page 40: Port Group Configuration Registers
Chapter 2 Pin Functions 2.2 Port Group Configuration Registers This section starts with an overview of all configuration registers and then presents all registers in detail. The configuration registers are classified in the following groups: • “Pin function configuration“ on page 41 •...
Page 41: Pin Function Configuration
Pin Functions Chapter 2 2.2.2 Pin function configuration The registers for pin function configuration define the general function of a pin: • input mode or output mode • port mode or alternative mode • selection of one of the alternative output functions ALT1-OUT/ALT2-OUT •...
Page 42 Chapter 2 Pin Functions PMn - Port mode register The PMn register specifies whether the individual pins of the port group n are in input mode or in output mode. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register.
Page 43 Pin Functions Chapter 2 PMCn - Port mode control register The PMCn register specifies whether the individual pins of port group n are in port mode or in alternative mode. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register.
Page 44 Chapter 2 Pin Functions PLCDCn - Port LCD control register Some port groups comprise pins for signal output of the LCD Controller Driver. For those port groups, the 8-bit PLCDCn register specifies whether an individual pin of port group n serves as an output pin of the LCD Controller/ Driver or not.
Page 45 Pin Functions Chapter 2 OCDM - On-chip debug mode register The 8-bit OCDM register specifies whether dedicated pins of the microcontroller operate in normal operation mode or can be used for on-chip debugging (N-Wire interface). The setting of this register concerns only those pins that can be used for the N-Wire interface: P05/DRST, P52/DDI, P53/DDO, P54/DCK, and P55/DMS.
Page 46: Pin Data Input/Output
Chapter 2 Pin Functions 2.2.3 Pin data input/output If a pin is in port mode, the registers for pin data input/output specify the input and output data. Pn - Port register In port mode (PMCn.PMCnm=0), data is input from or output to an external device by writing or reading the Pn register.
Page 47 Pin Functions Chapter 2 PPRn - Port pin read register The PPRn register reflects the actual pin value, independent of the control registers set-up. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register.
Page 48: Configuration Of Electrical Characteristics
Chapter 2 Pin Functions 2.2.4 Configuration of electrical characteristics The registers for the configuration of electrical characteristics are briefly described in the following. For details refer to the Electrical Target Specification. PDSCn - Port drive strength control register The 8-bit PDSCn register selects the output current limiting function for high- or low-drive strength.
Page 49 Pin Functions Chapter 2 PILCn - Port input level control register The 8-bit PILCn register selects between different input characteristics for Schmitt Trigger (PICCn.PICCnm = 1) and non-Schmitt Trigger (PICCn.PICCnm = 0). Access This register can be read/written in 8-bit and 1-bit units. Address see “Port Group Configuration“...
Page 50: Alternative Input Selection
Chapter 2 Pin Functions 2.2.5 Alternative input selection Alternative input functions of CSIB0, UART0, UART1, I C0 and I C1 are provided on two pins each. Thus you can select on which pin the alternative function should appear. For this purpose, four peripheral function select registers PFSRk (k = 0, 3) are provided.
Page 51 Pin Functions Chapter 2 PFSR3 - Peripheral function select register The 8-bit PFSR3 register selects the alternative input paths for the peripheral functions UARTA0 and UARTA1. Access This register can be read/written in 8-bit units. Address FFFF F726 Initial Value .
Page 52: Port Types Diagrams
Chapter 2 Pin Functions 2.3 Port Types Diagrams The control circuits that evaluate the settings of the configuration registers are of different types. This chapter presents the block diagrams of all port types. Port type M PDSCnm PICCnm Note 1 PILCnm PMCnm PMnm...
Page 53 Pin Functions Chapter 2 Note Bits PILCn.PILCnm are available only for port group 8. The PFCn register is only available for port groups P0, P3, P5, P6 and P13. Note that PFC0 does not select between ALT1-OUT and ALT2-OUT but has a different function, refer to “Port type R“...
Page 54 Chapter 2 Pin Functions Port type Q PDSCnm PICCnm PMCn m PMnm PODCn m PFCn m ENABLE A L T1-OU T Pn m A L T2-OU T Pn m ENABLE internal RESET LCD Bus LCD Bus I/F read I/F write Figure 2-3 Block diagram: port type Q Preliminary User’s Manual U17566EE1V2UM00...
Page 55 Pin Functions Chapter 2 Port type R This port type holds for pins that can be used for on-chip debugging with the N-Wire interface. PDSCnm PICCnm OCDM PMn m PODCn m PFCnm Pn m Pn m ENABLE internal RESET PFC0.PDC05 DDI, DMS, DCK, DRST Figure 2-4 Block diagram: port type R...
Page 56: Port Group Configuration
Chapter 2 Pin Functions Port type B This port type holds for pins that only work in input mode. Pins of port type B are used for the corresponding alternative input function. At the same time, the pin status can also be read via the port register Pn, so that the pin also works in port function.
Page 57 Pin Functions Chapter 2 Table 2-18 Port group list for µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 (1/4) Alternative outputs Port group Alternative Port Port name ALT1_OUT/ALT2_OUT/ name inputs type LCD_OUT – INTP0/NMI – INTP1 – INTP2 – INTP3 – INTP4 – DRST –...
Page 58 Chapter 2 Pin Functions Table 2-18 Port group list for µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 (2/4) Alternative outputs Port group Alternative Port Port name ALT1_OUT/ALT2_OUT/ name inputs type LCD_OUT FOUT/SGOA – – – – – – – RXDA1/CRXD1 TXDA1/CTXD1 – SEG12 TIG20 SEG13 TIP01/TIG21...
Page 59 Pin Functions Chapter 2 Table 2-18 Port group list for µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 (3/4) Alternative outputs Port group Alternative Port Port name ALT1_OUT/ALT2_OUT/ name inputs type LCD_OUT SEG26 – SEG25 – SEG24 – SEG23 – – – FOUT/SEG27 – TXDA0/SEG30 –...
Page 60 Chapter 2 Pin Functions Table 2-18 Port group list for µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 (4/4) Alternative outputs Port group Alternative Port Port name ALT1_OUT/ALT2_OUT/ name inputs type LCD_OUT P120 SM51 – P121 SM52 – P122 SM53 – P123 SM54 – P124 SM61 –...
Page 61 Pin Functions Chapter 2 Table 2-19 Port group list for µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427 (2/5) Alternative outputs Port group Alternative Port Port name ALT1_OUT/ALT2_OUT/ name inputs type LCD_OUT SDA1 SDA1 SCL1 TIG02/SCL1 – TIG03 – TIG04 – TIG11 – TIG12 –...
Page 62 Chapter 2 Pin Functions Table 2-19 Port group list for µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427 (3/5) Alternative outputs Port group Alternative Port Port name ALT1_OUT/ALT2_OUT/ name inputs type LCD_OUT – TIG20 – TIP01/TIG21 TOP10 TIP10TIG25 TOP11 TIP11 SCL0 TIP20/SCL0 SDA0/TOP30 TIP30/SDA0 –...
Page 63 Pin Functions Chapter 2 Table 2-19 Port group list for µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427 (4/5) Alternative outputs Port group Alternative Port Port name ALT1_OUT/ALT2_OUT/ name inputs type LCD_OUT DBD0 – DBD1 – DBD2 – DBD3 – DBD4 – DBD5 – DBD6 –...
Page 64 Chapter 2 Pin Functions Table 2-19 Port group list for µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427 (5/5) Alternative outputs Port group Alternative Port Port name ALT1_OUT/ALT2_OUT/ name inputs type LCD_OUT P130 SM31/TOG01 TIG01 P131 SM32/TOG02 – P132 SM33/TOG03 – P133 SM34/TOG04 – P134 SM41/TOG11 –...
Page 65: Alphabetic Pin Function List
Pin Functions Chapter 2 2.4.2 Alphabetic pin function list Table 2-20 provides a list of all pin function names in alphabetic order. The right columns show also the port, the concerned signal is shared with: • “Pnm”: signal is shared with port Pnm •...
Page 66 Chapter 2 Pin Functions Table 2-20 Alphabetic pin functions list (2/5) Port Pin name Pin function ‘3420, ‘3421 ‘3424, ‘3425 ‘3427 ‘3422, ‘3423 ‘3426 External memory interface data – lines 16 to 31 P104 P105 P106 P107 DBD0 to DBD7 LCD Bus I/F data lines 0 to 7 P90 to P97 DBRD...
Page 67 Pin Functions Chapter 2 Table 2-20 Alphabetic pin functions list (3/5) Port Pin name Pin function ‘3420, ‘3421 ‘3424, ‘3425 ‘3427 ‘3422, ‘3423 ‘3426 MVSS50 to – External memory interface supply – no ports MVSS54 ground Non-maskable interrupt External memory interface read –...
Page 68 Chapter 2 Pin Functions Table 2-20 Alphabetic pin functions list (4/5) Port Pin name Pin function ‘3420, ‘3421 ‘3424, ‘3425 ‘3427 ‘3422, ‘3423 ‘3426 SM14 Stepper motor 1 output cos – P113 SM21 Stepper motor 2 output sin + P114 SM22 Stepper motor 2 output sin –...
Page 69 Pin Functions Chapter 2 Table 2-20 Alphabetic pin functions list (5/5) Port Pin name Pin function ‘3420, ‘3421 ‘3424, ‘3425 ‘3427 ‘3422, ‘3423 ‘3426 TIP10 Timer TMP1 channel 0 capture input TIP11 Timer TMP1 channel 1 capture input TIP20 Timer TMP2 channel 0 capture input TIP21 Timer TMP2 channel 1 capture...
Page 70 Chapter 2 Pin Functions Note Alternative input functions of CSIB0, UART0 and UART1 are provided on two pins each. Thus you can select on which pin the alternative function should appear. Refer to “Alternative input selection“ on page 50. Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 71: External Memory Interface Of Μpd70F3427
Pin Functions Chapter 2 2.4.3 External memory interface of µPD70F3427 The µPD70F3427 is equipped with an external memory interface. The data bus width can be chosen between 16-bit D[15:0] and 32-bit D[31:0]. The signals of the external memory interface are partly shared with ports respectively alternative functions and are controlled by different means, as listed in Table 2-21.
Page 72: Port Group 0
Chapter 2 Pin Functions 2.4.4 Port group 0 • Port group 0 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP0 to INTP6) • Non-maskable interrupt (NMI) • N-Wire debug interface reset (DRST) •...
Page 73 Pin Functions Chapter 2 Table 2-23 Port group 0: configuration registers Initial Register Address Used bits value FFFF F420 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PMC0 FFFF F440 PMC07 PMC06 PMC04 PMC03 PMC02 PMC01 PMC00 PFC0 FFFF F460 PDC05 OCDM FFFF F9FC...
Page 74: Port Group 1
Chapter 2 Pin Functions 2.4.5 Port group 1 Port group 1 is a 2-bit port group. In alternative mode, it comprises pins for the following functions: • I C0 data/clock line (SDA0/SCL0) Port group 1 includes the following pins: Table 2-24 Port group 1: pin functions and port types Pin functions in different modes Port mode...
Page 75: Port Group 2
Pin Functions Chapter 2 2.4.6 Port group 2 Port group 2 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Timer TMG0 to TMG1 channels (TIG02 to TIG04, TIG11 to TIG14) • I C1 data/clock line (SDA1, SCL1) •...
Page 76: Port Group 3
Chapter 2 Pin Functions 2.4.7 Port group 3 Port group 3 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • UARTA0 transmit/receive data (TXDA0, RXDA0) • UARTA1 transmit/receive data (TXDA1, RXDA1) • I C1 data/clock line (SDA1, SCL1) •...
Page 77 Pin Functions Chapter 2 Table 2-29 Port group 3: configuration registers Initial Register Address Used bits value FFFF F426 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PMC3 FFFF F446 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PFC3 FFFF F466 PFC37 PFC36 PFC35...
Page 78: Port Group 4
Chapter 2 Pin Functions 2.4.8 Port group 4 Port group 4 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Clocked Serial Interface CSIB0 data/clock line (SIB0, SOB0, SCKB0) • Clocked Serial Interface CSIB1 data/clock line (SIB1, SOB1, SCKB1) •...
Page 79: Port Group 5
Pin Functions Chapter 2 2.4.9 Port group 5 Port group 5 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP7) (µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427 only) • Sound Generator outputs (SGO, SGOA) •...
Page 80 Chapter 2 Pin Functions Table 2-33 Port group 5: configuration registers Initial Register Address Used bits value FFFF F42A PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PMC5 FFFF F44A PMC57 PMC56 PMC51 PMC50 PFC5 FFFF F46A PFC57 PFC50 OCDM FFFF F9FC OCDM0 FFFF F40A...
Page 81: Port Group 6
Pin Functions Chapter 2 2.4.10 Port group 6 Port group 6 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Timer TMP0 to TMP3 channels (TIP00 to TIP31, TOP00 to TOP31) • Timer TMG2 channels (TIG20 to TIG25, TOG21 to TOG24) •...
Page 82 Chapter 2 Pin Functions Table 2-35 Port group 6: configuration registers Initial Register Address Used bits value FFFF F42C PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 PMC6 FFFF F44C PMC67 PMC66 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 PFC6 FFFF F46C PFC65 PLCDC6 FFFF F34C...
Page 83: Port Group 7
Pin Functions Chapter 2 2.4.11 Port group 7 Port group 7 is a 16-bit port group. It includes pins for the A/D Converter input. The pins of this port group only work in input mode (port type B). They are used for their alternative input function.
Page 84 Chapter 2 Pin Functions Table 2-37 Port group 7: configuration registers Initial Register Address Used bits value PMC7L FFFF F44E PMC77 PMC76 PMC75 PMC74 PMC73 PMC72 PMC71 PMC70 PMC7H FFFF F44F PMC715 PMC714 PMC713 PMC712 PMC711 PMC710 PMC79 PMC78 PMC7 FFFF F44E 0000 PMC715 to PMC78 (PMC7H)
Page 85: Port Group 8
Pin Functions Chapter 2 2.4.12 Port group 8 Port group 8 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Clocked Serial Interface CSIB2 data/clock line (SIB2, SOB2, SCKB2) (µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427 only) •...
Page 86 Chapter 2 Pin Functions Table 2-39 Port group 8: configuration registers Initial Register Address Used bits value FFFF F430 PM87 PM87 PM86 PM85 PM84 PM83 PM82 PM81 PMC8 FFFF F450 PMC87 PMC86 PMC85 PMC84 PMC83 PMC82 PMC81 PMC80 PLCDC8 FFFF F350 PLCDC87 PLCDC86 PLCDC85...
Page 87: Port Group 9
Pin Functions Chapter 2 2.4.13 Port group 9 Port group 9 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • LCD Bus Interface data lines (DBD0 to DBD7) • LCD controller segment signal output (SEG36 to SEG39) (µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 only) •...
Page 88: Port Group 10
Chapter 2 Pin Functions 2.4.14 Port group 10 Port group 10 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Timer TMP0 and TMP2 (TOP00/01, TOP20/21, TIP00) • LCD Bus Interface read/write strobe (DBRD, DBWR) •...
Page 89: Port Group 11
Pin Functions Chapter 2 2.4.15 Port group 11 Port group 11 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Stepper Motor Controller/Driver outputs (SM11 to SM14, SM21 to SM24) Port group 11 includes the following pins: Table 2-44 Port group 11: pin functions and port types Pin functions in different modes...
Page 90: Port Group 12
Chapter 2 Pin Functions 2.4.16 Port group 12 Port group 12 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Stepper Motor Controller/Driver outputs (SM51 to SM54, SM61 to SM64) Port group 12 includes the following pins: Table 2-46 Port group 12: pin functions and port types Pin functions in different modes...
Page 91: Port Group 13
Pin Functions Chapter 2 2.4.17 Port group 13 Port group 13 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Stepper Motor Controller/Driver outputs (SM31 to SM34, SM41 to SM44) • Timer TMG0 to TMG1 channels (TIG01, TOG01 to TOG04, TOG11 to TOG14) Port group 13 includes the following pins: Table 2-48...
Page 92: Port Group 14 (Μpd70F3427 Only)
Chapter 2 Pin Functions 2.4.18 Port group 14 (µPD70F3427 only) Port group 14 is a 3-bit port group. In alternative mode, it comprises pins for the following functions: • External memory interface bus clock BCLK • External memory interface byte enable signals BE2, BE3 Port group 14 includes the following pins: Table 2-50 Port group 14: pin functions and port types...
Page 93: Noise Elimination
Pin Functions Chapter 2 2.5 Noise Elimination The input signals at some pins are passed through a filter to remove noise and glitches. The microcontroller supports both analog and digital filters. The analog filters are always applied to the input signals, whereas the digital filters can be enabled/disabled by control registers.
Page 94 Chapter 2 Pin Functions Filter operation The input terminal signal is sampled with the sampling frequency f . Spikes shorter than 2 sampling cycles are suppressed and no internal signal is generated. Pulses longer than 3 sampling cycles are recognized as valid pulses and an internal signal is generated.
Page 95 Pin Functions Chapter 2 Table 2-54 DFEN0 register contents Bit position Bit name Function Enables/disables the digital noise elimination filter for the corresponding input signal: 0: Digital filter is disabled. 15 to 0 DFENC[15:0] 1: Digital filter is enabled. For an assignment of bit positions to input signals see table Table 2-55.
Page 96 Chapter 2 Pin Functions DFEN1 - Digital filter enable register The 16-bit DFEN1 register enables/disables the digital filter for TMG0 to TMG2 and TMP0 to TMP1 input channels. Access This register can be read/written in 16-bit, 8-bit and 1-bit units. Address FFFF F712 Initial Value...
Page 97: Pin Functions In Reset And Power Save Modes
Pin Functions Chapter 2 2.6 Pin Functions in Reset and Power Save Modes The following table summarizes the status of the pins during reset and power save modes and after release of these operating states in normal operation mode, i.e. FLMD0 = 0. The reset source makes a difference concerning the N-Wire debugger interface pins DRST, DDI, DDO, DCK and DMS after reset release.
Page 98: Recommended Connection Of Unused Pins
Chapter 2 Pin Functions 2.7 Recommended connection of unused pins If a pin is not used, it is recommended to connect it as follows: • output pins: leave open • input pins: connect to V or V Sub oscillator If no sub oscillator crystal is connected, connect XT1 to V and leave XT2 connection open.
Page 99: Package Pins Assignment
Pin Functions Chapter 2 2.8 Package Pins Assignment The following sections show the location of pins in top view. Every pin is labelled with its pin number and all possible pin names. Additionally, a recommendation for the connection of unused pins is given at the end of the chapter.
Page 100: Μpd70F3424, Μpd70F3425, Μpd70F3426 - 144 Pin Package
Chapter 2 Pin Functions 2.8.2 µPD70F3424, µPD70F3425, µPD70F3426 — 144 pin package P92/DBD2 P23/TIG04 P93/DBD3 P22/TIG03 P21/TIG02/SCL1 P94/DBD4 P95/DBD5 P20/SDA1 P96/DBD6 P17/SCL0 P97/DBD7 P16/SDA0 DVDD50 VSS51 DVSS50 REGC1 VDD52 VDD51 REGC2 P30/TXDA0/SDA1 VSS52 P31/RXDA0/SCL1 FLMD0 P47/CTXD0 P46/CRXD0 V850E / DJ3 V850E / DJ3 P57/TXDA1/CTXD1 RESET...
Page 101: Μpd70F3427 - 208 Pin Package
Pin Functions Chapter 2 2.8.3 µPD70F3427 — 208 pin package P26/TIG13 P27/TIG14 P34/TOG21/TOP01 MVSS53 P35/TIG22/TOG22/TOP21 MVDD53 P36/TIG23/TOG23/TOP31 VSS51 P37/TIG24/TOG24/TOP11 REGC1 P60/TIG20 VDD51 P61/TIP01/TIG21 BVDD51 BVSS51 P62/TIP10/TIG25/TOP10 P63/TIP11/TOP11 P64/TIP20/SCL0 P65/TIP30/TOP30/SDA0 P66/TIP21 P67/TIP31/TOP31 P45/SCKB1 P44/SOB1 MVSS52 P43/SIB1 MVDD52 P82/SCKB2 P81/SOB2 P80/SIB2 V850E / DL3 P85/FOUT VDD52 REGC2...
Page 102 Chapter 2 Pin Functions Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 103: Chapter 3 Cpu System Functions
Chapter 3 CPU System Functions This chapter describes the registers of the CPU, the operation modes, the address space and the memory areas. 3.1 Overview The CPU is founded on Harvard architecture and it supports a RISC instruction set. Basic instructions can be executed in one clock period. Optimized five- stage pipelining is supported.
Page 104: Description
Table 3-1 Bus types Bus type Function NPB – NEC Peripheral Bus Bus interface to the peripherals (internal bus). VSB – V850 System Bus Bus interface to the Memory Controller for access to external memory, additional internal memory and to the NPB bus bridge BBR.
Page 105: Cpu Register Set
CPU System Functions Chapter 3 3.2 CPU Register Set There are two categories of registers: • General purpose registers • System registers All registers are 32-bit registers. An overview is given in the figure below. For details, refer to V850E1 User’s Manual Architecture. (Zero Register) EIPC (Status Saving Register during interrupt)
Page 106: General Purpose Registers (R0 To R31)
Chapter 3 CPU System Functions 3.2.1 General purpose registers (r0 to r31) Each of the 32 general purpose registers can be used as a data variable or address variable. However, the registers r0, r1, r3 to r5, r30, and r31 may implicitly be used by the assembler/compiler (see table Table 3-2).
Page 107: System Register Set
CPU System Functions Chapter 3 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Additionally, the program counter holds the instruction address during program execution. To read/write the system registers, use instructions LDSR (load to system register) or STSR (store contents of system register), respectively, with a specific system register number (regID) indicated below.
Page 108 Chapter 3 CPU System Functions PC - Program counter The program counter holds the instruction address during program execution. The lower 26 bits are valid, and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to 26, it is ignored. Branching to an odd address cannot be performed.
Page 109 CPU System Functions Chapter 3 PSW - Program status word The 32-bit program status word is a collection of flags that indicates the status of the program (result of instruction execution) and the status of the CPU. If the bits in the register are modified by the LDSR instruction, the PSW will take on the new value immediately after the LDSR instruction has been executed.
Page 110 Chapter 3 CPU System Functions In the case of saturate instructions, the SAT, S, and OV flags will be set according to the result of the operation as shown in the table below. Note that the SAT flag is set only when the OV flag has been set during a satu- rated operation.
Page 111 CPU System Functions Chapter 3 EIPSW, FEPSW, DBPSW, CTPSWPSW saving registers The PSW saving registers save the contents of the program status word for different occasions, see Table 3-4. When one of the occasions listed in Table 3-4 occurs, the current value of the PSW is saved to the saving registers.
Page 112 Chapter 3 CPU System Functions ECR - Interrupt/exception source register The 32-bit ECR register displays the exception codes if an exception or an interrupt has occurred. With the exception code, the interrupt/exception source can be identified. For a list of interrupts/exceptions and corresponding exception codes, see Table 3-9 on page 112.
Page 113 CPU System Functions Chapter 3 • PREPARE, DISPOSE instruction (only if an interrupt is generated before the stack pointer is updated) In this case, the address of the interrupted instruction is restored to the EIPC or FEPC, respectively. Execution is stopped, and after the completion of interrupt servicing the execution is resumed.
Page 114: Operation Modes
Chapter 3 CPU System Functions 3.3 Operation Modes This section describes the operation modes of the CPU and how the modes are specified. Flash devices The following operation modes are available for the flash memory devices: • Normal operation mode •...
Page 115: Normal Operation Mode
CPU System Functions Chapter 3 3.3.1 Normal operation mode Flash memory In normal operation mode, the internal flash memory is not re-programmed. devices After reset release, the firmware acquires the user's reset vector from the flash memory. The reset vector contains the start address of the user’s program code.
Page 116 Chapter 3 CPU System Functions CPU address space FFFF FFFFH Image FC00 0000H FBFF FFFFH Image Physical address space x3FF FFFFH F800 0000H Peripheral I/O x3FF F000H F7FF FFFFH VDB RAM x3FF 0000H Image VSB area 0800 0000H (Flash, RAM 07FF FFFFH external memory) Image...
Page 117: Program And Data Space
CPU System Functions Chapter 3 3.4.2 Program and data space The CPU allows the following assignment of data and instructions to the CPU address space: • 4 GB as data space The entire CPU address space can be used for operand addresses. •...
Page 118 Chapter 3 CPU System Functions Wrap-around of data space If an operand address calculation exceeds 32 bits, only the lower 32 bits of the result are considered. Therefore, the addresses 0000 0000 and FFFF FFFF are contiguous addresses. This results in a wrap-around of the data space: Data space FFFF FFFEH FFFF FFFFH...
Page 119: Memory
CPU System Functions Chapter 3 3.5 Memory In the following sections, the memory of the CPU is introduced. Specific memory areas are described and a recommendation for the usage of the address space is given. 3.5.1 Memory areas The internal memory of the CPU provides several areas: •...
Page 120 Chapter 3 CPU System Functions Internal VDB RAM area After reset The internal VDB RAM consists of several separated RAM blocks. If a reset occurs while writing to one RAM block, only the contents of that RAM block may be corrupted. The contents of the other RAM blocks remain unaffected. Table 3-12 summarizes the VDB (V850 Data Bus) RAM blocks compilation and their address assignment.
Page 121 CPU System Functions Chapter 3 Internal VSB flash area (µPD70F3426 only) The µPD70F3426 provides additional flash memory, accessible via the VSB (V850 System Bus). Table 3-13 Internal VSB flash memory Device Flash size Address range µPD70F3426 1 MB 0010 0000 to 001F FFFF Internal VSB RAM area (µPD70F3426 only) The µPD70F3426 provides additional RAM, accessible via the VSB (V850...
Page 122 Chapter 3 CPU System Functions For registers in which byte access is possible, if half word access is executed: • During read operation: The higher 8 bits become undefined. • During write operation: The lower 8 bits of data are written to the register.
Page 123: Recommended Use Of Data Address Space
CPU System Functions Chapter 3 3.5.2 Recommended use of data address space When accessing operand data in the data space, one register has to be used for address generation. This register is called pointer register. With relative addressing, an instruction can access operand data at all addresses that lie in the range of ±32 KB relative to the address in the pointer register.
Page 124: Write Protected Registers
Chapter 3 CPU System Functions 3.6 Write Protected Registers Write protected registers are protected from inadvertent write access due to erroneous program execution, etc. Write access to a write protected register is only given immediately after writing to a corresponding write enable register. For a write access to the write protected registers you have to use the following instructions: 1.
Page 125 CPU System Functions Chapter 3 Example Start the Watchdog Timer The following example shows how to write to the write protected register WDTM. The example starts the Watchdog Timer. do { _WPRERR = 0; DI(); WCMD = 0x5A; WDTM = 0x80; EI();...
Page 126: Instructions And Data Access Times
Chapter 3 CPU System Functions 3.7 Instructions and Data Access Times The below Table 3-16 and Table 3-17 list the instruction execution and data access cycles, required when accessing instructions or data in VFB flash/ROM, and VDB RAM and VSB flash/RAM. The access time depends on the •...
Page 127 CPU System Functions Chapter 3 Table 3-16 Single-cycle instructions execution times in CPU clock cycles µPD70F3421 µPD703420 µPD70F3424 µPD70F3427 µPD70F3426 µPD70F3422 µPD703421 Memory Access type µPD70F3425 µPD70F3423 µPD703422 Consecutive – VFB flash Random – Consecutive – – – – VFB ROM Random –...
Page 128 Chapter 3 CPU System Functions Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 129: Chapter 4 Clock Generator
Clock Generator Chapter 4 Chapter 4 Clock Generator The clock generator provides the clock signals needed by the CPU and the on-chip peripherals. 4.1 Overview The clock generator can generate the required clock signals from the following sources: • Main oscillator - a built-in oscillator with external crystal and a nominal frequency of 4 MHz •...
Page 130: Description
Chapter 4 Clock Generator 4.1.1 Description The clock generator is built up as illustrated in the following figure. CKC.SCEN PCC.CKS[1:0] CKC.PLLEN PCC.CLS PLLCLK PCC.MFRC CPU System Standby VBCLK MOCLK MainOSC 4 MHz SSCCLK SSCG Standby Standby PCLK0 AFCAN PCLK1 RingOSC ROCLK n=1,2,3,4,6,8 UARTA...
Page 131 Clock Generator Chapter 4 CPU clocks The CPU can be clocked directly by any of the oscillators, or by the output of one of the PLLs. The following table gives an overview of the available CPU clocks. Table 4-1 Clock sources and frequencies for the CPU Clock source Frequency Description Ring osc...
Page 132: Clock Monitors
Chapter 4 Clock Generator Calibration Timer. These clocks are directly derived from the oscillators and bypass the PLLs. LCDCLK The LCD Controller/Driver can be clocked by SPCLK7, SPCLK9, or LCDCLK. WTCLK This is the clock for the Watch Timer. It forms the time base for updating the internal bookkeeping of daytime and calendar.
Page 133: Power Save Modes Overview
Clock Generator Chapter 4 4.1.3 Power save modes overview The microcontroller provides the following stand-by modes: HALT, IDLE, WATCH, Sub-WATCH, and STOP. Application systems which are designed in a way that they switch between these modes according to operation purposes, reduce power consumption efficiently.
Page 134: Start Conditions
Chapter 4 Clock Generator 4.1.4 Start conditions After any reset release, the ring oscillator is always selected as the clock source. The oscillation stabilization time for the ring oscillator is ensured by hardware. The CPU clock VBCLK is derived from the ring oscillator. Several clocks are operating based on the ring oscillator clock after reset.
Page 135: Start-Up Guideline
Clock Generator Chapter 4 4.1.5 Start-up guideline After reset release, the internal firmware starts the main oscillator, but hands over control to the user’s software without ensuring that the main oscillator has stabilized. After that, the user’s software will typically: 1.
Page 136: Clock Generator Registers
Chapter 4 Clock Generator 4.2 Clock Generator Registers The Clock Generator is controlled and operated by means of the following registers (the list is sorted according to memory allocation): Table 4-3 Clock Generator register overview Write- protected Register name Shortcut Address by register PSC write protection register...
Page 137 Clock Generator Chapter 4 The subsequent register descriptions are grouped as follows: • General Clock Generator Registers: – “CKC - Clock Generator control register” on page 138 – “CGSTAT - Clock Generator status register” on page 139 – “PHCMD - Command protection register” on page 140 –...
Page 138: General Clock Generator Registers
Chapter 4 Clock Generator 4.2.1 General clock generator registers The general Clock Generator registers control and reflect the operation of the Clock Generator. CKC - Clock Generator control register The 8-bit CKC register controls the clock management. Access This register can be read/written in 8-bit units. Writing to this register is protected by a special sequence of instructions.
Page 139 Clock Generator Chapter 4 CGSTAT - Clock Generator status register The 8-bit CGSTAT register is read-only. It indicates the status of the main oscillator and the status of the clock generator after wake-up from power save mode. Access This register can be read in 8-bit units. Address FFFF F824 Initial Value...
Page 140 Chapter 4 Clock Generator PHCMD - Command protection register The 8-bit PHCMD register is write-only. It is used to protect other registers from unintended writing. Access This register must be written in 8-bit units. Address FFFF F800 Initial Value The contents of this register is undefined. PHCMD protects the registers that may have a significant influence on the application system from inadvertent write access, so that the system does not stop in case of a program hang-up.
Page 141 Clock Generator Chapter 4 PHS - Peripheral status register The 8-bit PHS register indicates the status of a write attempt to a register protected by PHCMD (see also “PHCMD - Command protection register” on page 140). Access This register can be read/written in 8-bit units. Address FFFF F802 Initial Value...
Page 142 Chapter 4 Clock Generator PCC - Processor clock control register The 8-bit PCC register controls the CPU clock. This register can be changed only once after reset or power save mode release. Access This register can be read/written in 8-bit units. Writing to this register is protected by a special sequence of instructions.
Page 143 Clock Generator Chapter 4 Table 4-7 PCC register contents (2/2) Bit position Bit name Function 1 to 0 CKS[1:0] Processor clock connection: CKS1 CKS0 Selected clock connection Main oscillator SSCG PLL (main oscillator frequency x4) PLL (main oscillator frequency x8) As long as PCC.CLS = 1 these bits are ignored.
Page 144: Sscg Control Registers
Chapter 4 Clock Generator 4.2.2 SSCG control registers This section describes the registers used for controlling the spread spectrum Clock Generator SSCG. For modulating the SSCG output clock it’s dithering mode must be enabled by CKC.DEN = 1. Reconfiguration of The SSCG control registers SCFC0, SCFC1 and SCFMC can only be rewritten SSCG registers with new settings if the SSCG is switched off, i.e.
Page 145 Clock Generator Chapter 4 SCFC0 - SSCG frequency control register 0 The 8-bit SCFC0 register controls the frequency modulation of the SSCG. It determines the SSCG output frequency and is used in conjunction with register SCFC1. = (4 MHz × N/M) / 2. This The center SSCG output frequency is f SSCGc register defines the divisor “m”...
Page 146 Chapter 4 Clock Generator SCFC1 - SSCG frequency control register 1 The 8-bit SCFC1 register controls the frequency multiplication of the SSCG. It determines the SSCG output frequency and is used in conjunction with register SCFC0. = (4 MHz × N/M) / 2. This The center SSCG output frequency is f SSCGc register defines the factor “n”...
Page 147 Clock Generator Chapter 4 SCFMC - SSCG frequency modulation control register The 8-bit SCFMC register controls the frequency modulation of the SSCG in dithering mode (when CKC.DEN = 1). Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F82A Initial Value...
Page 148 Chapter 4 Clock Generator Example • SCFC0 = 2B , SCFC1 = DF : center frequency f = 48 MHz SSCGc • [SCFMC[4:2]] = 101 : FM range = 5 % • [SCFMC[1:0]] = 01 : modulation frequency = 50 kHz Then: •...
Page 149 Clock Generator Chapter 4 SCPS - SSCG post scaler control register The 8-bit SCPS register controls the two independent SSCG post scalers (frequency dividers) for the CPU system clock VBCLK. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F830 Initial Value...
Page 150: Control Registers For Peripheral Clocks
Chapter 4 Clock Generator 4.2.3 Control registers for peripheral clocks This section describes the registers used for specifying the sources and operation modes for the clocks provided for the on-chip peripherals. These clocks are the clocks for the Watchdog and Watch Timers, the SPCLKn clocks, FOUTCLK, and IICLK.
Page 151 Clock Generator Chapter 4 Table 4-13 WCC register contents Bit position Bit name Function SOSTP Sub oscillator STOP mode control 1: Sub oscillator will stop when STOP mode is entered. 0: Sub oscillator will not stop when STOP mode is entered. 6 to 4 WPS[2:0] WDT clock divider selection:...
Page 152 Chapter 4 Clock Generator TCC - Watch Timer clock control register The 8-bit TCC register determines the Watch Timer and LCD controller clock source and the setting of the associated clock dividers. This register can be changed only once after Power-On-Clear reset or external RESET. Access This register can be read/written in 8-bit units.
Page 153 Clock Generator Chapter 4 Table 4-14 TCC register contents (2/2) Bit position Bit name Function 2, 0 WTSOS, Clock source for Watch Timer and LCD controller: WTSEL0 WTSOS WTSEL0 Clock source Ring oscillator Sub oscillator Main oscillator Setting prohibited By default, the sub oscillator is disabled in STOP mode (see bit WCC.SOSTP). If WCC.SOSTP is 1, choose main or ring oscillator before entering STOP mode.
Page 154 Chapter 4 Clock Generator SCC - SPCLK control register The 8-bit SCC register selects the SPCLK sources. Access This register can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “PHCMD - Command protection register”...
Page 155 Clock Generator Chapter 4 FCC - FOUTCLK control register The 8-bit FCC register configures the output clock FOUTCLK that can be used for external devices. Access This register can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “PHCMD - Command protection register”...
Page 156 Chapter 4 Clock Generator ICC - IIC clock control register The 8-bit ICC register determines the I C clock source for IICLK. Access This register can be read/written in 8-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “PHCMD - Command protection register”...
Page 157: Control Registers For Power Save Modes
Clock Generator Chapter 4 4.2.4 Control registers for power save modes The registers described in this section control the begin and end of the power save modes IDLE, WATCH, Sub-WATCH, and STOP. Please refer to “Power save mode activation” on page 179 for instructions and an example on how to enter a power save mode.
Page 158 Chapter 4 Clock Generator Table 4-18 PSM register contents Bit position Bit name Function CMODE Watch Calibration Timer clock selection: 0: PCLK1. 1: Main oscillator. OSCDIS Main oscillator disable/enable control during and after power save mode: 0: Main oscillator enabled. 1: Main oscillator disabled.
Page 159 Clock Generator Chapter 4 PSC - Power save control register The 8-bit PSC register is used to enter or leave the power save mode specified in register PSM. Access This register can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “PRCMD - PSC write protection register”...
Page 160 Chapter 4 Clock Generator PRCMD - PSC write protection register The 8-bit PRCMD register protects the register PSC from inadvertent write access, so that the system does not stop in case of a program hang-up. After data has been written to the PRCMD register, the first write access to register PSC is valid.
Page 161 Clock Generator Chapter 4 STBCTL- Stand-by control register The 8-bit STBCTL register is used to control the stand-by function of the voltage regulators. Access This register can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “STBCTLP - Stand-by control protection register”...
Page 162 Chapter 4 Clock Generator STBCTLP - Stand-by control protection register The 8-bit STBCTLP register protects the register STBCTL from inadvertent write access. After data has been written to the STBCTLP register, the first write access to register STBCTL is valid. All subsequent write accesses are ignored. Thus, the value of STBCTL can only be rewritten in a specified sequence, and illegal write access is inhibited.
Page 163: Clock Monitor Registers
Clock Generator Chapter 4 4.2.5 Clock monitor registers The following registers are used to control the monitor circuits of the main oscillator clock and the sub oscillator clock. Please refer to “Operation of the Clock Monitors” on page 185 for supplementary information.
Page 164 Chapter 4 Clock Generator PRCMDCMM - CLMM write protection register The 8-bit PRCMDCMM register protects the register CLMM from inadvertent write access, so that the system does not stop in case of a program hang-up. After data has been written to the PRCMDCMM register, the first write access to register CLMM is valid.
Page 165 Clock Generator Chapter 4 CLMS - Sub oscillator clock monitor register The 8-bit CLMS register is used to enable the monitor for the sub oscillator clock. Access This register can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “PRCMDCMS - CLMS write protection register”...
Page 166 Chapter 4 Clock Generator CLMCS - Sub oscillator clock monitor control register The 8-bit CLMCS register is used to start the monitor of the sub oscillator clock. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F71A Initial Value .
Page 167: Power Save Modes
Clock Generator Chapter 4 4.3 Power Save Modes This chapter describes the various power save modes and how they are operated. For details see: • “Power save modes description” on page 167 • “Power save mode activation” on page 179 •...
Page 168 Chapter 4 Clock Generator – Watch Timer interrupts INTWTnUV The Watch Timer clock WTCLK must be active and the Watch Timer must be enabled. – Watch Calibration Timer interrupt INTTM01 The Watch Calibration Timer clock WCTCLK must be active and the Watch Calibration Timer must be enabled.
Page 169 Clock Generator Chapter 4 HALT mode The HALT mode can be entered from normal run mode. In HALT mode, all clock settings remain unchanged. Only the CPU clock is suspended and hence program execution. Table 4-24 Clock Generator status in HALT mode Item Status Remarks...
Page 170 Chapter 4 Clock Generator IDLE mode The IDLE mode can be entered from any run mode. The main oscillator must be operating. IDLE mode can not be entered if the CPU is clocked by the sub or ring oscillator. In IDLE mode, the clock distribution is stopped (refer to the “Standby” switches in Figure 4-1, “Block diagram of the Clock Generator,”...
Page 171 Clock Generator Chapter 4 WATCH mode In WATCH mode, the clock supply for the CPU system and the majority of peripherals is stopped. The main oscillator continues operation. PLL and SSCG are stopped. By default, ring oscillator and sub oscillator operation is not affected. For exceptions see “Ring and sub oscillator operation”...
Page 172 Chapter 4 Clock Generator Sub-WATCH mode In Sub-WATCH mode, the clock supply for the CPU and the majority of peripherals is stopped. Main oscillator, PLL, and SSCG are stopped. By default, ring oscillator and sub oscillator operation is not influenced. For exceptions see “Ring and sub oscillator operation”...
Page 173 Clock Generator Chapter 4 STOP mode In STOP mode, all clock sources are stopped, except sub and ring oscillator. These can be configured in register WCC to stop as well. No clock is available, and no internal self-timed processes operates. Table 4-28 Clock Generator status in STOP mode Item...
Page 174 Chapter 4 Clock Generator Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 175 Clock Generator Chapter 4 Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 176 Chapter 4 Clock Generator Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 177: Clock Generator State Transistions
Clock Generator Chapter 4 4.3.2 Clock Generator state transistions VBCLK state transitions Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 178 Chapter 4 Clock Generator Main oscillator state transitions Reset MainOSC started by F/W MainOSC PSM release from - STOP (PSM[1:0] = 01 stabilization Stabilization counter expired PSM entry with MainOSC MainOSC PSM release from - PSM[1:0] = 01 (STOP) - PSM[1:0] = 11 (Sub-WATCH) - Sub-WATCH (PSM[1:0] = 11 ) and OSCDIS = 1...
Page 179: Power Save Mode Activation
Clock Generator Chapter 4 4.3.3 Power save mode activation In the following procedures for securely entering a power save mode are described. Stepper-C/D shut In order to minimize power consumption during power save modes the Stepper down Motor Controller/Driver needs to be shut down in a special sequence. Refer to “MCNTCn0, MCNTCn1 - Timer mode control registers”...
Page 180 Chapter 4 Clock Generator In this example, maskable interrupts are permitted to leave the power save mode. // xxIC.xxMK = 0 // mask all none wake-up interrupts // xxIC.xxMK = 1 // unmask all wake-up interrupts 0x02,r10 st.b 10,PSM[r0] // PSM.PSM[1:0] = 10B: WATCH mode 0x62,r10 st.b r10,PRCMD[r0]...
Page 181: Cpu Operation After Power Save Mode Release
Clock Generator Chapter 4 Make sure that all DMA channels are disabled. Otherwise a DMA could happen between steps 7 and 8, and the power down mode may not be entered at all. Further on do not perform write operations to PRCMD and write-protected registers by DMA transfers.
Page 182 Chapter 4 Clock Generator SSCG operating (provided that CGSTAT.CMPLPSM 1 before power save mode request) – CGSTAT.CMPLPSM = 1 if a power save mode has been completely entered, wake-up configuration established, PLL/SSCG stopped (provided that a power save mode request has been accepted before, i.e. →...
Page 183 Clock Generator Chapter 4 oscillator is automatically started, the oscillator stabilization time is waited and the main oscillator is chosen as the CPU system clock. After Sub-WATCH In Sub-WATCH mode the main oscillator is stopped. On return from Sub- WATCH, PCC.CLS is set to the status of PSM.OSCDIS. •...
Page 184: Clock Generator Operation
Chapter 4 Clock Generator 4.4 Clock Generator Operation 4.4.1 Ring and sub oscillator operation By default, sub and ring oscillator operate during all power save modes. However, it can be specified in the WCC register that the sub oscillator stops in STOP mode (WCC.SOSTP).
Page 185: Operation Of The Clock Monitors
Clock Generator Chapter 4 4.4.4 Operation of the Clock Monitors The microcontroller provides two separate clock monitors to watch the activity of the main oscillator and the sub oscillator. Description The functional block diagram is shown below. CLKM_MAIN main osc start CGSTAT.OSCSTAT output...
Page 186 Chapter 4 Clock Generator Since CLMCS.CMRT = 1 is synchronized with the ring oscillator any change of this bit has to be maintained for at least 65 ring oscillator periods T = 1/ ROSC to become effective. Therefore a wait period has to be assured before ROSC this bit is changed again.
Page 187: Chapter 5 Interrupt Controller (Intc)
Chapter 5 Interrupt Controller (INTC) This controller is provided with a dedicated Interrupt Controller (INTC) for interrupt servicing and can process a large amount of maskable and two non- maskable interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 188 Chapter 5 Interrupt Controller (INTC) Table 5-1 µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 interrupt/ exception source list (1/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Reset Interrupt RESET RESET input – 0000H 00000000H undef.
Page 189 Interrupt Controller (INTC) Chapter 5 Table 5-1 µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 interrupt/ exception source list (2/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Maskable Interrupt INTTP2CC0 TMP2 capture compare TMP2 0220H 00000220H next PC...
Page 190 Chapter 5 Interrupt Controller (INTC) Table 5-1 µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 interrupt/ exception source list (3/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Maskable Interrupt INTCB0RE CSIB0 receive error CSIB0 03E0H 000003E0H next PC...
Page 191 Interrupt Controller (INTC) Chapter 5 Table 5-1 µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 interrupt/ exception source list (4/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Maskable Interrupt INTTG2OV0 TMG2 overflow interrupt 0 TMG2 0590H 00000590H...
Page 192 Chapter 5 Interrupt Controller (INTC) Table 5-2 µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427 interrupt/ exception source list (1/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Reset Interrupt RESET RESET input – 0000H 00000000H undef.
Page 193 Interrupt Controller (INTC) Chapter 5 Table 5-2 µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427 interrupt/ exception source list (2/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Maskable Interrupt INTTP2CC0 TMP2 capture compare TMP2 0220H 00000220H next PC...
Page 194 Chapter 5 Interrupt Controller (INTC) Table 5-2 µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427 interrupt/ exception source list (3/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Maskable Interrupt INTCB0RE CSIB0 receive error CSIB0 03E0H 000003E0H next PC...
Page 195 Interrupt Controller (INTC) Chapter 5 Table 5-2 µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427 interrupt/ exception source list (4/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Maskable Interrupt INTTG2OV0 TMG2 overflow interrupt 0 TMG2 0590H 00000590H...
Page 196 Chapter 5 Interrupt Controller (INTC) Note Default priority: The priority order when two or more maskable interrupt requests are generated at the same time. The highest priority is 0. Restored PC: The value of the PC saved to EIPC or FEPC when interrupt/exception processing is started.
Page 197: Non-Maskable Interrupts
Interrupt Controller (INTC) Chapter 5 5.2 Non-Maskable Interrupts A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. Non-maskable interrupts of this microcontroller are available for the following two requests: • NMI0: NMI pin input •...
Page 198 Chapter 5 Interrupt Controller (INTC) NMI0 and NMIWDT requests generated simultaneously Main routine NMIWDT servicing NMI0 and NMIWDT requests System reset (generated simultaneously) Figure 5-1 Example of non-maskable interrupt request acknowledgement operation: multiple NMI requests generated at the same time Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com...
Page 199 Interrupt Controller (INTC) Chapter 5 NMI being NMI request generated during NMI servicing serviced NMI0 NMIWDT NMI0 request generated during NMIWDT request generated NMI0 NMI0 servicing during NMI0 servicing (NP = 1 retained before NMI1 request) Main routine Main routine NMI0 servicing NMI0 servicing NMIWDT request...
Page 200: Operation
Chapter 5 Interrupt Controller (INTC) 5.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: Saves the restored PC to FEPC. Saves the current PSW to FEPSW. Writes exception code 0010H to the higher halfword (FECC) of ECR. Sets the NP and ID bits of the PSW and clears the EP bit.
Page 201: Restore
Interrupt Controller (INTC) Chapter 5 5.2.2 Restore NMI0 Execution is restored from the non-maskable interrupt (NMI0) processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>...
Page 202: Non-Maskable Interrupt Status Flag (Np)
Chapter 5 Interrupt Controller (INTC) 5.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execution. This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 203: Maskable Interrupts
Interrupt Controller (INTC) Chapter 5 5.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control).
Page 204 Chapter 5 Interrupt Controller (INTC) INT input INTC accepted xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with the same priority? Maskable interrupt request Interrupt request pending...
Page 205: Restore
Interrupt Controller (INTC) Chapter 5 5.3.2 Restore Recovery from maskable interrupt processing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0.
Page 206: Priorities Of Maskable Interrupts
Chapter 5 Interrupt Controller (INTC) 5.3.3 Priorities of maskable interrupts This microcontroller provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 207 Interrupt Controller (INTC) Chapter 5 Main routine Processing of a Processing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the (level 3) (level 2) priority of b is higher than that of a and interrupts are enabled.
Page 208 Chapter 5 Interrupt Controller (INTC) The default priority in the figure indicates the relative priority between two interrupt requests. Main routine Processing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k priority is lower than that of i.
Page 209 Interrupt Controller (INTC) Chapter 5 Caution The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Note Lower default priority Higher default priority Main routine...
Page 210: Xxic - Maskable Interrupts Control Register
Chapter 5 Interrupt Controller (INTC) 5.3.4 xxIC - Maskable interrupts control register An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read/written in 8-bit or 1-bit units. Initial Address value...
Page 211 Interrupt Controller (INTC) Chapter 5 Table 5-3 Addresses and bits of interrupt control registers (1/3) Address Register FFFFF110H VC0IC VC0IF VC0MK VC0PR2 VC0PR1 VC0PR0 FFFFF112H VC1IC VC1IF VC1MK VC1PR2 VC1PR1 VC1PR0 FFFFF114H WT0UVIC WT0UVIF WT0UVMK WT0UVPR2 WT0UVPR1 WT0UVPR0 FFFFF116H WT1UVIC WT1UVIF WT1UVMK WT1UVPR2...
Page 212 Chapter 5 Interrupt Controller (INTC) Table 5-3 Addresses and bits of interrupt control registers (2/3) Address Register FFFFF162H TG1CC0C TG1CC0IF TG1CC0MK TG1CC0PR2 TG1CC0PR1 TG1CC0PR0 FFFFF164H TG1CC1IC TG1CC1IF TG1CC1MK TG1CC1PR2 TG1CC1PR1 TG1CC1PR0 FFFFF166H TG1CC2IC TG1CC2IF TG1CC2MK TG1CC2PR2 TG1CC2PR1 TG1CC2PR0 FFFFF168H TG1CC3IC TG1CC3IF TG1CC3MK TG1CC3PR2...
Page 213 Interrupt Controller (INTC) Chapter 5 Table 5-3 Addresses and bits of interrupt control registers (3/3) Address Register FFFFF1B8H TG2CC1IC TG2CC1IF TG2CC1MK TG2CC1PR2 TG2CC1PR1 TG2CC1PR0 FFFFF1BAH TG2CC2IC TG2CC2IF TG2CC2MK TG2CC2PR2 TG2CC2PR1 TG2CC2PR0 FFFFF1BCH TG2CC3IC TG2CC3IF TG2CC3MK TG2CC3PR2 TG2CC3PR1 TG2CC3PR0 FFFFF1BEH TG2CC4IC TG2CC4IF TG2CC4MK TG2CC4PR2...
Page 214: Imr0 To Imr5 - Interrupt Mask Registers
Chapter 5 Interrupt Controller (INTC) 5.3.5 IMR0 to IMR5 - Interrupt mask registers These registers set the interrupt mask state for the maskable interrupts. The xxMK bit of the IMRm (m = 0 to 5) registers is equivalent to the xxMK bit of the xxIC register.
Page 215 Interrupt Controller (INTC) Chapter 5 For µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 only: Address Initial value IMR4 C1TRXMK C1RECMK C1WUPMK C1ERRMK FFFFF108H FFFFH INT71MK INT70MK DMA3MK DMA2MK DMA1MK DMA0MK SG0MK IIC1MK Address Initial value IMR5 LCDMK CB1TMK CB1RMK CB1REMK TG2CC5MK FFFFF10AH FFFFH TG2CC4MK TG2CC3MK TG2CC2MK TG2CC1MK TG2CC0MK TG2OV1MK TG2OV0MK For µPD70F3424, µPD70F3425, µPD70F3426, µPD70F3427 only: Address...
Page 216: Ispr - In-Service Priority Register
Chapter 5 Interrupt Controller (INTC) 5.3.6 ISPR - In-service priority register This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 217: External Maskable Interrupts
Interrupt Controller (INTC) Chapter 5 5.3.8 External maskable interrupts This microcontroller provides maskable external interrupts INTPn with the following features: • Analog input filter (refer to “Analog filtered inputs“ on page 102) • Interrupt detection selectable for each interrupt input: –...
Page 218: Edge And Level Detection Configuration
Chapter 5 Interrupt Controller (INTC) 5.4 Edge and Level Detection Configuration The microcontroller provides the maskable external interrupts INTPn and one non-maskable interrupt (NMI). INTPn can be configured to generate interrupts upon edges or levels, the NMI can be set up to react on edges. INTM0 to INTM3 - External interrupt configuration register External interrupt function is configured by the registers INTM0…INTM3.
Page 219 Interrupt Controller (INTC) Chapter 5 The NMI and INTP0 share the same pin. The register bits NMIEN, ESEL0, ESEL01 and ESEL00 configure the NMI and INTP0 interrupt function: Function NMIEN ESEL0 ESEL01 ESEL00 INTP0 falling edge rising edge prohibited both edges masked low level high level...
Page 220: Software Exception
Chapter 5 Interrupt Controller (INTC) 5.5 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 5.5.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: Saves the restored PC to EIPC.
Page 221: Restore
Interrupt Controller (INTC) Chapter 5 5.5.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1.
Page 222: Exception Status Flag (Ep)
Chapter 5 Interrupt Controller (INTC) 5.5.3 Exception status flag (EP) The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP 00000020H Bit position...
Page 223 Interrupt Controller (INTC) Chapter 5 Exception trap (ILGOP) occurs DBPC restored PC DBPSW PSW.NP PSW.EP CPU processing PSW.ID 00000060H Exception processing Figure 5-12 Exception trap processing Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 224: Debug Trap
Chapter 5 Interrupt Controller (INTC) 5.6.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. Operation When the debug trap is generated, the CPU performs the following processing, transfers control to the debug monitor routine, and shifts to debug mode.
Page 225: Multiple Interrupt Processing Control
Interrupt Controller (INTC) Chapter 5 Restore Recovery from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW.
Page 226 Chapter 5 Interrupt Controller (INTC) Acknowledgment of maskable interrupts in service program Service program of maskable interrupt or exception • EIPC saved to memory or register • EIPSW saved to memory or register • EI instruction (interrupt acknowledgment enabled) Higher priority maskable interrupt acknowledgment •...
Page 227: Interrupt Response Time
Interrupt Controller (INTC) Chapter 5 The priority order for multiple interrupt processing control has 8 levels, from 0 to 7 for each maskable interrupt request (0 is the highest priority), but it can be set as desired via software. Setting of the priority order level is done using the PPRn0 to PPRn2 bits of the interrupt control request register (PlCn), which is provided for each maskable interrupt request.
Page 228: Periods In Which Interrupts Are Not Acknowledged
Chapter 5 Interrupt Controller (INTC) 5 system clocks VBCLK (Input) Interrupt request Instruction 1 EX MEM WB Instruction 2 IFX IDX Interrupt acknowledgement operation INT1 INT2 INT3 INT4 Instruction (first instruction of interrupt service routine) Figure 5-16 Pipeline operation at interrupt request acknowledgment (outline) Note INT1 to INT4: Interrupt acknowledgement processing IFx:...
Page 229: Chapter 6 Flash Memory
Chapter 6 Flash Memory The µPD70F3420, µPD70F3421, µPD70F3422, µPD70F3422, µPD70F3423, µPD70F3424, µPD70F3425, µPD70F3426 and µPD70F3427 microcontrollers are equipped with internal flash memory. The flash memory is attached to the V850 Fetch Bus VFB interface of the V850E CPU core. It is used for program code and storage of constant data.
Page 230: Flash Memory Address Assignment
Chapter 6 Flash Memory 6.1.1 Flash memory address assignment The µPD70F3427, µPD70F3426, µPD70F3425 1 MB flash memory is made up of 256 blocks. Figure 6-1 shows the address assignment of the flash memory blocks. 0010 0000 Block 255 (4 KB) 000F F000 Block 254 (4 KB) 000F E000...
Page 231 Flash Memory Chapter 6 The µPD70F3422 384 KB flash memory is made up of 96 blocks. Figure 6-3 shows the address assignment of the flash memory blocks. 0006 0000 Block 95 (4 KB) 0005 F000 Block 94 (4 KB) 0005 E000 0000 2000 Block 1 (4 KB) 0000 1000...
Page 232: Flash Memory Erasure And Rewrite
Chapter 6 Flash Memory The µPD70F3420 128 KB flash memory is made up of 32 blocks. Figure 6-3 shows the address assignment of the flash memory blocks. 0002 0000 Block 31 (4 KB) 0001 F000 Block 30 (4 KB) 0001 E000 0000 2000 Block 1 (4 KB) 0000 1000...
Page 233: Flash Memory Programming
For comprehensive information concerning secure boot block swapping refer to the application note “Self-Programming” (document nr. U16929EE), which explains also the functions of the self-programming library. The latest version of this document can be loaded via the URL http://www.ee.nec.de/updates Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com...
Page 234: Flash Self-Programming
The self-programming functions are part of the internal firmware, which resides in an extra internal ROM. The user’s application can call the self- programming functions via the self-programming library, provided by NEC. Caution During self-programming make sure to disable all ROM correction facilities, as enabled ROM corrections may conflict with the internal firmware.
Page 235 Flash Memory Chapter 6 SELFEN - Self-programming enable control register The 8-bit SELFEN register enables the self-programming functions by software. It is an internal substitute to enabling self-programming by rising the FLMD0 pin to high level. Access This registers can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions.
Page 236: Interrupt Handling During Flash Self-Programming
The latest version of this document can be loaded via the URL http://www.ee.nec.de/updates Since neither the interrupt vector table nor the interrupt handler routines, which are normally located in the flash memory, are accessible during self- programming, interrupt acknowledges have to be re-routed to non-flash memory, i.e.
Page 237: Flash Programming Via N-Wire
Flash Memory Chapter 6 6.3 Flash Programming via N-Wire The microcontroller’s flash memory is programmable via the N-Wire debug interface. Programming of the flash memory can be performed by the debug tool running on the host machine. Caution Programming the flash memory during debug sessions by the debug tool adds to the performed number of write/erase cycles of the flash memory.
Page 238: Flash Programming With Flash Programmer
Chapter 6 Flash Memory 6.4 Flash Programming with Flash Programmer A dedicated flash programmer can be used for on-board or off-board writing of the flash memory. On-board programming The contents of the flash memory can be rewritten with the microcontroller mounted on the target system.
Page 239: Communication Mode
Flash Memory Chapter 6 If the CSIB interface is used with handshake, the flash programmer’s HS signal is connected to a certain V850 port. The port used as the handshake port is given in Table 6-2. Flash memory programming off-board requires a dedicated program adapter. UARTA0, CSIB0 or N-Wire is used as the interface between the flash programmer and the microcontroller.
Page 240 Chapter 6 Flash Memory CSIB0 without handshake Serial clock: up to 2.5 MHz (MSB first) Note Note FLMD0 (FLMD1 FLMD0 (FLMD1 Axxxx Bxxxxx Cxxxxxx RESET RESET STATVE PG-FP4 SOB0 flash programmer SIB0 V850 microcontroller SCKB0 Note: FLMD1 connection may be replaced by a pull-down resistor on the board Figure 6-8 Communication with flash programmer via CSIB0 without handshake CSIB0 with handshake (CSIB0 + HS)
Page 241 Flash Memory Chapter 6 Table 6-2 Signals generated by flash programmer PG-FP4 PG-FP4 Controller Connection Signal Pin function Pin name UARTA0 CSIB0 CSIB0 + HS name FLMD0 Output Write enable/disable, FLMD0 mode setting × × × FLMD1 Output Mode setting FLMD1 voltage generation/voltage monitor...
Page 242: Pin Connection
Chapter 6 Flash Memory 6.4.3 Pin connection A connector must be mounted on the target system to connect the flash programmer for on-board writing. In addition, a function to switch between the normal operation mode and flash memory programming mode must be provided on the board.
Page 243 Flash Memory Chapter 6 Serial interface pins The pins used by each serial interface are shown in the table below. Table 6-4 Pins used by each serial interface Serial interface Pins UARTA0 TXDA0, RXDA0 at pins P30/P31 CSIB0 SOB0, SIB0, SCKB0 at pins P40 - P42 CSIB0 + HS SOB0, SIB0, SCKB0, P84 In flash programming mode the output drive strength control of the pins...
Page 244: Programming Method
Chapter 6 Flash Memory 6.4.4 Programming method Flash memory control The procedure to manipulate the flash memory is illustrated below. Figure 6-11 Flash memory manipulation procedure Flash memory programming mode To rewrite the contents of the flash memory by using the flash programmer, set the microcontroller in the flash memory programming mode.
Page 245 Flash Memory Chapter 6 RESET (input) FLMD1 (input) FLMD0 (input) (Note) RXDA0 (input) TXDA0 (output) Oscillation Communication stabilization mode selection Power Reset Flash control command communication supply release (such as erase and write) Figure 6-12 Flash memory programming mode start-up Note The number of clocks to be inserted differs depending on the chosen communication mode.
Page 246 Chapter 6 Flash Memory Communication commands The microcontroller communicates with the flash programmer via commands. The commands sent to the microcontroller are called commands, and the response signals sent by the microcontroller to the flash programmer are called response commands. Command Axxxx Bxxxxx...
Page 247 Flash Memory Chapter 6 The microcontroller returns a response command to the command issued by the flash programmer. The response commands sent by the microcontroller are listed below. Table 6-7 Response commands Response command name Function Acknowledges command/data. Acknowledges illegal command/data. Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com...
Page 248 Chapter 6 Flash Memory Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 249: Chapter 7 Bus And Memory Control (Bcu, Memc)
Chapter 7 Bus and Memory Control (BCU, MEMC) Besides providing access to on-chip peripheral I/Os, the µPD70F3427 microcontroller device supports access to external memory devices (such as external ROM and RAM) and external I/O. The Bus Control Unit BCU and Memory Controller MEMC control the access to on-chip peripheral I/Os and to external devices.
Page 250: Description
WAIT Bus Bridge (BBR) BCLK Internal Bus (NPB) On-chip Peripheral I/O Figure 7-1 Bus and Memory Control diagram Busses The busses are abbreviated as follows: • NPB: NEC peripheral bus Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 251 Bus and Memory Control (BCU, MEMC) Chapter 7 • VSB: V850 system bus • VDB: V850 data bus • VFB: V850 fetch bus The Bus Control Unit (BCU) controls the access to on-chip peripherals, to external memory controller (MEMC), the VSB RAM and VSB Flash of the µPD70F3426 device.
Page 252: Memory Banks And Chip Select Signals
Chapter 7 Bus and Memory Control (BCU, MEMC) ROMC To access external ROM with page access function (page ROM), the Page ROM Controller (ROMC) is provided. It can handle page widths from 8 to 128 bytes. For more details, see “Page ROM Controller” on page 279. Note If the concerned pins are configured as external memory bus pins change between input and output is performed automatically by memory controller’s...
Page 253 Bus and Memory Control (BCU, MEMC) Chapter 7 03FF FFFFH 03FF FFFFH Bank 15 Peripheral I/O area (2 MB) (4 KB) 03E0 0000H 03FF F000H Bank 14 VDB RAM (2 MB) (60 KB) 03C0 0000H 03FF 0000H Programmable peripheral Bank 13 I/O area (PPA) (2 MB) 03A0 0000H...
Page 254 Chapter 7 Bus and Memory Control (BCU, MEMC) 03FF FFFFH 03FF FFFFH Bank 15 Peripheral I/O area (2 MB) (4 KB) 03E0 0000H 03FF F000H Bank 14 VDB RAM (2 MB) (60 KB) 03C0 0000H 03FF 0000H Programmable peripheral Bank 13 I/O area (PPA) (2 MB) 03A0 0000H...
Page 255: Chips Select Priority Control
Bus and Memory Control (BCU, MEMC) Chapter 7 7.2.2 Chips select priority control The chip select signals CS0 to CS7 can be assigned to overlapping memory areas by setting the chip select area control registers CSC0 and CSC1. The chip select priority control rules the generation of chip select signals in this case.
Page 256 I/O area and assigns an additional 12 KB address space for accessing on-chip peripherals. The figure below illustrates the programmable peripheral I/O area (PPA). 3FF FFFFH Peripheral I/O register NPB (NEC Periheral Bus) (4 KB) 3FF F000H 3FF EFFFH same area base + 3FFFH...
Page 257: Npb Access Timing
Bus and Memory Control (BCU, MEMC) Chapter 7 7.2.4 NPB access timing All accesses to the peripheral I/O areas are passed over to the NPB bus via the VSB - NPB bus bridge BBR. Read and write access times to registers via the NPB depend on the register (refer to “Registers Access Times”...
Page 258: Boundary Operation Conditions
Chapter 7 Bus and Memory Control (BCU, MEMC) Table 7-4 Bus priority order Priority External bus cycle Bus master High DMA cycle DMA Controller Operand data access Instruction fetch Bus access The number of CPU clocks necessary for accessing each resource – independent of the bus width –...
Page 259: Initialization For Access To External Devices
Bus and Memory Control (BCU, MEMC) Chapter 7 7.2.7 Initialization for access to external devices To enable access to external devices, initialize the following registers after any reset. 1. Chip area select control registers CSCn Define the memory banks that are allocated to external devices. Memory banks that are not allocated to external devices, must be deactivated.
Page 260: Registers
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.3 Registers Access to on-chip peripherals, to external memory, and to external I/O is controlled and operated by registers of the Bus Control Unit (BCU) and of the Memory Controller (MEMC): Table 7-6 Bus and memory control register overview Module Register name...
Page 261: Bcu Registers
Bus and Memory Control (BCU, MEMC) Chapter 7 7.3.1 BCU registers The following registers are part of the BCU. They define the usage of the programmable peripheral I/O area (PPA), the data bus width, the endian format of word data, and they control access to external devices. BPC - Peripheral area selection control register The 16-bit BPC register defines whether the programmable peripheral I/O area (PPA) is used or not and determines the starting address of the PPA.
Page 262 Chapter 7 Bus and Memory Control (BCU, MEMC) Note The recommended setting for the BPC register is 8FFB . With this configuration the programmable peripheral area is mapped to the address range 03FE C000 to 03FE FFFF . With this setting the CAN message buffer registers are accessible via the addresses given in “CAN Controller (CAN)”...
Page 263 Bus and Memory Control (BCU, MEMC) Chapter 7 VSWC - Internal peripheral function wait control register The 8-bit VSWC register defines the wait states inserted when accessing peripheral special function registers via the internal bus. Both address setup and data wait states are based on the system clock. Access This register can be read/written in 8-bit or 1-bit units.
Page 264 Chapter 7 Bus and Memory Control (BCU, MEMC) The following setups are recommended for VSWC: Table 7-10 Recommended timing for internal bus System ≤ 16 MHz ≤ 25 MHz ≤ 33 MHz ≤ 50 MHz ≤ 66 MHz ≤ 75 MHz clock VBCLK SUWL...
Page 265 Bus and Memory Control (BCU, MEMC) Chapter 7 CSCn - Chip area select control registers The 16-bit registers CSC0 and CSC1 assign the chip select signals CS0 to CS3 and CS4 to CS7 to memory blanks (see also “Memory banks and chip select signals”...
Page 266 Chapter 7 Bus and Memory Control (BCU, MEMC) Table 7-11 CSC0 register contents Chip select Bit Position Bit Name Access to memory bank signal CS33 CS32 CS31 4 or 5 CS30 0, 1, 2 or 3 CS23 CS22 CS21 CS20 CS13 CS12 CS11...
Page 267 Bus and Memory Control (BCU, MEMC) Chapter 7 Initialization Initialize the CSCn registers as shown in • Table 7-13 for µPD70F3426 • Table 7-14 for µPD70F3427 Table 7-13 Initialization of the µPD70F3426 CSCn registers Bits Set to value Comment CSC0.CS0[3:0] 0001 CS0 assigned to bank 0 to VSB Flash memory 010 0000...
Page 268 Chapter 7 Bus and Memory Control (BCU, MEMC) Table 7-14 Initialization of the µPD70F3427 CSCn registers Bits Set to value Comment CSC0.CS0[3:0] xx00 Set CSC0.CS0[3:2] as required to assign CS0 to bank 2 to 3 to external memory 040 0000 - 07F FFFF Caution: CSC0.CS0[1:0] must be changed...
Page 269 Bus and Memory Control (BCU, MEMC) Chapter 7 BEC - Endian configuration register The 16-bit BEC register defines the endian format in which word data in the memory is processed. Each chip select area is controlled separately. Access This register can be read/written in 16-bit units. Address FFFF F068 Initial Value...
Page 270 Chapter 7 Bus and Memory Control (BCU, MEMC) Initialization Initialize the BEC register as shown in • Table 7-16 for µPD70F3426 • Table 7-17 for µPD70F3427 Table 7-16 Initialization of the µPD70F3426 BEC register Bits Set to value Comment BEC.BE00 Endian format for VSB Flash memory: little endian BEC.BE00 must be left with their default value...
Page 271: Memory Controller Registers (Μpd70F3427 Only)
Bus and Memory Control (BCU, MEMC) Chapter 7 7.3.2 Memory controller registers (µPD70F3427 only) The following registers are part of the Memory Controller. They specify the type of external device that is connected, the number of data wait states, the number of address wait states, the number of idle states, and they control features for page ROM.
Page 272 Chapter 7 Bus and Memory Control (BCU, MEMC) LBS - Local bus size configuration register The 16-bit LBS register controls the data bus width for each chip select area. Access This register can be read/written in 16-bit units. Address FFFF F48E Initial Value AAAA LB71 LB70 LB61 LB60 LB51 LB50 LB41 LB40 LB31 LB30 LB21 LB20 LB11 LB10 LB01 LB00...
Page 273 Bus and Memory Control (BCU, MEMC) Chapter 7 ASC - Address setup wait control register The 16-bit ASC register controls the number of wait states between address setup and the first access cycle (T1). Each chip select area is controlled separately.
Page 274 Chapter 7 Bus and Memory Control (BCU, MEMC) DWCn - Data wait control registers The 16-bit DWCn registers control the number of wait states after the first access cycle (T1). Each chip select area is controlled separately. A maximum of seven data wait states is possible. Access This register can be read/written in 16-bit units.
Page 275 Bus and Memory Control (BCU, MEMC) Chapter 7 BCC - Bus cycle control register The 16-bit BCC register controls the number of idle states inserted after the T2 cycle. Each chip select area is controlled separately. A maximum of three idle states is possible.
Page 276 Chapter 7 Bus and Memory Control (BCU, MEMC) RDDLY - Read delay control register The 8-bit RDDLY register controls the delay of the read strobe RD of the external memory interface. It provides the option to delay the rising edge of the RD by a half of the bus clock cycle BCLK.
Page 277 Bus and Memory Control (BCU, MEMC) Chapter 7 PRC - Page ROM configuration register The 16-bit PRC register controls whether a page ROM cycle is on-page or off-page. The register specifies the address mask. Masked address bits are not considered when deciding between on-page or off-page access. Set the mask according to the number of continuously readable bits.
Page 278 Chapter 7 Bus and Memory Control (BCU, MEMC) Note To initialize an external memory area after a reset, register PRC has to be set if page ROM mode is selected. Do not change this register after initialization. Do not access external page ROM devices before initialization is finished. Caution To initialize an external memory area after a reset, this register has to be set.
Page 279: Page Rom Controller
Bus and Memory Control (BCU, MEMC) Chapter 7 7.4 Page ROM Controller In page ROM mode the microcontroller reads consecutive data from one page by inserting the wait cycles defined by PRC.PRW[2:0] instead of wait cycles defined in registers DWC0 and DWC1. The page ROM controller decides whether a page ROM cycle is on-page or off-page.
Page 280 Chapter 7 Bus and Memory Control (BCU, MEMC) 16-bit data bus width The page size or the number of continuously readable bits is 8 x 16 bit. To provide 8 addresses, a 3-bit on-page address is required. Therefore, set PRC.MA[6:3] = 0001 Note For a 16-bit data bus, bit A0 of the output address is not used.
Page 281 Bus and Memory Control (BCU, MEMC) Chapter 7 Internal address latch (immediately preceding address) PRC register setting Comparison Output address Page ROM address Off-page address On-page address Figure 7-7 16-Mbit page ROM (512 k × 32 bits), page size 2 x 32 bit Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com...
Page 282: Configuration Of Memory Access
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.5 Configuration of Memory Access The microcontroller device supports interfacing with various memory devices. Therefore, the endian format, wait functions and idle state insertions can be configured. 7.5.1 Endian format The endian format is specified with the endian configuration register (BEC). It defines the byte order in which word data is stored.
Page 283 Bus and Memory Control (BCU, MEMC) Chapter 7 Programmable wait function With the purpose of realizing easy interfacing with low-speed memory or with I/Os, it is possible to insert up to seven data wait states after the first access cycle (T1 state). The number of wait states can be specified by data wait control registers DWC0 and DWC1.
Page 284: Idle State Insertion
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.5.3 Idle state insertion To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted between two bus cycles, that means after the T2 state. Idle states are inserted to meet the data output float delay time on memory read access for each CS space.
Page 285: Writing To External Devices
Bus and Memory Control (BCU, MEMC) Chapter 7 7.6.1 Writing to external devices This section shows typical sequences of writing data to external devices. Write with external wait cycle BCLK Address Address A[23:0] (output) CSk (output) RD (output) WR (output) D]31:0] (I/O) Data Data...
Page 286 Chapter 7 Bus and Memory Control (BCU, MEMC) Write with address setup wait and idle state insertion TASW BCLK Address A[23:0] (output) CSk (output) RD (output) WR (output) D[31:0] (I/O) Data WAIT (input) Figure 7-12 Timing: write data with address setup wait and idle state insertion Register settings: •...
Page 287: Reading From External Devices
Bus and Memory Control (BCU, MEMC) Chapter 7 7.6.2 Reading from external devices This section shows typical sequences of reading data from external devices. Read with external wait cycle BCLK Address Address A[23:0] (output) CSk (output) RD (output) WR (output) Data Data D[31:0] (I/O)
Page 288 Chapter 7 Bus and Memory Control (BCU, MEMC) Read with address setup wait and idle state insertion TASW BCLK Address A[23:0] (output) CSk (output) RD (output) WR (output) D[31:0] (I/O) Data WAIT (input) Figure 7-14 Timing: read data with address setup wait and idle state insertion Register settings: •...
Page 289: Read-Write Operation On External Devices
Bus and Memory Control (BCU, MEMC) Chapter 7 7.6.3 Read-write operation on external devices BCLK A[23:0] (output) Address CSk (output) RD (output) WR (output) D[31:0] (I/O) DataData WAIT (input) Figure 7-15 Read-write operation Register settings: • BCTm.BTk0 = 0 (connected external device is SRAM or external I/O) •...
Page 290: Write-Read Operation On External Devices
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.6.4 Write-read operation on external devices BCLK Address A[23:0] (output) CSk (output) RD (output) WR (output) Data D[31:0] (I/O) Data WAIT (input) Figure 7-16 Write-read operation Register settings: • BCTm.BTk0 = 0 (connected external device is SRAM or external I/O) •...
Page 291: Page Rom Access Timing
Bus and Memory Control (BCU, MEMC) Chapter 7 7.7 Page ROM Access Timing This section presents examples of read operations on page ROM. The states are abbreviated as: • T1 and T2 states: Basic states for access. • TW state: Wait state that is inserted according to the DWC0 and DWC1 register settings and according to the WAIT input.
Page 292: Half Word/Word Access With 8-Bit Bus Or Word Access With 16-Bit Bus
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.7.1 Half word/word access with 8-bit bus or word access with 16- bit bus Read operation Note that during on-page access, less data wait states are inserted than during off-page access. BCLK A[23:0] (output) Off-page address On-page address...
Page 293 Bus and Memory Control (BCU, MEMC) Chapter 7 Read operation with address setup wait states and idle state insertion TASW TASW BCLK A[23:0] (output) Off-page address On-page address CSk (output) RD (output) WR (output) D[7:0] (I/O) Data Data D[15:0] (I/O) WAIT (input) BCC.BCk[1:0] Figure 7-18...
Page 294: Byte Access With 8-Bit Bus Or Byte/Half Word Access With 16-Bit Bus
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.7.2 Byte access with 8-bit bus or byte/half word access with 16- bit bus Read operation Note that during on-page access, less data wait states are inserted than during off-page access. BCLK Off-page address On-page address A[23:0] (output)
Page 295 Bus and Memory Control (BCU, MEMC) Chapter 7 Read operation with address setup wait states and idle state insertion TASW TASW BCLK A[23:0] (output) Off-page address On-page address CSk (output) RD (output) WR (output) D[7:0] (I/O) Data Data D[15:0] (I/O) WAIT (input) BCC.BCk[1:0] Figure 7-20...
Page 296: Data Access Order
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.8 Data Access Order 7.8.1 Access to 8-bit data busses This section shows how byte, half word and word accesses are performed for an 8-bit data bus. Byte access (8 bits) (a) Little endian Address Address 2n + 1...
Page 297 Bus and Memory Control (BCU, MEMC) Chapter 7 Halfword access (16 bits) (a) Little endian 1-st Access 1-st Access 2-nd Access 2-nd Access Address Address Address Address 2n + 1 2n + 1 2n + 2 Halfword External Halfword External Halfword External Halfword...
Page 298 Chapter 7 Bus and Memory Control (BCU, MEMC) Word access (32 bits) (a) Little endian 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data External Word data External...
Page 299 Bus and Memory Control (BCU, MEMC) Chapter 7 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data External Word data External Word data External...
Page 300 Chapter 7 Bus and Memory Control (BCU, MEMC) (b) Big endian 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data External Word data External Word data External...
Page 301 Bus and Memory Control (BCU, MEMC) Chapter 7 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data External Word data External Word data External...
Page 302: Access To 16-Bit Data Busses
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.8.2 Access to 16-bit data busses This section shows how byte, half word and word accesses are performed for a 16 bit data bus. Access all data in order starting from the lower order side. Byte access (8 bits) (a) Little endian Address...
Page 303 Bus and Memory Control (BCU, MEMC) Chapter 7 Halfword access (16 bits) (a) Little endian 1-st Access 2-nd Access Address Address Address 2n + 1 2n + 1 2n + 2 Halfword External Halfword External Halfword External data data bus data data bus data...
Page 304 Chapter 7 Bus and Memory Control (BCU, MEMC) Word access (32 bits) (a) Little endian 1-st Access 2-nd Access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data External data bus data bus Figure 7-37 Access to address 4n 1-st Access...
Page 305 Bus and Memory Control (BCU, MEMC) Chapter 7 1-st Access 2-nd Access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data External data bus data bus Figure 7-39 Access to address 4n + 2 1-st Access 2-nd Access 3-rd Access...
Page 306 Chapter 7 Bus and Memory Control (BCU, MEMC) (b) Big endian 1-st Access 2-nd Access Address Address 4n + 2 4n + 1 4n + 3 Word data External Word data External data bus data bus Figure 7-41 Access to address 4n 3-rd Access 1-st Access 2-nd Access...
Page 307 Bus and Memory Control (BCU, MEMC) Chapter 7 1-st Access 2-nd Access Address Address 4n + 2 4n + 4 4n + 3 4n + 5 Word data External Word data External data bus data bus Figure 7-43 Access to address 4n + 2 1-st Access 2-nd Access 3-rd Access...
Page 308 Chapter 7 Bus and Memory Control (BCU, MEMC) Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 309: Chapter 8 Dma Controller (Dmac)
Chapter 8 DMA Controller (DMAC) The microcontroller includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfers. Note Throughout this chapter, the individual channels of the DMA Controller are identified by “n”. The DMAC controls data transfer between memory and I/O or among I/Os, based on DMA requests issued by the on-chip peripheral I/O, or software triggers.
Page 310: Peripheral And Cpu Clock Settings
Chapter 8 DMA Controller (DMAC) 8.2 Peripheral and CPU Clock Settings In order to ensure safe capture of DMA trigger signals from the involved peripheral functions, a certain minimum relation between the operation clock of the concerned peripheral function and the CPU system has to be regarded. In the following table the minimum CPU system clock frequency f is given VBCLK...
Page 311 DMA Controller (DMAC) Chapter 8 Table 8-1 Peripheral functions and CPU system clocks for DMA transfers (2/2) SPCLKn, PCLKn Minimum Input clock configuration Peripheral Clock controller settings VBCLK [MHz] [MHz] Peripheral clock Source ICC = 00 IICLK MainOsc 6.00 ICC = 72 PLL / 4.5 7.11 10.67...
Page 312: Dmac Registers
Chapter 8 DMA Controller (DMAC) 8.3 DMAC Registers 8.3.1 DMA Source address registers These registers are used to set the DMA source addresses (28 bits each) for DMA channel n. They are divided into two 16-bit registers, DSAHn and DSALn. Since these registers are configured as 2-stage FIFO buffer registers, a new source address for DMA transfer can be specified during DMA transfer (refer to “Automatic Restart Function”...
Page 313 DMA Controller (DMAC) Chapter 8 DSALn - DMA source address registers Ln These registers can be read/written in 16-bit units. Initial Address value DSAL0 SA15 SA14 SA13 SA12 SA11 SA10 FFFFF080H undef. Initial Address value DSAL1 SA15 SA14 SA13 SA12 SA11 SA10 FFFFF088H...
Page 314: Dma Destination Address Registers
Chapter 8 DMA Controller (DMAC) 8.3.2 DMA destination address registers These registers are used to set the DMA destination address (28 bits each) for DMA channel n. They are divided into two 16-bit registers, DDAHn and DDALn. Since these registers are configured as 2-stage FIFO buffer registers, a new destination address for DMA transfer can be specified during DMA transfer (refer to “Automatic Restart Function”...
Page 315 DMA Controller (DMAC) Chapter 8 DDALn - DMA destination address registers Ln These registers can be read/written in 16-bit units. Initial Address value DDAL0 DA15 DA14 DA13 DA12 DA11 DA10 FFFFF084H undef. Initial Address value DDAL1 DA15 DA14 DA13 DA12 DA11 DA10 FFFFF08CH...
Page 316: Dbcn - Dma Transfer Count Registers
Chapter 8 DMA Controller (DMAC) 8.3.3 DBCn - DMA transfer count registers These 16-bit registers are used to set the transfer counts for DMA channels n. They store the remaining transfer counts during DMA transfer. Since these registers are configured as 2-stage FIFO buffer registers, a new DMA transfer count for DMA transfer can be specified during DMA transfer (refer to “Automatic Restart Function”...
Page 317: Dadcn - Dma Addressing Control Registers
DMA Controller (DMAC) Chapter 8 8.3.4 DADCn - DMA addressing control registers These 16-bit registers are used to control the DMA transfer modes for DMA channel n. They can be read/written in 16-bit units. Initial Address value DADC0 SAD1 SAD0 DAD1 DAD0 FFFFF0D0H 0000H Initial...
Page 318 Chapter 8 DMA Controller (DMAC) Bit position Bit name Function 3, 2 TM1, TM0 Sets the transfer mode during DMA transfer. Transfer mode Single transfer mode Setting prohibited Setting prohibited Block transfer mode Caution These registers cannot be accessed during DMA operation. Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com...
Page 319: Dchcn - Dma Channel Control Registers
DMA Controller (DMAC) Chapter 8 8.3.5 DCHCn - DMA channel control registers These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n. These registers can be read/written in 8-bit or 1-bit units. (However, bit 7 is read only and bits 2 and 1 are write only.
Page 320: Drst - Dma Restart Register
Chapter 8 DMA Controller (DMAC) 8.3.6 DRST - DMA restart register The ENn bit of this register and the ENn bit of the DCHCn register are linked to each other. This provides a fast way to check the status of all DMA channels. This register can be read/written in 8-bit or 1-bit units.
Page 321: Dtfrn - Dma Trigger Source Select Register
DMA Controller (DMAC) Chapter 8 8.3.7 DTFRn - DMA trigger source select register The 8-bit DMA trigger source selection registers are used to control the DMA transfer triggers for the individual DMA channels. These triggers initiate DMA transfer requests received from built-in peripheral hardware. Interrupt signals are used as DMA transfer requests.
Page 322 Chapter 8 DMA Controller (DMAC) 2. Set the DMA request bit DTFRn.DRQn = 0 in parallel to changing DTFRn.IFCn[2:0], i.e. within the same write operation. Thus DTFRn must be written in 8-bit access mode. Do not change DTFRn.IFCn[2:0] with single-bit instructions. The following list details the functions of the individual DMA trigger sources referenced in the above table.
Page 323: Automatic Restart Function
DMA Controller (DMAC) Chapter 8 Set DMACTn according to the following table: Source \ Destination Internal RAM Peripherals Internal RAM – Peripherals 8.4 Automatic Restart Function The DMA source address registers (DSAHn, DSALn), DMA destination address registers (DDAHn, DDALn), and DMA transfer count register (DBCn) are buffer registers with a 2-stage FIFO structure, named master and slave register.
Page 324: Transfer Type
Chapter 8 DMA Controller (DMAC) Data read Address/ Data write Master Slave count register register controller Figure 8-1 Buffer register configuration 8.5 Transfer Type All DMA transfers of this microcontroller are two-cycle transfers. In two-cycle transfer, data transfer is performed in two cycles: a read cycle (source to DMAC) and a write cycle (DMAC to destination).
Page 325: Dma Channel Priorities
DMA Controller (DMAC) Chapter 8 8.7 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > … > DMA channel n In the single-step transfer mode, the DMA Controller releases the buses after each byte/half-word/word transfer.
Page 326: Forcible Termination
Chapter 8 DMA Controller (DMAC) NMI (input) Forcible Transfer Forcible interruption restart interruption DMA transfer DMA transfer stop DMA transfer DMA transfer stop EN0 bit of DCHC0 register Figure 8-2 Example of forcible interruption of DMA transfer Caution The resumed DMA transfer after NMI interruption cannot be executed with new settings.
Page 327: Dma Transfer Completion
DMA Controller (DMAC) Chapter 8 Note The next condition can be set even during DMA transfer because the DSAn, DDAn, and DBCn registers are buffered registers. However, the setting to the DADCn register is invalid (refer to “Automatic Restart Function” on page 323 and “DADCn - DMA addressing control registers”...
Page 328: Transfer Mode
Chapter 8 DMA Controller (DMAC) 8.12 Transfer Mode 8.12.1 Single transfer mode In single transfer mode, the DMAC releases the bus after each byte/halfword/ word transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 329 DMA Controller (DMAC) Chapter 8 Figure 8-6 shows DMAC transfers in single transfer mode in which a higher priority DMA transfer request is generated. DMA channels 0 to 2 are used for a block transfer and channel 3 is used for a single transfer. DMA Transfer Request CH0 DMA Transfer...
Page 330: Block Transfer Mode
Chapter 8 DMA Controller (DMAC) Figure 8-8 shows a single transfer mode example in which two or more lower priority DMA transfer requests are generated within one clock after the end of a single transfer. DMA channels 0, 2 and 3 are used for this single transfer example.
Page 331: Chapter 9 Rom Correction Function (Romc)
Chapter 9 ROM Correction Function (ROMC) This microcontroller features following ROM correction facilities: • “DBTRAP” ROM correction: – 1x 8 channels for VFB flash memory and ROM – 1 x 8 channels for VSB flash memory (for µPD70F3426 only) The individual channels of each “DBTRAP” ROM correction are identified by “m”...
Page 332: Dbtrap" Rom Correction Unit
Chapter 9 ROM Correction Function (ROMC) 9.2 “DBTRAP” ROM Correction Unit • 1x 8 channels for VFB flash memory and ROM • The individual channels of the “DBTRAP” ROM correction unit are identified by “m” (m = 0 to 7) •...
Page 333: Dbtrap" Rom Correction Operation
ROM Correction Function (ROMC) Chapter 9 9.2.1 “DBTRAP” ROM correction operation The “DBTRAP” ROM correction unit compares the address on the V850 fetch bus (VFB) with the contents of the programmable correction address registers CORADm. If an address matches, the DBTRAP instruction opcode is put on the V850 fetch bus instead of the ROM contents.
Page 334 Chapter 9 ROM Correction Function (ROMC) Reset & start Initialize microcontroller Set CORADm register Read data for setting ROM Load DBTRAP exception correction from external handler and ROM correction code Set CORCN register CORENm bit = 1? Execute fetch code Fetch address = CORADm? Execute fetch code...
Page 335: Dbtrap" Rom Correction Registers
ROM Correction Function (ROMC) Chapter 9 9.2.2 “DBTRAP” ROM correction registers CORCN - VFB flash/ROM “DBTRAP” ROM correction control register This register enables or disables the VFB flash/ROM ROM correction of each channel. Access This register can be read/written in 8- and 1-bit units. Address FFFF F880 Initial Value...
Page 336 Chapter 9 ROM Correction Function (ROMC) CORADm - VFB flash/ROM “DBTRAP” ROM Correction address register These registers hold the address where the VFB flash/ROM correction should be performed. Access These registers can be read/written in 32-bit (CORADm) and 16-bit units (CORADmL for bits 15 to 0, CORADmH for bits 31 to 16).
Page 337 ROM Correction Function (ROMC) Chapter 9 COR2ADm - VSB flash “DBTRAP” ROM Correction address register (µPD70F3427 only) These registers hold the address where the VSB flash memory correction should be performed. Access These registers can be read/written in 32-bit (COR2ADm) and 16-bit units (COR2ADmL for bits 15 to 0, COR2ADmH for bits 31 to 16).
Page 338 Chapter 9 ROM Correction Function (ROMC) Siemens VDO Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 339: Chapter 10 Code Protection And Security
Chapter 10 Code Protection and Security 10.1 Overview The microcontroller supports various methods for protecting the program code in the flash memory from undesired access, such as illegal read-out or illegal reprogramming. Some interfaces offer in general access to the internal flash memory: N-Wire debug interface, external flash programmer interface, self-programming facilities and test interfaces.
Page 340 Chapter 10 Code Protection and Security Table 10-1 Possible results of ID code comparison N-Wire use enable flag ID code Protection Level Level 2: Full protection N-Wire debug interface cannot be used. user-specific Level 1: ID code protection ID code N-Wire debug interface can only be used if the user enters the correct ID code.
Page 341: Flash Writer And Self-Programming Protection
Code Protection and Security Chapter 10 10.4 Flash Writer and Self-Programming Protection In general, illegal read-out and re-programming of the flash memory contents is possible via the flash writer interface and the self-programming feature. For protection of the flash memory, the following flags provide various protection levels.
Page 342 Chapter 10 Code Protection and Security Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 343: Chapter 11 16-Bit Timer/Event Counter P (Tmp)
Chapter 11 16-bit Timer/Event Counter P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The V850E/Dx3 microcontrollers have following instances of the 16-bit timer/ event counter TMP: All devices Instances Names TMP0 to TMP3 Throughout this chapter, the individual instances of Timer P are identified by “n”, for example TMPn, or TPnCTL0 for the TMPn control register 0.
Page 344: Functions
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.2 Functions TMPn has the following functions. • Interval timer • External event counter • External trigger pulse output • One-shot pulse output • PWM output • Free-running timer • Pulse width measurement •...
Page 345 16-bit Timer/Event Counter P (TMP) Chapter 11 The second (PCLK01) and the third (PCLK02) clock selector input is not supplied from the clock generator, but derived from the first selector input PCLK0 inside the timer P. In case the PLL is disabled the PCLKx clocks are supplied from the main oscillator, i.e.: •...
Page 346: Tmp Registers
Chapter 11 16-bit Timer/Event Counter P (TMP) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. 11.4 TMP Registers The TMPn are controlled and operated by means of the following registers: Table 11-1 TMPn registers overview Register name...
Page 347 16-bit Timer/Event Counter P (TMP) Chapter 11 TPnCTL0 - TMPn control register 0 The TPnCTL0 register is an 8-bit register that controls the operation of TMPn. Access This register can be read/written in 8-bit or 1-bit units. Address <base> Initial Value .
Page 348 Chapter 11 16-bit Timer/Event Counter P (TMP) TPnCTL1 - TMPn control register 1 The TPnCTL1 register is an 8-bit register that controls the operation of TMPn. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 1 Initial Value .
Page 349 16-bit Timer/Event Counter P (TMP) Chapter 11 Set the TPnEEE and TPnMD2 to TPnMD0 bits when the TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit = 1.) The operation is not guaranteed when rewriting is performed with the TPnCE bit = 1.
Page 350 Chapter 11 16-bit Timer/Event Counter P (TMP) TPnIOC1 - TMPn I/O control register 1 The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0, TIPn1 pins). Access This register can be read/written in 8-bit or 1-bit units. Address <base>...
Page 351 16-bit Timer/Event Counter P (TMP) Chapter 11 TPnIOC2 - TMPn I/O control register 2 The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0 pin) and external trigger input signal (TIPn0 pin).
Page 352 Chapter 11 16-bit Timer/Event Counter P (TMP) TPnOPT0 - TMPn option register 0 The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. Access This register can be read/written in 8-bit or 1-bit units. Address <base>...
Page 353 16-bit Timer/Event Counter P (TMP) Chapter 11 TPnCCR0 - TMPn capture/compare register 0 The TPnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS0 bit.
Page 354 Chapter 11 16-bit Timer/Event Counter P (TMP) (b) Function as capture register When the TPnCCR0 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the TPnCCR0 register if the valid edge of the capture trigger input pin (TIPn0 pin) is detected.
Page 355 16-bit Timer/Event Counter P (TMP) Chapter 11 TPnCCR1 - TMPn capture/compare register 1 The TPnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS1 bit.
Page 356 Chapter 11 16-bit Timer/Event Counter P (TMP) (b) Function as capture register When the TPnCCR1 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the TPnCCR1 register if the valid edge of the capture trigger input pin (TIPn1 pin) is detected.
Page 357 16-bit Timer/Event Counter P (TMP) Chapter 11 TPnCNT - TMPn counter read buffer register The TPnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TPnCTL0.TPnCE bit = 1, the count value of the 16-bit timer can be read.
Page 358: Operation
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5 Operation TMPn can perform the following operations. TPnCTL1.TPnEST Bit TIPn0 Pin Capture/ Compare Compare Register Operation (Software Trigger Bit) (Ext. Trigger Input) Register Setting Write Interval timer mode Invalid Invalid Compare only Anytime write External event count Invalid...
Page 359 16-bit Timer/Event Counter P (TMP) Chapter 11 FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal Interval (D + 1) Interval (D + 1) Interval (D + 1) Interval (D + 1) Figure 11-3 Basic timing of operation in interval timer mode When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting.
Page 360 Chapter 11 16-bit Timer/Event Counter P (TMP) (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE TPnMD2 TPnMD1 TPnMD0 TPnCTL1 0, 0, 0: Interval timer mode (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnOE1 TPnOL0 TPnOE0 TPnIOC0 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting of output level with operation of TOPn0 pin disabled...
Page 361 16-bit Timer/Event Counter P (TMP) Chapter 11 Interval timer mode operation flow FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed Register initial setting before setting the TPnCE bit to 1.
Page 362 Chapter 11 16-bit Timer/Event Counter P (TMP) Interval timer mode operation timing (a) Operation if TPnCCR0 register is set to 0000H If the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated at each count clock, and the output of the TOPn0 pin is inverted. The value of the 16-bit counter is always 0000H.
Page 363 16-bit Timer/Event Counter P (TMP) Chapter 11 (c) Notes on rewriting TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 364 Chapter 11 16-bit Timer/Event Counter P (TMP) (d) Operation of TPnCCR1 register TPnCCR1 register Output TOPn1 pin CCR1 buffer register controller Match signal INTTPnCC1 signal Clear Count clock Output 16-bit counter TOPn0 pin selection controller Match signal INTTPnCC0 signal CCR0 buffer register TPnCE bit TPnCCR0 register Figure 11-5...
Page 365 16-bit Timer/Event Counter P (TMP) Chapter 11 FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal TPnCCR1 register TOPn1 pin output INTTPnCC1 signal ≥ D Figure 11-6 Timing chart when D If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the count value of the 16-bit counter does not match the value of the TPnCCR1 register.
Page 366 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal TPnCCR1 register TOPn1 pin output INTTPnCC1 signal Figure 11-7 Timing chart when D < D Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 367: External Event Count Mode (Tpnmd2 To Tpnmd0 = 001)
16-bit Timer/Event Counter P (TMP) Chapter 11 11.5.2 External event count mode (TPnMD2 to TPnMD0 = 001) In the external event count mode, the valid edge of the external event count input is counted when the TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the specified number of edges have been counted.
Page 368 Chapter 11 16-bit Timer/Event Counter P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
Page 369 16-bit Timer/Event Counter P (TMP) Chapter 11 (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnOE1 TPnOL0 TPnOE0 TPnIOC0 0: Disable TOPn0 pin output 0: Disable TOPn1 pin output 1: Enable TOPn1 pin output Setting of output level with operation of TOPn1 pin disabled 0: Low level 1: High level...
Page 370 Chapter 11 16-bit Timer/Event Counter P (TMP) Caution When the compare register TPnCCR0 (TPnCCR1) is set to 0000 and the external event counter mode is started the first interrupt INTTPnCC0 (INTTPnCC1) occurs upon the first timer overflow (TPnCNT: → FFFF 0000 ), but not with the first external count event.
Page 371 16-bit Timer/Event Counter P (TMP) Chapter 11 External event count mode operation flow FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 register is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1.
Page 372 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation timing in external event count mode (a) Operation if TPnCCR0 register is set to 0000H If the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated each time the valid signal of the external event count signal has been detected.
Page 373 16-bit Timer/Event Counter P (TMP) Chapter 11 (c) Notes on rewriting the TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 374 Chapter 11 16-bit Timer/Event Counter P (TMP) (d) Operation of TPnCCR1 register TPnCCR1 register Output CCR1 buffer register TOPn1 pin controller Match signal INTTPnCC1 signal Clear Edge TIPn0 pin 16-bit counter detector Match signal INTTPnCC0 signal TPnCE bit CCR0 buffer register TPnCCR0 register Figure 11-11 Configuration of TPnCCR1 register...
Page 375 16-bit Timer/Event Counter P (TMP) Chapter 11 If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the INTTPnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TPnCCR1 register do not match.
Page 376: External Trigger Pulse Output Mode (Tpnmd2 To Tpnmd0 = 010)
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOPn1 pin.
Page 377 16-bit Timer/Event Counter P (TMP) Chapter 11 FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (software trigger) TPnCCR1 register INTTPnCC1 signal TOPn1 pin output Wait Active level Active level Active level width (D width (D...
Page 378 Chapter 11 16-bit Timer/Event Counter P (TMP) Setting of registers in external trigger pulse output mode (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 379 16-bit Timer/Event Counter P (TMP) Chapter 11 (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnOE1 TPnOL0 TPnOE0 TPnIOC0 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Settings of output level while operation of TOPn0 pin is disabled 0: Low level 1: High level 0: Disable TOPn1 pin output...
Page 380 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation flow in external trigger pulse output mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output (software trigger) TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output...
Page 381 16-bit Timer/Event Counter P (TMP) Chapter 11 <1> Count operation start flow <3> PnCCR0, TPnCCR1 register setting change flow Only writing of the TPnCCR1 START register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of the Setting of TPnCCR1 register TPnCCRm register is transferred...
Page 382 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output (software trigger) TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output In order to transfer data from the TPnCCRm register to the CCRm buffer register, the TPnCCR1 register must be written.
Page 383 16-bit Timer/Event Counter P (TMP) Chapter 11 (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically. Count clock −...
Page 384 Chapter 11 16-bit Timer/Event Counter P (TMP) (c) Conflict between trigger detection and match with TPnCCR1 register If the trigger is detected immediately after the INTTPnCC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOPn1 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened.
Page 385 16-bit Timer/Event Counter P (TMP) Chapter 11 (d) Conflict between trigger detection and match with TPnCCR0 register If the trigger is detected immediately after the INTTPnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOPn1 pin is extended by time from generation of the INTTPnCC0 signal to trigger detection.
Page 386 Chapter 11 16-bit Timer/Event Counter P (TMP) (e) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the external trigger pulse output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 387: One-Shot Pulse Output Mode (Tpnmd2 To Tpnmd0 = 011)
16-bit Timer/Event Counter P (TMP) Chapter 11 11.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOPn1 pin.
Page 388 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register INTTPnCC1 signal TOPn1 pin output Delay Active Delay Active Delay Active level width level width level width −...
Page 389 16-bit Timer/Event Counter P (TMP) Chapter 11 Setting of registers in one-shot pulse output mode (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 390 Chapter 11 16-bit Timer/Event Counter P (TMP) (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnOE1 TPnOL0 TPnOE0 TPnIOC0 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting of output level while operation of TOPn0 pin is disabled 0: Low level 1: High level 0: Disable TOPn1 pin output...
Page 391 16-bit Timer/Event Counter P (TMP) Chapter 11 Operation flow in one-shot pulse output mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TPnCCR1 register INTTPnCC1 signal TOPn1 pin output <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is...
Page 392 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation timing in one-shot pulse output mode (a) Note on rewriting TPnCCRm register To change the set value of the TPnCCRm register to a smaller value, stop counting once, and then change the set value. If the value of the TPnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 393 16-bit Timer/Event Counter P (TMP) Chapter 11 (b) Generation timing of compare match interrupt request signal (INTTPnCC1) The generation timing of the INTTPnCC1 signal in the one-shot pulse output mode is different from other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 394: Pwm Output Mode (Tpnmd2 To Tpnmd0 = 100)
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5.5 PWM output mode (TPnMD2 to TPnMD0 = 100) In the PWM output mode, a PWM waveform is output from the TOPn1 pin when the TPnCTL0.TPnCE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOPn0 pin.
Page 395 16-bit Timer/Event Counter P (TMP) Chapter 11 FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register NTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output Active period Cycle Inactive period − D + 1) + 1) Figure 11-22...
Page 396 Chapter 11 16-bit Timer/Event Counter P (TMP) Setting of registers in PWM output mode (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 397 16-bit Timer/Event Counter P (TMP) Chapter 11 (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external event count input. (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 398 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation flow in PWM output mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output <1> <2>...
Page 399 16-bit Timer/Event Counter P (TMP) Chapter 11 <1> Count operation start flow <3> TPnCCR0, TPnCCR1 register setting change flow Only writing of the TPnCCR1 START register must be performed when the set duty factor is changed. When the counter is cleared after setting, the Setting of TPnCCR1 register value of compare register m...
Page 400 Chapter 11 16-bit Timer/Event Counter P (TMP) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC1 signal is detected.
Page 401 16-bit Timer/Event Counter P (TMP) Chapter 11 (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically. Count clock −...
Page 402 Chapter 11 16-bit Timer/Event Counter P (TMP) (c) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the PWM output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 403: Free-Running Timer Mode (Tpnmd2 To Tpnmd0 = 101)
16-bit Timer/Event Counter P (TMP) Chapter 11 11.5.6 Free-running timer mode (TPnMD2 to TPnMD0 = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. At this time, the TPnCCRm register can be used as a compare register or a capture register, depending on the setting of the TPnOPT0.TPnCCS0 and TPnOPT0.TPnCCS1 bits.
Page 404 Chapter 11 16-bit Timer/Event Counter P (TMP) When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOPn0 and TOPn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TPnCCRm register, a compare match interrupt request signal (INTTPnCCm) is generated, and the output signal of the TOPnm pin is inverted.
Page 405 16-bit Timer/Event Counter P (TMP) Chapter 11 When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and a capture interrupt request signal (INTTPnCCm) is generated.
Page 406 Chapter 11 16-bit Timer/Event Counter P (TMP) Register setting in free-running timer mode (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1 (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 407 16-bit Timer/Event Counter P (TMP) Chapter 11 (d) TMPn I/O control register 1 (TPnIOC1) TPnIS3 TPnIS2 TPnIS1 TPnIS0 TPnIOC1 Select valid edge of TIPn0 pin input Select valid edge of TIPn1 pin input (e) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2...
Page 408 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation flow in free-running timer mode (a) When using capture/compare register as compare register FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register INTTPnCC1 signal TOPn1 pin output INTTPnOV signal TPnOVF bit <1>...
Page 409 16-bit Timer/Event Counter P (TMP) Chapter 11 <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1. TPnCTL1, TPnIOC0, TPnIOC2, TPnOPT0, TPnCCR0, TPnCCR1 The TPnCKS0 to TPnCKS2 bits can be set at the same time...
Page 410 Chapter 11 16-bit Timer/Event Counter P (TMP) (b) When using capture/compare register as capture register FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register 0000 0000 INTTPnCC0 signal TIPn1 pin input 0000 0000 TPnCCR1 register INTTPnCC1 signal INTTPnOV signal TPnOVF bit Cleared to 0 by Cleared to 0 by...
Page 411 16-bit Timer/Event Counter P (TMP) Chapter 11 <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1. TPnCTL1, TPnIOC1, TPnOPT0 The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting TPnCE bit = 1 has been started (TPnCE bit = 1).
Page 412 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TPnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTPnCCm signal has been detected.
Page 413 16-bit Timer/Event Counter P (TMP) Chapter 11 (b) Pulse width measurement with capture register When pulse width measurement is performed with the TPnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTPnCCm signal has been detected and for calculating an interval.
Page 414 Chapter 11 16-bit Timer/Event Counter P (TMP) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below.
Page 415 16-bit Timer/Event Counter P (TMP) Chapter 11 FFFFH 16-bit counter 0000H TPnCE bit INTTPnOV signal TPnOVF bit Note TPnOVF0 flag TIPn0 pin input TPnCCR0 register Note TPnOVF1 flag TIPn1 pin input TPnCCR1 register <1> <2> <3> <4> <5> <6> Figure 11-33 Example when two capture registers are used (using overflow interrupt) Note The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software.
Page 416 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit INTTPnOV signal TPnOVF bit Note TPnOVF0 flag TIPn0 pin input TPnCCR0 register Note TPnOVF1 flag TIPn1 pin input TPnCCR1 register <1> <2> <3> <4> <5> <6> Figure 11-34 Example when two capture registers are used (without using overflow interrupt) Note...
Page 417 16-bit Timer/Event Counter P (TMP) Chapter 11 (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next.
Page 418 Chapter 11 16-bit Timer/Event Counter P (TMP) If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software.
Page 419 16-bit Timer/Event Counter P (TMP) Chapter 11 (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register.
Page 420: Pulse Width Measurement Mode (Tpnmd2 To Tpnmd0 = 110)
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. Each time the valid edge input to the TIPnm pin has been detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and the 16-bit counter is cleared to 0000H.
Page 421 16-bit Timer/Event Counter P (TMP) Chapter 11 FFFFH 16-bit counter 0000H TPnCE bit TIPnm pin input TPnCCRm register 0000H INTTPnCCm signal INTTPnOV signal Cleared to 0 by TPnOVF bit CLR instruction Figure 11-38 Basic timing in pulse width measurement mode When the TPnCE bit is set to 1, the 16-bit counter starts counting.
Page 422 Chapter 11 16-bit Timer/Event Counter P (TMP) Register setting in pulse width measurement mode (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note Setting is invalid when the TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 423 16-bit Timer/Event Counter P (TMP) Chapter 11 (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external event count input (e) TMPn option register 0 (TPnOPT0) TPnCCS1 TPnCCS0 TPnOVF TPnOPT0 Overflow flag (f) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 424 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation flow in pulse width measurement mode FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register 0000H 0000H INTTPnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 is performed before setting the...
Page 425 16-bit Timer/Event Counter P (TMP) Chapter 11 Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register.
Page 426: Timer Output Operations
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5.8 Timer output operations The following table shows the operations and output levels of the TOPn0 and TOPn1 pins. Table 11-11 Timer output control in each mode Operation Mode TOPn1 Pin TOPn0 Pin Interval timer mode Square wave output External event count mode...
Page 427: Operating Precautions
16-bit Timer/Event Counter P (TMP) Chapter 11 11.6 Operating Precautions 11.6.1 Capture operation in pulse width measurement and free- running mode When the capture operation is used in pulse width measurement or free-run- ning mode the first captured counter value of the capture registers TPnCCR0/ TPnCCR, i.e.
Page 428 Chapter 11 16-bit Timer/Event Counter P (TMP) Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 429: Chapter 12 16-Bit Interval Timer Z (Tmz)
Chapter 12 16-bit Interval Timer Z (TMZ) Timer Z (TMZ) is a general purpose 16-bit timer/counter. The V850E/Dx3 microcontrollers have following instances of the general purpose Timer Z: µPD70F3427, µPD70F3426 µPD70F3423, µPD70(F)3422 µPD70F3425, µPD70F3424 µPD70(F)3421, µPD70(F)3420 Instances Names TMZ0 to TMZ9...
Page 430: Description
Chapter 12 16-bit Interval Timer Z (TMZ) 12.1.1 Description The TMZ has no external connections. It is built up as illustrated in the following figure. Internal bus TZnCTL TZnR TZCKS1 TZCKS0 TZCKS2 TZnCNT1 TZnCNT0 Reload buffer PCLK2 (4 MHz) 16-bit down counter INTTZnUV PCLK4 (1 MHz) TZnCNT...
Page 431: Tmz Registers
16-bit Interval Timer Z (TMZ) Chapter 12 12.2 TMZ Registers Each Timer Z is controlled and operated by means of the following four registers: Table 12-1 Timer Z registers overview Register name Shortcut Address Timer Z synchronized read register TZnCNT0 <base>...
Page 432 Chapter 12 16-bit Interval Timer Z (TMZ) TZnCTL - TMZn timer control register The 8-bit TZnCTL register controls the operation of the Timer Z. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 6 Initial Value .
Page 433 16-bit Interval Timer Z (TMZ) Chapter 12 TZnCNT0 - TMZn synchronized counter register The TZnCNT0 register is the synchronized register that can be used to read the present value of the 16-bit counter. “Synchronized” means that the read access via the internal bus is synchronized with the maximum counter clock (PCLK2).
Page 434 Chapter 12 16-bit Interval Timer Z (TMZ) TZnR - Reload register The TZnR register is a dedicated register for setting the reload value of the corresponding counter. Access This register can be read/written in 16-bit units. Address <base> + 4 Initial Value 0000 .
Page 435: Timing
16-bit Interval Timer Z (TMZ) Chapter 12 12.3 Timing The contents of the reload register TZnR can be changed at any time, provided the timer is enabled. The contents is then copied to the reload buffer. However, the counter reloads its start value from the buffer only upon underflow. Caution When specifying PCLK4, PLCK5, PCLK7 or PCLK9 as the count clock, a jitter of maximum ±...
Page 436: Timer Start And Stop
Chapter 12 16-bit Interval Timer Z (TMZ) 12.3.2 Timer start and stop The timer TZn is enabled by setting TZnCTL.TZCE to 1. Start The subsequent write access to register TZnR with non-zero data starts the timer. After that, it is prepared to load the value written to register TZnR into the reload buffer and the counter.
Page 437: Chapter 13 16-Bit Multi-Purpose Timer G (Tmg)
Chapter 13 16-bit Multi-Purpose Timer G (TMG) The V850E/Dx3 microcontrollers have following instances of the 16-bit multi- purpose Timer G: Throughout this chapter, the individual instances of Timer G are identified by “n”, for example TMGn, or TMGMn for the TMGn mode register.
Page 438: Function Overview Of Each Timer Gn
Chapter 13 16-bit Multi-Purpose Timer G (TMG) 13.2 Function Overview of Each Timer Gn • 16-bit timer/counter (TMGn0, TMGn1): 2 channels • Bit length – Timer Gn registers (TMGn0, TMGn1): 16 bits • Capture/compare register (GCCny): 6 – 16-bit – 2 registers are assigned fix to the corresponding one of the 2 counters –...
Page 439 16-bit Multi-Purpose Timer G (TMG) Chapter 13 SCPLK0 SCPLK0 INTTGnOV0 SCPLK0 COUNT0 SCPLK0 TMGn0 (16-bit) SPCLK0 (16 MHz) Clear SCPLK0 (Note 1) SCPLK0 SCPLK0 INTTGnCC0 /128 SCPLK0 GCCn0 (16-bit) Noise Elimination TIGn0 capture/compare Edge Detection (Note 2) INTTGnCC1 TOGn1 Noise Elimination GCCn1 (16-bit) TIGn1 Edge Detection...
Page 440: Basic Configuration
Chapter 13 16-bit Multi-Purpose Timer G (TMG) TIGn0 differs: – n = 0: TIG00 not connected – n = 1: TIG10 not connected – n = 2: TIG20 available as external capture input TIGn5 differs: – n = 0: CAN0 time stamp TSOUTCAN0 -> TIG05 –...
Page 441: Tmg Registers
16-bit Multi-Purpose Timer G (TMG) Chapter 13 13.4 TMG Registers The Timers Gn are controlled and operated by means of the following registers: Table 13-2 TMGn registers overview Register name Shortcut Address Timer Gn mode register TMGMn <base> Timer Gn channel mode register TMGCMn <base>...
Page 442 Chapter 13 16-bit Multi-Purpose Timer G (TMG) TMGMn - Timer Gn mode register Access This register can be read/written in 16-bit, 8-bit or 1-bit units. The low byte TMGMn.bit[7:0] is accessible separately under the name TMGMnL, the high byte TMGMn.bit[15:8] under the name TMGMnH. Address TMGMn, TMGMnL: <base>...
Page 443 16-bit Multi-Purpose Timer G (TMG) Chapter 13 Table 13-4 TMGMn register contents (2/2) Bit name Function position 7, 6 CCSGn5 Specifies the mode of the TMGn0 (TMGn1)(CCSGn5 for TMGn1, CCSGn0 for CCSGn0 TMGn0): 0: Free-run mode for TMGn1 (TMGn0), GCCn5 (GCCn0) in capture mode (an detected edge at Pin TIGn5 (TIGn0) stores the value of TMGn1 (TMGn0) in GCCn5 (GCCn0) and an interrupt INTCCGn5 (INTCCGn0) is output) 1: Match and Clear mode of the TMGn1 (TMGn0), GCCn5 (GCCn0) in compare...
Page 444 Chapter 13 16-bit Multi-Purpose Timer G (TMG) TMGCMn - Timer Gn channel mode register This register specifies the assigned counter (TMGn0 or TMGn1) for the GCCnm register. Furthermore it specifies the edge detection for the TIGny-input-pins. Access This register can be read/written in 16-bit, 8-bit or 1-bit units. The low byte TMGCMn.bit[7:0] is accessible separately under the name TMGCMnL, the high byte TMGCMn.bit[15:8] under the name TMGCMnH.
Page 445 16-bit Multi-Purpose Timer G (TMG) Chapter 13 OCTLGn - Timer Gn output control register This register controls the timer output from the TOGnm pin and the capture or compare modus for the GCCnm register. Access This register can be read/written in 16-bit, 8-bit or 1-bit units. The low byte OCTLGn.bit[7:0] is accessible separately under the name OCTLGnL, the high byte OCTLGn.bit[15:8] under the name OCTLGnH.
Page 446 Chapter 13 16-bit Multi-Purpose Timer G (TMG) TMGSTn - Time base status register The TMGSTn register indicates the status of TMGn0 and TMGn1. For the CCFGny bit see “Operation in Free-Run Mode“ on page 451. Access This register can be read/written in 8-bit or 1-bit units. Address <base>...
Page 447 16-bit Multi-Purpose Timer G (TMG) Chapter 13 GCCn0, GCCn5 - Timer Gn capture/compare registers of the 2 counters The GCCn0, GCCn5 registers are 16-bit capture/compare registers of Timer Gn. These registers are fixed assigned to the counter registers: • GCCn0 is fixed assigned to timebase TMGn0 •...
Page 448 Chapter 13 16-bit Multi-Purpose Timer G (TMG) GCCn1 to GCCn4 - Timer G capture/compare registers with external PWW-output function The GCCn1 to GCCn4 registers are 16-bit capture/compare registers of Timer Gn. They can be assigned to one of the two counters either TMGn0 or TMGn1. Capture mode In the capture register mode, these registers capture the value of TMGn0 when the TBGnm bit (m = 1 to 4) of the TMGCMnH register = 0.
Page 449: Output Delay Operation
16-bit Multi-Purpose Timer G (TMG) Chapter 13 13.5 Output Delay Operation When the OLDEn bit is set, different delays of count clock period are added to the TOGnm pins: Delay Output pin COUNT TOGn1 TOGn2 TOGn3 TOGn4 The figure below shows the timing for the case where the count clock is set to /2.
Page 450: Explanation Of Basic Operation
Chapter 13 16-bit Multi-Purpose Timer G (TMG) 13.6 Explanation of Basic Operation Overview of the mode settings The Timer Gn includes 2 channels of 16-bit counters (TMGn0/TMGn1), which can operate as independently timebases. TMGn0 (TMGn1) can be set by CCSGn0 bit (CCSGn5 bit) in the following modes: •...
Page 451: Operation In Free-Run Mode
16-bit Multi-Purpose Timer G (TMG) Chapter 13 Table 13-9 Interrupt output and timer output states dependent on the register setting values Register setting value State of each output pin CCSGn5 TBGnm SWFGnm CCSGnm INTTMGn1 INTCCGn5 INTCCGnm TOGnm TIm edge detection Tied to inactive GCCnm match level...
Page 452 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (a) Example: Pulse width or period measurement of the TIGny input signal (free run) Capture setting method: When using one of the TOGn1 to TOGn4 pins, select the corresponding counter with the TBGnm bit. When TIGn0 is used, the corresponding counter is TMGn0.
Page 453 16-bit Multi-Purpose Timer G (TMG) Chapter 13 COUNTx 0000H 0001H FFF FH 0000H TM G n0 C ount sta rt Cl ear TI Gn0 GCCn0 INTTGnCC0 INTGnOV0 CCFGn0 N o overf low Overf low N o overf low Figure 13-3 Timing when both edges of TIGn0 are valid (free run) Note The figure above shows an image.
Page 454 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (b) Timing of capture trigger edge detection The Tin inputs are fitted with an edge-detection and noise-elimination circuit. Because of this circuit, 3 periods to less than 4 periods of the count clock are required from edge input until an interrupt signal is output and capture operation is performed.
Page 455 16-bit Multi-Purpose Timer G (TMG) Chapter 13 (c) Timing of starting capture trigger edge detection A capture trigger input signal (TIGny) is synchronized in the noise eliminator for internal use. Edge detection starts when 1 count clock period (f ) has been input after COUNT timer count operation starts.
Page 456 Chapter 13 16-bit Multi-Purpose Timer G (TMG) Compare operation (free run) Basic settings (m = 1 to 4): Value Remark CCSGn0 free run mode CCSGn5 SWFGnm disable TOGnm Compare mode for CCSGnm GCCnm assign counter for GCCnm TBGnm 0: TMGn0 1: TMGn1 (a) Example: Interval timer (free run) Setting method interval timer:...
Page 457 16-bit Multi-Purpose Timer G (TMG) Chapter 13 (b) When the value 0000H is set in GCCnm INTCCGnm is activated when the value of the counter becomes 0001H. INTTMGn0/INTTMGn1 is activated when the value of the counter changes from FFFFH to 0000H. Note, however, that even if no data is set in GCCnm, INTCCGnm is activated immediately after the counter starts.
Page 458 Chapter 13 16-bit Multi-Purpose Timer G (TMG) PWM output (free run) Basic settings (m = 1 to 4): Value Remark CCSGn0 free run mode CCSGn5 Note SWFGnm enable TOGnm Compare mode for Note CCSGnm GCCnm assign counter for GCCnm TBGnm 0: TMGn0 1: TMGn1 Note...
Page 459 16-bit Multi-Purpose Timer G (TMG) Chapter 13 ENFG0 FFFFH FFFFH FFFFH Ma tch TM G n0 GCCn1 INTTGnCC1 INTTGnOV0 TOGn1 (ALVG1=1) TOGn1 (ALVG1=0) Figure 13-8 Timing of PWM operation (free run) Data N is set in GCCn1, counter TMGn0 is selected. (a) When 0000H is set in GCCnm (m = 1 to 4) When 0000H is set in GCCnm, TOGnm is tied to the inactive level.
Page 460 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (b) When FFFFH is set in GCCnm (m = 1 to 4) When FFFFH is set in GCCnm, TOGnm outputs the inactive level for one clock period immediately after each counter overflow (except the first overflow). The figure shows the state of TOGn1 when FFFFH is set in GCCn1, and TMGn0 is selected.
Page 461 16-bit Multi-Purpose Timer G (TMG) Chapter 13 (c) When GCCnm is rewritten during operation (m = 1 to 4) When GCCn1 is rewritten from 5555H to AAAAH, the operation shown below is performed. The figure below shows a case where TMGn0 is selected for GCCn1. ENFG0 FFFFH FFFFH...
Page 462: Match And Clear Mode
Chapter 13 16-bit Multi-Purpose Timer G (TMG) 13.8 Match and Clear Mode The match and clear mode is mainly used reduce the number of valid bits of the counters (TMGn0, TMGn1). Therefore the fixed assigned register GCCn0 (GCCn1) is used to compare its value with the counter TMGn0 (TMGn1).
Page 463 16-bit Multi-Purpose Timer G (TMG) Chapter 13 (b) Example: Capture where both edges of TIGnm are valid (match and clear) For the timing chart TMGn0 is selected as the counter corresponding to TOGn1, and 0FFFH is set in GCCn0. COUNTx 0000H 0001H 0FF F H 0000H TMGn0...
Page 464 Chapter 13 16-bit Multi-Purpose Timer G (TMG) Compare operation (match and clear) Basic settings (m = 1 to 4): Value Remark CCSGn0 match and clear mode CCSGn5 SWFGnm disable TOGnm Compare mode for CCSGnm GCCnm assign counter for GCCnm TBGnm 0: TMGn0 1: TMGn1 (a) Example: Interval timer (match and clear)
Page 465 16-bit Multi-Purpose Timer G (TMG) Chapter 13 ENFG0 0FFFH 0FFFH 0FFFH Ma tch TM G n0 GCCn1 INTTGnCC1 INTTGnCC0 Figure 13-13 Timing of compare operation (match and clear) In this example, the data N is set in GCCn1, and TMGn0 is selected. 0FFFH is set in GCCn0.
Page 466 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (f) When GCCnm (m = 1 to 4) is rewritten during operation (match and clear) When the value of GCCn1 is changed from 0555H to 0AAAH, the operation described below is performed. TMGn0 is selected as the counter, and 0FFFH is set in GCCn0. ENFG0 Ma tch Ma tch...
Page 467 16-bit Multi-Purpose Timer G (TMG) Chapter 13 Setting Method: An usable compare register is one of GCCn1 to GCCn4, and the corresponding counters TMGn0 or TMGn1 must be selected with the TBGnm bit (m = 1 to 4). Select a count clock cycle with the CSE12 to CSE10 (TMGn1) bits or CSE02 to CSE00 (TMGn0) bits.
Page 468 Chapter 13 16-bit Multi-Purpose Timer G (TMG) Example where the data N is set, and the counter TMGn0 is selected. 0FFFH is set in GCCn0 and N < 0FFFH. ENFG0 0FFFH 0FFFH 0FFFH Ma tch TM G n0 GCCn1 INTTGnCC1 INTTGnCC0 TOGn1(ALVG1=1) TOGn1(ALVG1=0)
Page 469 16-bit Multi-Purpose Timer G (TMG) Chapter 13 (b) When 0000H is set in GCCnm (match and clear) When 0000H is set in GCCnm, TOGnm is tied to the inactive level. The figure below shows the state of TOGn1 when 0000H is set in GCCn1, and TMGn0 is selected.
Page 470 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (c) When the same value as set in GCCn0 or GCCn5 is set in GCCnm (match and clear) When the same value as set in GCCn0 (GCCn5) is set in GCCnm, TOGnm outputs the inactive level for only one clock period immediately after each match and clear event (excluding the first match and clear event).
Page 471 16-bit Multi-Purpose Timer G (TMG) Chapter 13 (d) When a value exceeding the value set in GCCn0 or GCCn5 is set in GCCnm (match and clear) When a value exceeding the value set in GCCn0 (GCCn5) is set in GCCnm, TOGnm starts and continues outputting the active level immediately after the first match and clear event (until count operation stops.) The figure shows the state of TOGn1 when 0FFFH is set in GCCn0, 1FFFH is...
Page 472 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (e) When GCCnm is rewritten during operation (match and clear) When GCCn1 is rewritten from 0555H to 0AAAH, the operation shown below is performed. The figure below shows a case where 0FFFH is set in GCCn0, and TMGn0 is selected for GCCn1.
Page 473: Edge Noise Elimination
16-bit Multi-Purpose Timer G (TMG) Chapter 13 13.9 Edge Noise Elimination The edge detection circuit has a noise elimination function. This function regards: • a pulse not wider than 1 count clock period as a noise, and does not detect it as an edge. •...
Page 474: Precautions Timer Gn
Chapter 13 16-bit Multi-Purpose Timer G (TMG) 13.10 Precautions Timer Gn When POWERn bit of TMGMHn register is set The rewriting of the CSEn2 to CSEn0 bits of TMGMHn register is prohibited. These bits set the prescaler for the Timer Gn counter. The rewriting of the CCSGny bits (y = 0 to 5) is prohibited.
Page 475 16-bit Multi-Purpose Timer G (TMG) Chapter 13 If only one overflow is necessary, the CCFGny bits (y = 0 to 5) can be used for overflow detection. Only the overflow of the TMGn0 or TMGn1counter clears the CCFGny bit (TMGSTn register). The software-based clearing via CLRGn0 or CLRGn1 bit (TMGMLn register) doesn’t affect these bits.
Page 476 Chapter 13 16-bit Multi-Purpose Timer G (TMG) Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 477: Chapter 14 Watch Timer (Wt)
Chapter 14 Watch Timer (WT) The Watch Timer (WT) generates interrupts at regular time intervals. These interrupts are generally used as ticks for updating the internal daytime and calendar. The Watch Timer includes two identical counters. Throughout this chapter, the counters are identified as WTn, where n = 0 to 1.
Page 478 Chapter 14 Watch Timer (WT) Features summary Special features of the Watch Timer are: • Periodic interrupts (clock ticks) generated by two down-counters • Two reload registers, one for each counter • Choice of oscillators to reduce power consumption in stand-by mode •...
Page 479: Description
Watch Timer (WT) Chapter 14 14.1.1 Description The following figure shows the structure of the Watch Timer and its connection to the Watch Calibration Timer. Internal bus Watch WT0R WT1R Timer WT0CNT1 WT0CNT0 Reload buffer WT1CNT1 WT1CNT0 Reload buffer Reload Reload 16-bit down-counter 16-bit down-counter...
Page 480: Principle Of Operation
Chapter 14 Watch Timer (WT) 14.1.2 Principle of operation In order to generate an interrupt every one or two seconds, WTCLK is usually set to a frequency around 30 KHz. Then, a load value around 2 will yield a running time of about 1 s. Operation control of WT0 The source and frequency of WTCLK are specified in the Clock Generator register TCC.
Page 481 Watch Timer (WT) Chapter 14 Operation of WCT The third counter WCT is used for clock correction. This counter is connected to PCLK1 (8 MHz) or directly to the 4 MHz main oscillator. It is used to measure the time between two INTWT0UV requests. For this measurement, WCT is configured as a capture timer.
Page 482: Watch Timer Registers
Chapter 14 Watch Timer (WT) 14.2 Watch Timer Registers The Watch Timer counters WT0 and WT1 are controlled and operated by means of the following registers: Table 14-2 WTn registers overview Register name Shortcut Address Watch timer synchronized read register WTnCNT0 <base>...
Page 483: Preliminary User's Manual U17566Ee1V2Um00
Watch Timer (WT) Chapter 14 WTnCNT0 - WTn synchronized counter register The WTnCNT0 register is the synchronized register that can be used to read the present value of the 16-bit counter. “Synchronized” means that the read access via the internal bus is synchronized with the counter clock.
Page 484 Chapter 14 Watch Timer (WT) Reading the counter value via WTnCNT1 instead of WTnCNT0 is only reasonable when the CPU clock is remarkably higher than WTCLK and the overhead of multiple reading WTnCNT1 is justifiable. WTnR - WTn reload register The WTnR register is a dedicated register for setting the reload value of the corresponding counter.
Page 485: Watch Timer Operation
Watch Timer (WT) Chapter 14 14.3 Watch Timer Operation This section describes the operation of the Watch Timer counters in detail. 14.3.1 Timing of steady operation The contents of the reload registers WTnR can be changed at any time, provided the corresponding counter is enabled. The contents is then copied to the reload buffer.
Page 486: Watch Timer Start-Up
Chapter 14 Watch Timer (WT) 14.3.2 Watch Timer start-up The first interval after starting WT0 and WT1 until their first underflow takes at least four additional input clock cycles. At this point in time, the values of the counter registers WTnCNT are not correct. After the first automatic reload of the WTnR value, the counter registers WTnCNT hold the correct number of clock cycles since the last underflow.
Page 487 Watch Timer (WT) Chapter 14 As a consequence, register WT1CNT does not show the correct number of INTWT0UV events after WT1R > 0, but a value of four less: – 1 INTWT0UV cycle 2 –> 3 taken for the cycle WT1R is written –...
Page 488: Watch Calibration Timer Registers
Chapter 14 Watch Timer (WT) 14.4 Watch Calibration Timer Registers The Watch Calibration Timer is controlled by means of the following registers: Table 14-5 WCT registers overview Register name Shortcut Address WCT timer / counter read register TM00 <base> WCT capture / compare register CR000 <base>...
Page 489 Watch Timer (WT) Chapter 14 TMC00 - WCT mode control register The 8-bit TMC00 register controls the operation of the WCT. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 6 Initial Value . This register is cleared by any reset. TMC003 TMC002 OVF00...
Page 490 Chapter 14 Watch Timer (WT) PRM00 - WCT prescaler mode register The 8-bit PRM00 register is used to select the “valid edge” of INTWT0UV for interval measurements. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 7 Initial Value .
Page 491 Watch Timer (WT) Chapter 14 CRC00 - WCT capture / compare control register The 8-bit CRC00 register controls the operation of the capture/compare register CR000. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 8 Initial Value .
Page 492 Chapter 14 Watch Timer (WT) CR000 - WCT capture / compare register 1 The 16-bit CR000 register can be used as a capture register or as a compare register. Whether it is used as a capture register or compare register is specified in bit CRC00.CRC000.
Page 493: Watch Calibration Timer Operation
Watch Timer (WT) Chapter 14 14.5 Watch Calibration Timer Operation The Watch Calibration Timer WCT is used to measure the time between two successive occurrences of the Watch Timer WT0 underflow interrupt INTWT0UV. The WCT is supplied with the stable clock WCTCLK: •...
Page 494: Intwt0Uv Interval Measurement With Free-Running Counter
Chapter 14 Watch Timer (WT) 14.5.1 INTWT0UV interval measurement with free-running counter When the timer is used as a free-running counter (see register TMC00) and it detects the valid edge of INTWT0UV, it • copies the present counter value of register TM00 to CR000, •...
Page 495: Intwt0Uv Interval Measurement By Restarting The Counter
Watch Timer (WT) Chapter 14 14.5.2 INTWT0UV interval measurement by restarting the counter When the timer is in restart mode (see register TMC00) and it detects the valid edge of INTWT0UV, it • copies the present counter value of register TM00 to CR000, •...
Page 496 Chapter 14 Watch Timer (WT) Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 497: Chapter 15 Watchdog Timer (Wdt)
Chapter 15 Watchdog Timer (WDT) The Watchdog Timer is used to escape from a system deadlock or program runaway. If it is not restarted within a certain time, the Watchdog Timer flows over and interrupts or even resets the microcontroller. 15.1 Overview The Watchdog Timer contains an up-counter that is driven by the Watchdog Timer clock WDTCLK.
Page 498: Description
Chapter 15 Watchdog Timer (WDT) 15.1.1 Description The following figure shows a simplified block diagram. Internal bus SYSRES reset reset SYSRESWDT WDCS WDCS2 WDCS1 WDCS0 WDTMODE WDTM SYSRESWDT clear / WDTCLK WDTCLK Counter/Timer / WDTCLK / WDTCLK / WDTCLK Output NMIWDT overflow control...
Page 499: Watchdog Timer Clock
Watchdog Timer (WDT) Chapter 15 Watchdog Timer mode 1 (generate reset request RESWDT) If WDTM.WDTMODE is 1, the Watchdog Timer is in reset-request mode. Setting bit WDTM.RUN to 1 starts the counter. Without intervention, the timer will now run until the specified time has elapsed and then generate the internal RESWDT signal.
Page 500: Reset Behavior
Chapter 15 Watchdog Timer (WDT) 15.1.4 Reset behavior The reset of the Watchdog Timer is controlled by the two reset inputs SYSRES and SYSRESWDT. The respective signals are generated by the Reset module. Every reset sets the WDCS register to the longest possible running time. SYSRESWDT The watchdog reset SYSRESWDT is used to initialize the Watchdog Timer.
Page 501: Watchdog Timer Registers
Watchdog Timer (WDT) Chapter 15 15.2 Watchdog Timer Registers The Watchdog Timer is controlled by means of the following registers: Table 15-1 Watchdog Timer registers overview Register name Shortcut Address Watchdog Timer clock selection register WDCS <base> Watchdog Timer command protection register WCMD <base>...
Page 502 Chapter 15 Watchdog Timer (WDT) WDCS - WDT clock selection register The 8-bit WDCS register is used to specify the running time of the Watchdog Timer. Access This register can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “WCMD - WDT command protection register“...
Page 503 Watchdog Timer (WDT) Chapter 15 The running time depends on the frequency of the chosen clock. The following table shows two examples for 4 MHz and 32 KHz. Table 15-4 Running time examples Time until overflow WDCS2 WDCS1 WDCS0 Calculation = 4 MHz (main = 32 KHz (sub WDTCLK...
Page 504 Chapter 15 Watchdog Timer (WDT) WDTM - WDT mode register This register sets the operating mode of the Watchdog Timer and enables or disables counting. When the Watchdog Timer is running and shall not overflow, it is necessary to write to WDTM before the specified running time has elapsed. Access This register can be read/written in 8-bit units.
Page 505 Watchdog Timer (WDT) Chapter 15 WCMD - WDT command protection register The 8-bit WCMD register is write-only. It is used to protect the WDTM and WDCS registers from unintended writing. Access This register can be written in 8-bit units. Address <base>...
Page 506 Chapter 15 Watchdog Timer (WDT) WPHS - WDT command status register The WPHS register monitors the success of a write instruction to the WDTM and WDCS registers. If the write operation to WDTM or WDCS failed because WCMD was not written immediately before writing to WDTM or WDCS, the WPRERR flag is set.
Page 507: Chapter 16 Asynchronous Serial Interface (Uarta)
Chapter 16 Asynchronous Serial Interface (UARTA) The V850E/Dx3 microcontrollers have following instances of the universal Asynchronous Serial Interface UARTA: UARTA All devices Instances Names UARTA0 to UARTA1 Throughout this chapter, the individual instances of UARTA are identified by “n”, for example, UARTAn, or UAnCTL0 for the UARTAn control register 0.
Page 508: Configuration
Chapter 16 Asynchronous Serial Interface (UARTA) • 13 to 20 bits selectable for the SBF (Sync Break Field) in the LIN (Local Interconnect Network) communication format – Recognition of 11 bits or more possible for SBF reception in LIN communication format –...
Page 509 Asynchronous Serial Interface (UARTA) Chapter 16 UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation. UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register used to select the input clock for the UARTAn.
Page 510: Uarta Registers
Chapter 16 Asynchronous Serial Interface (UARTA) 16.3 UARTA Registers The asynchroneous serial interfaces UARTAn are controlled and operated by means of the following registers: Table 16-1 UARTAn registers overview Register name Shortcut Address UARTAn control register 0 UAnCTL0 <base> UARTAn control register 1 UAnCTL1 <base>...
Page 511 Asynchronous Serial Interface (UARTA) Chapter 16 UAnCTL0 - UARTAn control register 0 The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation. Access This register can be read/written in 8-bit or 1-bit units. Address <base> Initial Value .
Page 512 Chapter 16 Asynchronous Serial Interface (UARTA) Table 16-3 UAnCTL0 register contents (2/2) Bit position Bit name Function 3, 2 UAnPS[1:0] Parity selection Parity selection during UAnPS1 UAnPS0 transmission reception No parity output Reception with no parity 0 parity output Reception with 0 parity Odd parity output Odd parity check Even parity output Even parity check...
Page 513 Asynchronous Serial Interface (UARTA) Chapter 16 UAnOPT0 - UARTAn option control register 0 The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register. Access This register can be read/written in 8-bit or 1-bit units. Address <base>...
Page 514 Chapter 16 Asynchronous Serial Interface (UARTA) Table 16-4 UAnOPT0 register contents Bit position Bit name Function UAnSRF SBF reception flag: 0: When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnRXE bit = 0 are set. Also upon normal end of SBF reception. 1: During SBF reception •...
Page 515 Asynchronous Serial Interface (UARTA) Chapter 16 UAnSTR - UARTAn status register The UAnSTR register is an 8-bit register that displays the UARTAn transfer status and reception error contents. Access This register can be read or written in 8-bit or 1-bit units. Address <base>...
Page 516 Chapter 16 Asynchronous Serial Interface (UARTA) Table 16-5 UAnSTR register contents (2/2) Bit position Bit name Function UAnPE Parity error flag: 0: – When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set. – When 0 has been written 1: When parity of data and parity bit do not match during reception.
Page 517 Asynchronous Serial Interface (UARTA) Chapter 16 UAnRX - UARTAn receive data register The UAnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UAnRX register upon completion of reception of 1 byte of data.
Page 518: Interrupt Request Signals
Chapter 16 Asynchronous Serial Interface (UARTA) 16.4 Interrupt Request Signals The following three interrupt request signals are generated from UARTAn: • Reception complete interrupt request signal (INTUAnR) • Receive error interrupt request signal (INTUAnRE) • Transmission enable interrupt request signal (INTUAnT) Reception complete interrupt request signal (INTUAnR) A reception complete interrupt request signal is output when data is shifted into the receive shift register and transferred to the UAnRX register in the reception...
Page 519: Operation
Asynchronous Serial Interface (UARTA) Chapter 16 16.5 Operation 16.5.1 Data format Full-duplex serial data reception and transmission is performed. As shown in the figures below, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of MSB/LSB-first transfer are performed using the UAnCTL0 register.
Page 520 Chapter 16 Asynchronous Serial Interface (UARTA) (c) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H, TXDAn inversion 1 data frame Start Parity Stop (d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H 1 data frame Start Parity...
Page 521: Sbf Transmission/Reception Format
Asynchronous Serial Interface (UARTA) Chapter 16 16.5.2 SBF transmission/reception format The UARTA has an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. About LIN LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial co mmunication protocol intended to aid the cost reduction of an automotive network.
Page 522 Chapter 16 Asynchronous Serial Interface (UARTA) A transmission enable interrupt request signal (INTUAnT) is output at the start of each transmission. The INTUAnT signal is also output at the start of each SBF transmission. Wake-up Synch Check signal break Synch DATA DATA Ident...
Page 523: Sbf Transmission
Asynchronous Serial Interface (UARTA) Chapter 16 16.5.3 SBF transmission When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnTXE bit = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UAnOPT0.UAnSTT bit). Thereafter, a low level the width of bits 13 to 20 specified by the UAnOPT0.UAnSBL2 to UAnOPT0.UAnSBL0 bits is output.
Page 524 Chapter 16 Asynchronous Serial Interface (UARTA) (a) Normal SBF reception (detection of stop bit in more than 10.5 bits) 11.5 UAnSRF INTUAnR interrupt (b) SBF reception error (detection of stop bit in 10.5 or fewer bits) 10.5 UA0SRF INTUAnR interrupt Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com...
Page 525: Uart Transmission
Asynchronous Serial Interface (UARTA) Chapter 16 16.5.5 UART transmission A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started by writing transmit data to the UAnTX register.
Page 526: Continuous Transmission Procedure
Chapter 16 Asynchronous Serial Interface (UARTA) 16.5.6 Continuous transmission procedure UARTAn can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the shift operation. The transmit timing of the UARTAn transmit shift register can be judged from the transmission enable interrupt request signal (INTUAnT).
Page 527 Asynchronous Serial Interface (UARTA) Chapter 16 Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDAn UAnTX Data (1) Data (2) Data (3) Transmission Data (2) Data (1) shift register INTUAnT UAnTSF Figure 16-6 Continuous transmission operation timing —transmission start Stop UATTXD Parity...
Page 528: Uart Reception
Chapter 16 Asynchronous Serial Interface (UARTA) 16.5.7 UART reception The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine.
Page 529 Asynchronous Serial Interface (UARTA) Chapter 16 Caution Be sure to read the UAnRX register even when a reception error occurs. If the UAnRX register is not read, an overrun error occurs during reception of the next data, and reception errors continue occurring indefinitely. The operation during reception is performed assuming that there is only one stop bit.
Page 530: Reception Errors
Chapter 16 Asynchronous Serial Interface (UARTA) 16.5.8 Reception errors Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception result error flags are set in the UAnSTR register and a reception error interrupt request signal (INTUAnRE) is output when an error occurs.
Page 531 Asynchronous Serial Interface (UARTA) Chapter 16 Odd parity • During transmission Opposite to even parity, the number of bits whose value is “1” among the transmit data, including the parity bit, is controlled so that it is an odd number. The parity bit values are as follows. –...
Page 532: Receive Data Noise Filter
Chapter 16 Asynchronous Serial Interface (UARTA) 16.5.10 Receive data noise filter This filter samples the RXDAn pin using the base clock of the prescaler output. When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled as the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see Figure 16-10).
Page 533: Baud Rate Generator
Asynchronous Serial Interface (UARTA) Chapter 16 16.6 Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel.
Page 534: Baud Rate Generator Registers
Chapter 16 Asynchronous Serial Interface (UARTA) 16.6.2 Baud Rate Generator registers UAnCTL1 - UARTAn control register 1 The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock. Access This register can be read or written in 8-bit units. Address <base>...
Page 535 Asynchronous Serial Interface (UARTA) Chapter 16 UAnCTL2 - UARTAn control register 2 The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn. Access This register can be read or written in 8-bit units. Address <base>...
Page 536: Baud Rate Calculation
Chapter 16 Asynchronous Serial Interface (UARTA) 16.6.3 Baud rate calculation The baud rate is obtained by the following equation. UCLK Baud rate -------------- - [bps] × = Frequency of base clock selected by the UAnCTL1.UAnCKS[2:0] UCLK Value set using the UAnCTL2.UAnBRS[7:0] bits (k = 4, 5, 6, …, 255) 16.6.4 Baud rate error The baud rate error is obtained by the following equation.
Page 537: Baud Rate Setting Example
Asynchronous Serial Interface (UARTA) Chapter 16 16.6.5 Baud rate setting example Table 16-9 Baud rate generator setting data Target Effective UAnCTL1 UAnCTL2 Baud rate error baud rate baud rate [bps] [bps] Selector Divider Divider k 300.48 0.16 600.96 0.16 1,200 1,201.92 0.16 2,400...
Page 538 Chapter 16 Asynchronous Serial Interface (UARTA) Latch timing UARTn Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit transfer rate 1 data frame (11 × FL) Minimum Bit 0 Bit 1 Bit 7 Stop bit Start bit Parity bit allowable transfer rate...
Page 539 Asynchronous Serial Interface (UARTA) Chapter 16 Therefore, the minimum baud rate that can be received by the destination is as follows. – ⁄ ------------------ - × FLmax 11 BRmin Brate – 21k 2 Obtaining the allowable baud rate error for UARTAn and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following.
Page 540: Baud Rate During Continuous Transmission
Chapter 16 Asynchronous Serial Interface (UARTA) 16.6.7 Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result.
Page 541: Chapter 17 Clocked Serial Interface (Csib)
Chapter 17 Clocked Serial Interface (CSIB) The V850E/Dx3 microcontrollers have following instances of the clocked serial interface CSIB: µPD70F3427, µPD70F3426 µPD70F3423, µPD70(F)3422 CSIB µPD70F3425, µPD70F3424 µPD70(F)3421, µPD70(F)3420 Instances Names CSIB0 to CSIB2 CSIB0 to CSIB1 Throughout this chapter, the individual instances of clocked serial interface are identified by “n”, for example CSIBn, or CBnCTL0 for the control register 0 of...
Page 542: Configuration
Chapter 17 Clocked Serial Interface (CSIB) 17.2 Configuration The following shows the block diagram of CSIBn. Internal bus CBnCTL1 CBnCTL0 CBnCTL2 SPCLK1 (8 MHz) CBnSTR INTCBnT BRGn Controller INTCBnR INTCBnRE Note PCLK1 (8 MHz) PCLK2 (4 MHz) PCLK3 (2 MHz) Phase control PCLK4 (1 MHz) PCLK5 (500 KHz)
Page 543: Csib Control Registers
Clocked Serial Interface (CSIB) Chapter 17 17.3 CSIB Control Registers The clocked serial interfaces CSIBn are controlled and operated by means of the following registers: Table 17-1 CSIBn registers overview Register name Shortcut Address CSIBn control register 0 CBnCTL0 <base> CSIBn control register 1 CBnCTL1 <base>...
Page 544 Chapter 17 Clocked Serial Interface (CSIB) CBnCTL0 - CSIBn control register 0 CBnCTL0 is a register that controls the CSIBn serial transfer operation. Access This register can be read/written in 8-bit or 1-bit units. Address <base> Initial Value . This register is cleared by any reset. CBnPWR CBnTXE CBnRXE CBnDIR...
Page 545 Clocked Serial Interface (CSIB) Chapter 17 Table 17-3 CBnCTL0 register contents (2/2) Bit position Bit name Function CBnDIR Transfer direction mode specification (MSB/LSB): 0: MSB first transfer 1: LSB first transfer CBnTMS Transfer direction mode specification (MSB/LSB): 0: Single transfer mode 1: Continuous transfer mode CBnSCE Transfer direction mode specification (MSB/LSB):...
Page 546 Chapter 17 Clocked Serial Interface (CSIB) CBnCTL1 - CSIBn control register 1 CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation. Access This register can be read/written in 8-bit units. Address <base> + 1 Initial Value . This register is cleared by any reset. CBnCKP CBnDAP CBnCKS2 CBnCKS1 CBnCKS0 Caution The CBnCTL1 register can be rewritten only when the...
Page 547 Clocked Serial Interface (CSIB) Chapter 17 Table 17-5 Specification of data transmission/reception timing in relation to SCKBn Communication type CBnCKP CBnDAP SIBn/SOBN timing in relation to SCKBn Communication type 1 SCKBn (I/O) SOBn (output) SIBn capture Communication type 2 SCKBn (I/O) SOBn (output)
Page 548 Chapter 17 Clocked Serial Interface (CSIB) CBnCTL2 - CSIBn control register 2 CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits. Access This register can be read/written in 8-bit units. Address <base> + 2 Initial Value .
Page 549 Clocked Serial Interface (CSIB) Chapter 17 (a) Transfer data length change function The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits using the CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
Page 550 Chapter 17 Clocked Serial Interface (CSIB) CBnSTR - CSIBn status register CBnSTR is an 8-bit register that displays the CSIBn status. Access This register can be read/written in 8-bit or 1-bit units. Bit CBnTSF is read-only. Address <base> + 3 Initial Value .
Page 551 Clocked Serial Interface (CSIB) Chapter 17 CBnRX - CSIBn receive data register The CBnRX register is a 16-bit buffer register that holds receive data. Access This register can be read-only in 16-bit units. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnRXL register.
Page 552: Operation
Chapter 17 Clocked Serial Interface (CSIB) 17.4 Operation 17.4.1 Single transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.4 (2) CSIBn control register 1 (CBnCTL1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnTX write (55H) CBnRX read (AAH) SCKBn...
Page 553 Clocked Serial Interface (CSIB) Chapter 17 Note In single transmission or single transmission/reception mode, the INTCBnT signal is not generated. When communication is complete, the INTCBnR signal is generated. The processing of steps (3) and (4) can be set simultaneously. Caution In case the CSIB interface is operating in •...
Page 554: Single Transfer Mode (Master Mode, Reception Mode)
Chapter 17 Clocked Serial Interface (CSIB) 17.4.2 Single transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.4 (2) CSIBn control register 1 (CBnCTL1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnRX read (55H) CBnRX read (AAH) SCKBn...
Page 555: Continuous Mode (Master Mode, Transmission/Reception Mode)
Clocked Serial Interface (CSIB) Chapter 17 17.4.3 Continuous mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 3 (see 16.4 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnTX SCKBn SOBn...
Page 556: Continuous Mode (Master Mode, Reception Mode)
Chapter 17 Clocked Serial Interface (CSIB) (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of transmission/reception). To continue transfer, repeat steps (5) to (7) before (8). In transmission mode or transmission/reception mode, the communication is not started by reading the CBnRX register.
Page 557: Continuous Reception Mode (Error)
Clocked Serial Interface (CSIB) Chapter 17 (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of reception). To continue transfer, repeat steps (5) and (6) before (7). 17.4.5 Continuous reception mode (error) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (see 16.4 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits...
Page 558: Continuous Mode (Slave Mode, Transmission/Reception Mode)
Chapter 17 Clocked Serial Interface (CSIB) 17.4.6 Continuous mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (see 16.4 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CSnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnTX SCKBn SOBn...
Page 559 Clocked Serial Interface (CSIB) Chapter 17 Read the CBnRX register. (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of transmission/reception). To continue transfer, repeat steps (5) to (7) before (8). Note In order to start the entire data transfer the CBnTX register has to be written initially, as done in step (5) above.
Page 560: Continuous Mode (Slave Mode, Reception Mode)
Chapter 17 Clocked Serial Interface (CSIB) 17.4.7 Continuous mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.4 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) SCKBn SIBn INTCBnR...
Page 561: Clock Timing
Clocked Serial Interface (CSIB) Chapter 17 17.4.8 Clock timing SCKBn SIBn capture SOBn Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF Figure 17-4 (i) Communication type 1 (CBnCKP = 0, CBnDAP = 0) SCKBn SIBn capture SOBn Reg-R/W INTCBnT Note 1 interrupt...
Page 562 Chapter 17 Clocked Serial Interface (CSIB) SCKBn SIBn capture SOBn Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF Figure 17-6 (iii) Communication type 2 (CBnCKP = 0, CBnDAP = 1) SCKBn SIBn capture SOBn Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2...
Page 563: Output Pins
Clocked Serial Interface (CSIB) Chapter 17 17.5 Output Pins SCKBn pin When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows. CBnCKP CBnCKS2 CBnCKS1 CBnCKS0 SCKBn pin output Don’t care Don’t care Don’t care Fixed to high level High impedance Other than above...
Page 564: Operation Flow
Chapter 17 Clocked Serial Interface (CSIB) 17.6 Operation Flow Single transmission START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnT bit = 1? Data to be transferred next exists? CBnTSF bit = 1? (CBnSTR) CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting.
Page 565 Clocked Serial Interface (CSIB) Chapter 17 Single reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) CBnRX register dummy read (start reception) INTCBnR bit = 1? Last data? CBnRX register read CBnSCE bit = 0 (CBnCTL0) CBnRX register read CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting.
Page 566 Chapter 17 Clocked Serial Interface (CSIB) Single transmission/reception START Note 1 Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnR bit = 1? Transmission/reception Reception Transmission Read CBnRX register. Read CBnRX register. Transfer end? Transfer end? Transfer end? Note 2 Note 2 Note 2...
Page 567 Clocked Serial Interface (CSIB) Chapter 17 Continuous transmission START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnT bit = 1? Data to be transferred next exists? CBnTSF bit = 1? (CBnSTR) CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting.
Page 568 Chapter 17 Clocked Serial Interface (CSIB) Continuous reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) CBnRX register dummy read (start reception) INTCBnR bit = 1? CBnRX register read CBnOVE bit = 1? (CBnSTR) CBnRX register read Is data being received last data? CBnOVE bit clear (CBnSTR)
Page 569 Clocked Serial Interface (CSIB) Chapter 17 Continuous transmission/reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register. INTCBnT bit = 1? Is data being transferred last data? Write CBnTX register. INTCBnT bit = 1? CBnRX register read CBnOVE bit = 0? (CBnSTR) CBnOVE bit clear (CBnSTR)
Page 570: Baud Rate Generator
Chapter 17 Clocked Serial Interface (CSIB) 17.7 Baud Rate Generator 17.7.1 Overview Each CSIBSn interface is equipped with a dedicated baud rate generator. Selector 8-bit timer counter SPCLK1 (1, 1/2, 1/4, 1/8) Match detector BRGnOUT BGnCS1, BGnCS0 PRSCMn Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 571: Baud Rate Generator Registers
Clocked Serial Interface (CSIB) Chapter 17 17.7.2 Baud Rate Generator registers The Baud Rate Generators BRGn are controlled and operated by means of the following registers: Table 17-9 BRGn registers overview Register name Shortcut Address BRGn prescaler mode register PRSMn <BRG_base>...
Page 572: Baud Rate Calculation
Chapter 17 Clocked Serial Interface (CSIB) PRSCMn - Prescaler compare registers The PRSCMn registers are 8-bit compare registers. Access This register can be read/written in 8-bit units. Address <BRG_base> + 1 Initial Value . This register is cleared by any reset. PRSCMn7 PRSCMn6 PRSCMn5...
Page 573: Chapter 18 I 2 C Bus (Iic)
Chapter 18 I C Bus (IIC) The V850E/Dx3 microcontrollers have following instances of the I C Bus interface IIC: All devices Instances Names IIC0 to IIC1 Throughout this chapter, the individual instances of C Bus interface are identified by “n”, for example IICn, or IICCn for the IICn control register.
Page 574: I2C Pin Configuration
Chapter 18 C Bus (IIC) 18.2 I C Pin Configuration The I C function requires to define the pins SCLn and SDAn as input and open drain output pins simultaneously. In the following the pin configuration registers are listed to be set up properly for I •...
Page 575: Configuration
C Bus (IIC) Chapter 18 18.3 Configuration The block diagram of the I C0n is shown below. Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn LRELn WRELnSPIEn WTIMn ACKEn STTn SPTn Slave address Clear Start condition...
Page 576 Chapter 18 C Bus (IIC) A serial bus configuration example is shown below. Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC Address 4 Slave IC Address N Figure 18-2 Serial bus configuration example using I...
Page 577 C Bus (IIC) Chapter 18 Prescaler This selects the sampling clock to be used. Serial clock counter This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received.
Page 578: Iic Registers
Chapter 18 C Bus (IIC) 18.4 IIC Registers The I C serial interfaces IICn are controlled and operated by means of the following registers: Table 18-2 IICn registers overview Register name Shortcut Address IICn shift register IICn <base> IICn control register IICCn <base>...
Page 579 C Bus (IIC) Chapter 18 IICCn - IICn control registers The IICCn registers enable/stop I Cn operations, set the wait timing, and set other I Cn operations. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 2 Initial Value .
Page 580 Chapter 18 C Bus (IIC) SPIEn Enable/disable generation of interrupt request when stop condition is detected Disabled Enabled Note 2 Condition for clearing (SPIEn = 0) Condition for setting (SPIEn = 1) • Cleared by instruction • Set by instruction •...
Page 581 C Bus (IIC) Chapter 18 STTn Start condition trigger Start condition is not generated. When bus is released (in STOP mode): A start condition is generated (for starting as master). The SDAn line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, the SCLn line is changed to low level.
Page 582 Chapter 18 C Bus (IIC) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDAn line goes to low level, either set the SCLn line to high level or wait until it goes to high level.
Page 583 C Bus (IIC) Chapter 18 IICSn - IICn status registers The IICSn registers indicate the status of the I Cn bus. Access This register can only be read in 8-bit or 1-bit units. Address <base> + 6 Initial Value . This register is cleared by any reset. MSTSn ALDn EXCn...
Page 584 Chapter 18 C Bus (IIC) COIn Matching address detection Addresses do not match. Addresses match. Condition for clearing (COIn = 0) Condition for setting (COIn = 1) • When a start condition is detected • When the received address matches the local address (SVAn register) (set at the rising edge of •...
Page 585 C Bus (IIC) Chapter 18 STDn Start condition detection Start condition was not detected. Start condition was detected. This indicates that the address transfer period is in effect Condition for clearing (STDn = 0) Condition for setting (STDn = 1) •...
Page 586 Chapter 18 C Bus (IIC) IICFn - IICn flag registers The registers set the I Cn operation mode and indicate the I C bus status. Access This register can be read/written in 8-bit or 1-bit units. STCFn and IICBSYn bits are read-only. Address <base>...
Page 587 C Bus (IIC) Chapter 18 IICRSVn Communication reservation function disable bit Communication reservation enabled Communication reservation disabled Condition for clearing (IICRSVn = 0) Condition for setting (IICRSVn = 1) • Clearing by instruction • Setting by instruction • After reset Note Bits 6 and 7 are read-only bits.
Page 588 Chapter 18 C Bus (IIC) IICCLn - IICn clock select registers The IICCLn registers set the transfer clock for the I Cn bus. The SMCn, CLn1, and CLn0 bits are set by the combination of the IICXn.CLXn bit and the OCKSTHn, OCKSn[1:0] bits of the OCKSn register (see “Transfer rate setting“...
Page 589 C Bus (IIC) Chapter 18 IICXn - IICn function expansion registers The IICXn registers provide additional transfer data rate configuration in fast- speed mode. Setting of the IICXn.CLXn is performed in combination with the IICCLn.SMCn, IICCLn.CLn[1:0], OCKSn.OCKSTHn and OCKSn.OCKSn[1:0] (refer to “Transfer rate setting“ on page 590) Access This register can be read/written in 8-bit or 1-bit units.
Page 590 Chapter 18 C Bus (IIC) Transfer rate setting The nominal transfer rate of the I C interface is determined by the following means: • the root clock source for the I C clock IICLK can be chosen as – main oscillator (4 MHz): ICC.IICSEL1 = 0 –...
Page 591 C Bus (IIC) Chapter 18 Clock Stretching Heavy capacitive load and the dimension of the external pull-up resistor on the C bus pins may yield extended rise times of the rising edge of SCLn and SDAn. Since the controller senses the level of the I C bus signals it recognizes such situation and takes countermeasures by stretching the clock SCLn in order to ensure proper high level time t...
Page 592 Chapter 18 C Bus (IIC) IICn - IICn shift registers The IICn registers are used for serial transmission/reception (shift operations) synchronized with the serial clock. A wait state is released by writing the IICn register during the wait period, and data transfer is started.
Page 593: I 2 C Bus Pin Functions
C Bus (IIC) Chapter 18 18.5 I C Bus Pin Functions The serial clock pin (SCLn) and serial data bus pin (SDAn) are configured as follows. SCLn This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices.
Page 594: Start Condition
Chapter 18 C Bus (IIC) condition”, “data”, and “stop condition” output via the I C bus’s serial data bus is shown below. 1 to 7 1 to 7 1 to 7 SCLn SDAn Start Address Data Data Stop condition condition Figure 18-5 C bus serial data transfer timing The master device outputs the start condition, slave address, and stop...
Page 595: Addresses
C Bus (IIC) Chapter 18 18.6.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
Page 596: Transfer Direction Specification
Chapter 18 C Bus (IIC) 18.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 597 C Bus (IIC) Chapter 18 the ACKEn bit to 0 will prevent the master device from starting transmission of the subsequent data. Similarly, when the master device is receiving (when TRCn bit = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, clearing the ACKEn bit to 0 will prevent the ACK signal from being returned.
Page 598: Stop Condition
Chapter 18 C Bus (IIC) 18.6.5 Stop condition When the SCLn pin is high level, changing the SDAn pin from low level to high level generates a stop condition. A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed.
Page 599: Wait Signal (Wait)
C Bus (IIC) Chapter 18 18.6.6 Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLn pin to low level notifies the communication partner of the wait status.
Page 600 Chapter 18 C Bus (IIC) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn bit = 1) Master and slave both wait Master (Tx) after output of ninth clock. IICn data write (cancel wait) IICn SCLn Slave (Rx)
Page 601: I 2 C Interrupt Request Signals (Intiicn)
C Bus (IIC) Chapter 18 18.7 I C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing. 18.7.1 Master device operation Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1>...
Page 602 Chapter 18 C Bus (IIC) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 STTn bit = 1 SPTn bit = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1...
Page 603 C Bus (IIC) Chapter 18 Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 ▲1 ▲2 ▲3 ▲4 Δ5 ▲1: IICSn register = 1010X110B...
Page 604: Slave Device Operation
Chapter 18 C Bus (IIC) 18.7.2 Slave device operation Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ▲1 ▲2 ▲3 Δ4 ▲1: IICSn register = 0001X110B ▲2: IICSn register = 0001X000B ▲3: IICSn register = 0001X000B Δ...
Page 605 C Bus (IIC) Chapter 18 Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1 ▲2 ▲3...
Page 606 Chapter 18 C Bus (IIC) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1 ▲2 ▲3...
Page 607 C Bus (IIC) Chapter 18 Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1 ▲2...
Page 608: Slave Device Operation (When Receiving Extension Code)
Chapter 18 C Bus (IIC) 18.7.3 Slave device operation (when receiving extension code) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ▲1 ▲2 ▲3 Δ4 ▲1: IICSn register = 0010X010B ▲2: IICSn register = 0010X000B...
Page 609 C Bus (IIC) Chapter 18 Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1 ▲2 ▲3...
Page 610 Chapter 18 C Bus (IIC) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1 ▲2 ▲3...
Page 611 C Bus (IIC) Chapter 18 Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1 ▲2...
Page 612: Operation Without Communication
Chapter 18 C Bus (IIC) 18.7.4 Operation without communication Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 Δ1 Δ 1: IICSn register = 00000001B Remarks 1. Δ: Generated only when SPIEn bit = 1 2.
Page 613 C Bus (IIC) Chapter 18 When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ▲1 ▲2 ▲3 Δ4 ▲1: IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing) ▲2: IICSn register = 0010X000B ▲3: IICSn register = 0010X000B Δ...
Page 614: Operation When Arbitration Loss Occurs
Chapter 18 C Bus (IIC) 18.7.6 Operation when arbitration loss occurs When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0 D7 to D0 ▲1 Δ2 ▲1: IICSn register = 01000110B (Example: When ALDn bit is read during interrupt servicing) Δ...
Page 615 C Bus (IIC) Chapter 18 When arbitration loss occurs during data transfer <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ▲1 ▲2 Δ3 ▲1: IICSn register = 10001110B ▲2: IICSn register = 01000000B (Example: When ALDn bit is read during interrupt servicing) Δ...
Page 616 Chapter 18 C Bus (IIC) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 ▲1 ▲2 Δ3 ▲1: IICSn register = 1000X110B ▲2: IICSn register = 01000110B (Example: When ALDn bit is read during interrupt servicing) Δ...
Page 617 C Bus (IIC) Chapter 18 When arbitration loss occurs due to low level of SDAn pin when attempting to generate a restart condition When WTIMn bit = 1 STTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 ▲1 ▲2...
Page 618 Chapter 18 C Bus (IIC) When arbitration loss occurs due to low level of SDAn pin when attempting to generate a stop condition When WTIMn bit = 1 SPTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 ▲1 ▲2...
Page 619: Interrupt Request Signal (Intiicn)
C Bus (IIC) Chapter 18 18.8 Interrupt Request Signal (INTIICn) The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below. Table 18-4 INTIICn generation timing and wait control WTIMn Bit During Slave Device Operation During Master Device Operation...
Page 620: Address Match Detection Method
Chapter 18 C Bus (IIC) Wait cancellation method The four wait cancellation methods are as follows. • By setting the IICCn.WRELn bit to 1 • By writing to the IICn register • Note By start condition setting (IICCn.STTn bit = 1) •...
Page 621: Extension Code
C Bus (IIC) Chapter 18 18.11 Extension Code • When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (IICSn.EXCn bit) is set for extension code reception and an interrupt request signal (INTIICn) is issued at the falling edge of the eighth clock.
Page 622: Arbitration
Chapter 18 C Bus (IIC) 18.12 Arbitration When several master devices simultaneously output a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs.
Page 623: Wakeup Function
C Bus (IIC) Chapter 18 Table 18-6 Status during arbitration and interrupt request signal generation timing Status During Arbitration Interrupt Request Generation Timing Transmitting address transmission At falling edge of eighth or ninth clock following byte Note 1 transfer Read/write data after address transmission Transmitting extension code Read/write data after extension code transmission Transmitting data...
Page 624: Cautions
Chapter 18 C Bus (IIC) 18.14 Cautions When IICFn.STCENn bit = 0 Immediately after the I C0n operation is enabled, the bus communication status (IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication.
Page 625 C Bus (IIC) Chapter 18 START ← ××H IICCLn Select transfer clock ← ××H IICCn IICEn = SPIEn = WTIMn = SPTn = 1 INTIICn = 1? Yes (stop condition detection) STTn = 1 Wait time is secured by Wait software (see Table 17-6) Communication reservation MSTSn = 1?
Page 626: Master Operation 2
Chapter 18 C Bus (IIC) 18.15.2 Master operation 2 The following shows the flowchart for master communication when the communication reservation function is disabled (IICRSVn bit = 1) and the master operation is started without detecting a stop condition (STCENn bit = 1). START ←...
Page 627: Slave Operation
C Bus (IIC) Chapter 18 18.15.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIICn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary.
Page 628 Chapter 18 C Bus (IIC) Communication direction flag This flag indicates the direction of communication and is the same as the value of IICSn.TRCn bit. The following shows the operation of the main processing block during slave operation. Start I C0n and wait for the communication enabled status.
Page 629 C Bus (IIC) Chapter 18 START IICCLn ← XXH Selection of transfer flag IICFn ← XXH IICFn register setting IICCn ← XXH IICEn = 1 Communication mode? ACKEn = WTIMn = 1 Communication direction flag = 1? WRELn = 1 WTIMn = 1 Communication mode? Data processing...
Page 630 Chapter 18 C Bus (IIC) During an INTIICn interrupt, the status is confirmed and the following steps are executed. <1> When a stop condition is detected, communication is terminated. <2> When a start condition is detected, the address is confirmed. If the address does not match, communication is terminated.
Page 631: Timing Of Data Communication
C Bus (IIC) Chapter 18 18.16 Timing of Data Communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICSn.TRCn bit, which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 632 Chapter 18 C Bus (IIC) Processing by master device ← ← IICn IICn address IICn data ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transmit Transfer lines SCL0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0n Start condition Processing by slave device ←...
Page 633 C Bus (IIC) Chapter 18 Processing by master device ← ← IICn data IICn data IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transmit Transfer lines SCL0n SDA0n Processing by slave device ← ← IICn IICn FFH Note IICn FFH Note...
Page 634 Chapter 18 C Bus (IIC) Processing by master device ← ← IICn IICn data IICn address ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn Transmit Transfer lines SCL0n SDA0n Stop Start condition condition Processing by slave device ←...
Page 635 C Bus (IIC) Chapter 18 Processing by master device ← ← IICn IICn address IICn FFH Note ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn Note INTIICn TRCn Transfer lines SCL0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0n Start condition Processing by slave device ←...
Page 636 Chapter 18 C Bus (IIC) Processing by master device IICn ← FFH Note IICn ← FFH Note IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn Note Note WRELn INTIICn TRCn Receive Transfer lines SCL0n SDA0n Processing by slave device IICn ←...
Page 637 C Bus (IIC) Chapter 18 Processing by master device ← ← IICn IICn FFH Note IICn address ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn Note WRELn INTIICn (When SPIEn = 1) TRCn Transfer lines SCL0n D7D6D5D4D3D2D1D0AD5 SDA0n N- ACK Stop Start condition...
Page 638 Chapter 18 C Bus (IIC) Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 639: Chapter 19 Can Controller (Can)
Chapter 19 CAN Controller (CAN) These microcontrollers feature an on-chip n-channel CAN (Controller Area Network) controller that complies with the CAN protocol as standardized in ISO 11898. The V850E/Dx3 microcontrollers have following number of channels of the CAN controller: All devices Instances...
Page 640: Features
Chapter 19 CAN Controller (CAN) 19.1 Features • Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test) • Standard frame and extended frame transmission/reception enabled • Transfer rate: 1 Mbps max. (if CAN clock input ≥ 8 MHz) •...
Page 641: Overview Of Functions
CAN Controller (CAN) Chapter 19 19.1.1 Overview of functions Table 19-1 presents an overview of the CAN Controller functions. Table 19-1 Overview of functions Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Maximum 1 Mbps (CAN clock input ≥ 8 MHz) Baud rate Data storage Storing messages in the CAN RAM...
Page 642: Configuration
19.1.2 Configuration The CAN Controller is composed of the following four blocks. • NPB interface This functional block provides an NPB (NEC Peripheral I/O Bus) interface and means of transmitting and receiving signals between the CAN module and the host CPU.
Page 643: Can Protocol
CAN Controller (CAN) Chapter 19 19.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer.
Page 644: Frame Types
Chapter 19 CAN Controller (CAN) 19.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 19-2 Frame types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame...
Page 645 CAN Controller (CAN) Chapter 19 Remote frame A remote frame is composed of six fields. Remote frame <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Figure 19-4 Remote frame Note...
Page 646 Chapter 19 CAN Controller (CAN) <2> Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Arbitration field (Control field) Identifier (r1) ID28 · · · · · · · · · · · · · · · · · · · · · · · · · · ID18 (11 bits) (1 bit) (1 bit)
Page 647 CAN Controller (CAN) Chapter 19 Table 19-3 RTR frame settings Frame Type RTR Bit Data frame 0 (D) Remote frame 1 (R) Table 19-4 Frame format setting (IDE bit) and number of identifier (ID) bits Frame Format SRR Bit IDE Bit Number of Bits Standard format mode None...
Page 648 Chapter 19 CAN Controller (CAN) <4> Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. (Control field) Data field (CRC field) Data 0 Data 7 (8 bits) (8 bits)
Page 649 CAN Controller (CAN) Chapter 19 <6> ACK field The ACK field is used to acknowledge normal reception. (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit) Figure 19-11 ACK field Note D: Dominant = 0 R: Recessive = 1 •...
Page 650 Chapter 19 CAN Controller (CAN) <8> Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. • The bus state differs depending on the error status. –...
Page 651 CAN Controller (CAN) Chapter 19 • Operation in error status Table 19-6 Operation in error status Error Status Operation Error active A node in this status can transmit immediately after a 3-bit intermission. Error passive A node in this status can transmit 8 bits after the intermission. Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com...
Page 652: Error Frame
Chapter 19 CAN Controller (CAN) 19.2.4 Error frame An error frame is output by a node that has detected an error. Error frame (<4>) <1> <2> <3> (<5>) 6 bits 0 to 6 bits 8 bits Interframe space or overload frame Error delimiter Error flag 2 Error flag 1...
Page 653: Overload Frame
CAN Controller (CAN) Chapter 19 19.2.5 Overload frame An overload frame is transmitted under the following conditions. • When the receiving node has not completed the reception operation • If a dominant level is detected at the first two bits during intermission •...
Page 654: Functions
Chapter 19 CAN Controller (CAN) 19.3 Functions 19.3.1 Determining bus priority When a node starts transmission: • During bus idle, the node that output data first transmits the data. When more than one node starts transmission: • The node that consecutively outputs the dominant level for the longest from the first bit of the arbitration field has the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value).
Page 655: Multi Masters
CAN Controller (CAN) Chapter 19 19.3.3 Multi masters As the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus master. 19.3.4 Multi cast Although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes.
Page 656 Chapter 19 CAN Controller (CAN) Output timing of error frame Table 19-12 Output timing of error frame Type Output Timing Bit error, stuff error, Error frame output is started at the timing of the bit following form error, ACK error the detected error.
Page 657 CAN Controller (CAN) Chapter 19 Table 19-13 Types of error states Value of Error Indication of Type Operation Operation Specific to Error State Counter CnINFO Register Error active Transmission 0 to 95 TECS1, TECS0 = 00 Outputs an active error flag (6 consecutive dominant-level bits) on detection of the error.
Page 658 Chapter 19 CAN Controller (CAN) (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counter is updated during the first bit of the error delimiter. Table 19-14 Error counter Transmission error counter Reception error counter...
Page 659 CAN Controller (CAN) Chapter 19 (c) Occurrence of bit error in intermission An overload frame is generated. Caution If an error occurs, it is controlled according to the contents of the transmission error counter and reception error counter before the error occurred. The value of the error counter is incremented after the error flag has been output.
Page 660 Chapter 19 CAN Controller (CAN) Caution In the bus-off recovery sequence, the REC0 to REC6 bits counts up (+1) each time 11 consecutive recessive-level bits have been detected. Even during the bus-off period, the CAN module can enter the CAN sleep mode or CAN stop mode.
Page 661 CAN Controller (CAN) Chapter 19 (b) Forced recovery operation that skips bus-off recovery sequence The CAN module can be forcibly released from the bus-off state, regardless of the bus state, by skipping the bus-off recovery sequence. Here is the procedure. First, the CAN module requests to enter the initialization mode.
Page 662: Baud Rate Control Function
Chapter 19 CAN Controller (CAN) 19.3.7 Baud rate control function Prescaler The CAN Controller has a prescaler that divides the clock (f ) supplied to CAN. This prescaler generates a CAN protocol layer base clock (f ) that is the CAN module system clock (f ) divided by 1 to 256 (“CnBRP - CANn CANMOD...
Page 663 CAN Controller (CAN) Chapter 19 Data bit time(DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 Sample point (SPT) Figure 19-19 Configuration of data bit time defined by CAN specification Table 19-16 Configuration of data bit time defined by CAN specification Notes on setting to conform to CAN Segment name Settable range...
Page 664 Chapter 19 CAN Controller (CAN) Synchronizing data bit • The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. • The transmitting node transmits data in synchronization with the bit timing of the transmitting node.
Page 665: Connection With Target System
CAN Controller (CAN) Chapter 19 If phase error is positive CAN bus Prop Sync Phase Bit timing Phase segment 1 segment segment segment 2 Sample point If phase error is negative CAN bus Prop Sync Phase Bit timing Phase segment 1 segment segment segment 2...
Page 666: Internal Registers Of Can Controller
Chapter 19 CAN Controller (CAN) 19.5 Internal Registers of CAN Controller 19.5.1 CAN module register and message buffer addresses In this chapter all register and message buffer addresses are defined as address offsets to different base addresses. Since all registers are accessed via the programmable peripheral area the bottom address is defined by the BPC register (refer to “Programmable peripheral I/O area“...
Page 667: Can Controller Configuration
CAN Controller (CAN) Chapter 19 19.5.2 CAN controller configuration Table 19-18 List of CAN controller registers Item Register Name CAN global registers CANn global control register (CnGMCTRL) CANn global clock selection register (CnGMCS) CANn global automatic block transmission control register (CnGMABT) CANn global automatic block transmission delay setting register (CnGMABTD) CAN module registers CANn module mask 1 register (CnMASK1L, CnMASK1H)
Page 668: Can Registers Overview
Chapter 19 CAN Controller (CAN) 19.5.3 CAN registers overview CAN0 module registers The following table lists the address offsets to the CAN0 register base address: C0RBaseAddr = PBA Table 19-19 CAN0 global and module registers Access Address Register name Symbol After reset offset 1-bit...
Page 669 CAN Controller (CAN) Chapter 19 The addresses in the following table denote the address offsets to the CAN0 message buffer base address: C0MBaseAddr = PBA + 100 Example CAN0, message buffer register m = 14 = E , byte 6 C0MDATA614 has the address E x 20 + C0MBaseAddr...
Page 670 Chapter 19 CAN Controller (CAN) CAN1 module registers The following table lists the address offsets to the CAN1 register base address: C1RBaseAddr = PBA + 600 Table 19-21 CAN1 global and module registersM Access Address Register name Symbol After reset offset 1-bit 8-bit...
Page 671 CAN Controller (CAN) Chapter 19 The addresses in the following table denote the address offsets to the CAN0 message buffer base address: C1MBaseAddr = PBA + 700 Example CAN1, message buffer register m = 23 = 17 , byte 3 C1MDATA323 has the address 17 x 20 + C1MBaseAddr...
Page 672: Register Bit Configuration
Chapter 19 CAN Controller (CAN) 19.5.4 Register bit configuration Table 19-23 CAN global register bits configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 offset CnGMCTRL (W) Clear GOM Set EFSD Set GOM CnGMCTRL (R) EFSD...
Page 673 CAN Controller (CAN) Chapter 19 Table 19-24 CAN module register bit configuration (2/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 offset CnLEC (R) LEC2 LEC1 LEC0 CnINFO BOFF TECS1 TECS0 RECS1 RECS0...
Page 674 Chapter 19 CAN Controller (CAN) Table 19-25 Message buffer register bit configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 offset CnMDATA01m Message data (byte 0) Message data (byte 1) CnMDATA0m Message data (byte 0) CnMDATA1m...
Page 675: Control Registers
CAN Controller (CAN) Chapter 19 19.6 Control Registers CnGMCTRL - CANn global control register The CnGMCTRL register is used to control the operation of the CAN module. After reset: 0000H Address: <CnRBaseAddr> + 000 (a) Read CnGMCTRL MBON EFSD MBON Bit enabling access to message buffer register, transmit/receive history registers Write access and read access to the message buffer register and the transmit/receive history list registers is disabled.
Page 676 Chapter 19 CAN Controller (CAN) EFSD Bit enabling forced shut down Forced shut down by GOM bit = 0 disabled. Forced shut down by GOM bit = 0 enabled. Caution To request forced shut down, the GOM bit must be cleared to 0 immediately after the EFSD bit has been set to 1.
Page 677 CAN Controller (CAN) Chapter 19 CnGMCS - CANn global clock selection register The CnGMCS register is used to select the CAN module system clock. After reset: 0FH Address: <CnRBaseAddr> + 002 CnGMCS CCP3 CCP2 CCP1 CCP0 CCP3 CCP2 CCP1 CCP1 CAN module system clock (f CANMOD /16 (Default value)
Page 678 Chapter 19 CAN Controller (CAN) CnGMABT - CANn global automatic block transmission control register The CnGMABT register is used to control the automatic block transmission (ABT) operation. After reset: 0000H Address: <CnRBaseAddr> + 006 (a) Read CnGMABT ABTCLR ABTTRG ABTCLR Automatic block transmission engine clear status bit Clearing the automatic transmission engine is completed.
Page 679 CAN Controller (CAN) Chapter 19 (b) Write CnGMABT ABTCLR ABTTRG Clear ABTTRG Caution Before changing the normal operation mode with ABT to the initialization mode, be sure to set the CnGMABT register to the default value (00H). Set ABTCLR Automatic block transmission engine clear request bit The automatic block transmission engine is in idle status or under operation.
Page 680 Chapter 19 CAN Controller (CAN) CnGMABTD - CANn global automatic block transmission delay register The CnGMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT.
Page 681 CAN Controller (CAN) Chapter 19 CnMASKaL, CnMASKaH - CANn module mask control register (a = 1 to 4) The CnMASKaL and CnMASKaH registers are used to extend the number of receivable messages by masking part of the identifier (ID) of a message and invalidating the ID of the masked part.
Page 682 Chapter 19 CAN Controller (CAN) (c) CANn module mask 3 register (CnMASK3L, CnMASK3H) After reset: Undefined Address: CnMASK3L <CnRBaseAddr> + 048 CnMASK3H <CnRBaseAddr> + 04A CnMASK3L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 CnMASK3H...
Page 683 CAN Controller (CAN) Chapter 19 CnCTRL - CANn module control register The CnCTRL register is used to control the operation mode of the CAN module. After reset: 0000H R/W Address: CnCTRL <CnRBaseAddr> + 050 (a) Read CnCTRL RSTAT TSTAT PSMODE PSMODE OPMODE OPMODE...
Page 684 Chapter 19 CAN Controller (CAN) CCERC Error counter clear bit The CnERC and CnINFO registers are not cleared in the initialization mode. The CnERC and CnINFO registers are cleared in the initialization mode. Note The CCERC bit is used to clear the CnERC and CnINFO registers for re- initialization or forced recovery from the bus-off status.
Page 685 CAN Controller (CAN) Chapter 19 Caution Transition to and from the CAN stop mode must be made via CAN sleep mode. A request for direct transition to and from the CAN stop mode is ignored. OPMODE2 OPMODE1 OPMODE0 Operation mode No operation mode is selected (CAN module is in the initialization mode).
Page 686 Chapter 19 CAN Controller (CAN) Clear Setting of PSMODE0 bit PSMODE0 PSMODE0 PSMODE0 bit is cleared to 0. PSMODE bit is set to 1. Other than above PSMODE0 bit is not changed. Clear Setting of PSMODE1 bit PSMODE1 PSMODE1 PSMODE1 bit is cleared to 0. PSMODE1 bit is set to 1.
Page 687 CAN Controller (CAN) Chapter 19 CnLEC - CANn module last error information register The CnLEC register provides the error information of the CAN protocol. After reset: 00H Address: CnLEC <CnRBaseAddr> + 052 CnLEC LEC2 LEC1 LEC0 Note The contents of the CnLEC register are not cleared when the CAN module changes from an operation mode to the initialization mode.
Page 688 Chapter 19 CAN Controller (CAN) CnINFO - CANn module information register The CnINFO register indicates the status of the CAN module. After reset: 00H Address: CnINFO <CnRBaseAddr> + 053 CnINFO BOFF TECS1 TECS0 RECS1 RECS0 BOFF Bus-off status bit Not bus-off status (transmit error counter ≤ 255). (The value of the transmit counter is less than 256.) Bus-off status (transmit error counter >...
Page 689 CAN Controller (CAN) Chapter 19 CnERC - CANn module error counter register The CnERC register indicates the count value of the transmission/reception error counter. After reset: 0000H R Address: CnERC <CnRBaseAddr> + 054H CnERC REPS REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7...
Page 690 Chapter 19 CAN Controller (CAN) (10) CnIE - CANn module interrupt enable register The CnIE register is used to enable or disable the interrupts of the CAN module. After reset: 0000H R/W Address: CnIE <CnRBaseAddr> + 056 (a) Read CnIE CIE5 CIE4 CIE3...
Page 691 CAN Controller (CAN) Chapter 19 Set CIE2 Clear CIE2 Setting of CIE2 bit CIE2 bit is cleared to 0. CIE2 bit is set to 1. Other than above CIE2 bit is not changed. Set CIE1 Clear CIE1 Setting of CIE1 bit CIE1 bit is cleared to 0.
Page 692 Chapter 19 CAN Controller (CAN) Note The CINTS5 bit is set only when the CAN module is woken up from the CAN sleep mode by a CAN bus operation. The CINTS5 bit is not set when the CAN sleep mode has been released by software. (b) Write CnINTS Clear...
Page 693 CAN Controller (CAN) Chapter 19 (12) CnBRP - CANn module bit rate prescaler register The CnBRP register is used to select the CAN protocol layer base clock (f The communication baud rate is set to the CnBTR register. After reset: FFH Address: CnBRP <CnRBaseAddr>...
Page 694 Chapter 19 CAN Controller (CAN) CnBTR SJW1 SJW0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Data bit time (DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 Time segment 1 (TSEG1) Time segment 2 (TSEG2) Sample point (SPT) Figure 19-24 Data bit time SJW1...
Page 695 CAN Controller (CAN) Chapter 19 TSEG13 TSEG12 TSEG11 TSEG10 Length of time segment 1 Setting prohibited Note Note 10TQ 11TQ 12TQ 13TQ 14TQ 15TQ 16TQ (default value) Note This setting must not be made when the CnBRP register = 00H. TQ = 1/f : CAN protocol layer basic system clock) (14)
Page 696 Chapter 19 CAN Controller (CAN) (15) CnRGPT - CANn module receive history list register The CnRGPT register is used to read the receive history list. After reset: xx02H Address: CnRGPT <CnRBaseAddr> + 060 (a) Read CnRGPT RGPT7 RGPT6 RGPT5 RGPT4 RGPT3 RGPT2 RGPT1...
Page 697 CAN Controller (CAN) Chapter 19 (b) Write CnRGPT Clear ROVF Clear Setting of ROVF bit ROVF ROVF bit is not changed. ROVF bit is cleared to 0. (16) CnLOPT - CANn module last out-pointer register The CnLOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last.
Page 698 Chapter 19 CAN Controller (CAN) (17) CnTGPT - CANn module transmit history list register The CnTGPT register is used to read the transmit history list. After reset: xx02H Address: CnTGPT <CnRBaseAddr> + 064 (a) Read CnTGPT TGPT7 TGPT6 TGPT5 TGPT4 TGPT3 TGPT2 TGPT1...
Page 699 CAN Controller (CAN) Chapter 19 Clear TOVF Setting of TOVF bit TOVF bit is not changed. TOVF bit is cleared to 0. Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 700 Chapter 19 CAN Controller (CAN) (18) CnTS - CANn module time stamp register The CnTS register is used to control the time stamp function. After reset: 0000H Address: CnTS <CnRBaseAddr> + 066 (a) Read CnTS TSLOCK TSSEL TSEN TSLOCK Time stamp lock function enable bit Time stamp lock function stopped.
Page 701 CAN Controller (CAN) Chapter 19 Clear Setting of TSLOCK bit TSLOCK TSLOCK TSLOCK bit is cleared to 0. TSLOCK bit is set to 1. Other than above TSLOCK bit is not changed. Clear Setting of TSSEL bit TSSEL TSSEL TSSEL bit is cleared to 0. TSSEL bit is set to 1.
Page 702 Chapter 19 CAN Controller (CAN) (19) CnMDATAxm - CANn message data byte register (x = 0 to 7) The CnMDATAxm register is used to store the data of a transmit/receive message. After reset: Undefined Address: refer to “CAN registers overview“ on page 668 MDATA01 MDATA01 MDATA01...
Page 703 CAN Controller (CAN) Chapter 19 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 CnMDATA45m MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 CnMDATA4m MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 CnMDATA5m MDATA67 MDATA67 MDATA67...
Page 704 Chapter 19 CAN Controller (CAN) (20) CnMDLCm - CANn message data length register m The CnMDLCm register is used to set the number of bytes of the data field of a message buffer. After reset: 0000xxxxB Address: refer to “CAN registers overview“ on page 668 CnMDLCm MDLC3 MDLC2...
Page 705 CAN Controller (CAN) Chapter 19 (21) CnMCONFm - CANn message configuration register m The CnMCONFm register is used to specify the type of the message buffer and to set a mask. After reset: Undefined Address: refer to “CAN registers overview“ on page 668 CnMCONFm Overwrite control bit Note...
Page 706 Chapter 19 CAN Controller (CAN) Message buffer assignment bit Message buffer not used. Message buffer used. Caution Be sure to write 0 to bits 2 and 1. (22) CnMIDLm, CnMIDHm - CANn message ID register m The CnMIDLm and CnMIDHm registers are used to set an identifier (ID). After reset: Undefined Address: refer to “CAN registers overview“...
Page 707 CAN Controller (CAN) Chapter 19 (23) CnMCTRLm - CANn message control register m The CnMCTRLm register is used to control the operation of the message buffer. After reset: 00x000000 Address: refer to “CAN registers overview“ on page 668 00000000B (a) Read CnMCTRLm Note Bit indicating that message buffer data is being updated...
Page 708 Chapter 19 CAN Controller (CAN) Message buffer ready bit The message buffer can be written by software. The CAN module cannot write to the message buffer. Writing the message buffer by software is ignored (except a write access to the RDY, TRQ, DN, and MOW bits).
Page 709: Bit Set/Clear Function
CAN Controller (CAN) Chapter 19 19.7 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.
Page 710 Chapter 19 CAN Controller (CAN) Register’s current value Write value clear 1 Register’s value after write operation Figure 19-25 Example of bit setting/clearing operations Bit Status After Bit Setting/Clearing Operations Clear Clear Clear Clear Clear Clear Clear Clear Set 7 Set 6 Set 5 Set 4...
Page 711: Can Controller Initialization
CAN Controller (CAN) Chapter 19 19.8 CAN Controller Initialization 19.8.1 Initialization of CAN module Before CAN module operation is enabled, the CAN module system clock needs to be determined by setting the CnGMCS.CCP0 to CnGMCS.CCP3 bits by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled.
Page 712 Chapter 19 CAN Controller (CAN) Redefinition completed Execute transmission? Wait for 1 bit of CAN data. Set TRQ bit Set TRQ bit = 1 Clear TRQ bit = 0 Figure 19-26 Setting transmission request (TRQ) to transmit message buffer after redefinition Caution When a message is received, reception filtering is performed in accordance...
Page 713: Transition From Initialization Mode To Operation Mode
CAN Controller (CAN) Chapter 19 19.9 Transition from Initialization Mode to Operation Mode The CAN module can be switched to the following operation modes. • Normal operation mode • Normal operation mode with ABT • Receive-only mode • Single-shot mode •...
Page 714: Resetting Error Counter Cnerc Of Can Module
Chapter 19 CAN Controller (CAN) 19.9.1 Resetting error counter CNERC of CAN module If it is necessary to reset the CnERC and CnINFO registers when re- initialization or forced recovery from the bus-off status is made, set the CnCTRL.CCERC bit to 1 in the initialization mode. When this bit is set to 1, the CnERC and CnINFO registers are cleared to their default values.
Page 715: Receive History List Function
CAN Controller (CAN) Chapter 19 19.10.2 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding CnLIPT register and the receive history list get pointer (RGPT) with the corresponding CnRGPT register.
Page 716 Chapter 19 CAN Controller (CAN) Receive history list (RHL) Receive history list (RHL) When message buffer 6 is read If message is stored in message buffers 3, 4, and 8 Last in-message pointer (LIPT) Message buffer 8 Message buffer 4 Last in-message Message buffer 3 pointer (LIPT)
Page 717: Mask Function
CAN Controller (CAN) Chapter 19 19.10.3 Mask function It can be defined whether masking of the identifier that is set to a message buffer is linked with another message buffer. By using the mask function, the identifier of a message received from the CAN bus can be compared with the identifier set to a message buffer in advance.
Page 718 Chapter 19 CAN Controller (CAN) <3> Mask setting for CAN module 1 (mask 1) (Example) (Using CAN1 address mask 1 registers L and H (C1MASKL1 and C1MASKH1)) CMID2 CMID2 CMID2 CMID2 CMID2 CMID2 CMID2 CMID2 CMID2 CMID1 CMID1 CMID1 CMID1 CMID1 CMID1 CMID1...
Page 719: Multi Buffer Receive Block Function
CAN Controller (CAN) Chapter 19 19.10.4 Multi buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type.
Page 720: Remote Frame Reception
Chapter 19 CAN Controller (CAN) 19.10.5 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. •...
Page 721: Message Transmission
CAN Controller (CAN) Chapter 19 19.11 Message Transmission 19.11.1 Message transmission In all the operation modes, if the CnMCTRLm.TRQ bit is set to 1 in a message buffer that satisfies the following conditions, the message buffer that is to transmit a message is searched. •...
Page 722 Chapter 19 CAN Controller (CAN) Priority Conditions Description 1 (high) Value of first 11 bits of ID The message frame with the lowest value represented by the first 11 [ID28 to ID18]: bits of the ID is transmitted first. If the value of an 11-bit standard ID is equal to or smaller than the first 11 bits of a 29-bit extended ID, the 11- bit standard ID has a higher priority than a message frame with a 29-bit extended ID.
Page 723: Transmit History List Function
CAN Controller (CAN) Chapter 19 19.11.2 Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer in which each data frame or remote frame was received and stored. The THL consists of storage elements equivalent to up to seven messages, the last out-message pointer (LOPT) with the corresponding CnLOPT register, and the transmit history list get pointer (TGPT) with the corresponding CnTGPT register.
Page 724 Chapter 19 CAN Controller (CAN) Transmit history list (THL) When message buffer 6 is read Transmit history list (THL) If transmission from message buffers 3 and 4 Last Message buffer 4 Last out-message is completed out-message Message buffer 3 pointer (LOPT) pointer (LOPT) Message buffer 7 Message buffer 7...
Page 725: Automatic Block Transmission (Abt)
CAN Controller (CAN) Chapter 19 19.11.3 Automatic block transmission (ABT) The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message buffer numbers 0 to 7).
Page 726 Chapter 19 CAN Controller (CAN) Transmission of a data frame from an ABT message buffer is not recorded in the transmit history list (THL). Caution Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0. If the ABTCLR bit is set to 1 while the ABTTRG bit is set to 1, the subsequent operation is not guaranteed.
Page 727: Transmission Abort Process
CAN Controller (CAN) Chapter 19 19.11.4 Transmission abort process Transmission abort in normal operation mode The user can clear the CnMCTRLm.TRQ bit to 0 to abort a transmission request. The TRQ bit will be cleared immediately if the abort was successful. Whether the transmission was successfully aborted or not can be checked using the CnCTRL.TSTAT bit and the CnTGPT register, which indicate the transmission status on the CAN bus (for details, refer to the processing in...
Page 728: Power Saving Modes
Chapter 19 CAN Controller (CAN) 19.12 Power Saving Modes 19.12.1 CAN sleep mode The CAN sleep mode can be used to set the CAN Controller to stand-by mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes.
Page 729 CAN Controller (CAN) Chapter 19 •If a CAN sleep mode request is pending waiting for the CAN bus state to become bus idle while the CAN module is in one of the operation modes, and if a request for transition to the initialization mode is made, the pending CAN sleep mode request becomes disabled, and only the initialization mode request is enabled (in this case, the CAN sleep mode request continues to be held pending).
Page 730: Can Stop Mode
Chapter 19 CAN Controller (CAN) 19.12.2 CAN stop mode The CAN stop mode can be used to set the CAN Controller to stand-by mode to reduce power consumption. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the CAN module in the CAN sleep mode.
Page 731: Example Of Using Power Saving Modes
CAN Controller (CAN) Chapter 19 19.12.3 Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus.
Page 732: Interrupt Function
Chapter 19 CAN Controller (CAN) 19.13 Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register.
Page 733: Diagnosis Functions And Special Operational Modes
CAN Controller (CAN) Chapter 19 19.14 Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self- test mode to support CAN bus diagnosis functions or the operation of special CAN communication methods. 19.14.1 Receive-only mode The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and can be used for CAN bus analysis nodes.
Page 734: Single-Shot Mode
Chapter 19 CAN Controller (CAN) transmitted from the CAN module to the CAN bus even when a CAN bus error is detected while receiving a message frame. Since no transmission can be issued from the CAN module, the transmission error counter the CnERC.TEC7 to CnERC.TEC0 bits are never updated.
Page 735: Self-Test Mode
CAN Controller (CAN) Chapter 19 19.14.3 Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or without affecting the CAN bus. In the self-test mode, the CAN module is completely disconnected from the CAN bus, but transmission and reception are internally looped back.
Page 736: Time Stamp Function
Chapter 19 CAN Controller (CAN) 19.15 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may even have different frequencies).
Page 737: Baud Rate Settings
CAN Controller (CAN) Chapter 19 Caution The time stamp function using the TSLOCK bit stops toggle of the TSOUT signal by receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer. Since a receive message buffer cannot receive a remote frame, toggle of the TSOUT signal cannot be stopped by reception of a remote frame.
Page 738 Chapter 19 CAN Controller (CAN) Table 19-27 shows the combinations of bit rates that satisfy the above conditions. Table 19-27 Settable bit rate combinations (1/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG13 to TSEG22 to (unit %) DBT length...
Page 739 CAN Controller (CAN) Chapter 19 Table 19-27 Settable bit rate combinations (2/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG13 to TSEG22 to (unit %) DBT length SEGMENT SEGMENT SEGMENT1 SEGMENT2 TSEG10 TSEG20 1001 64.7 1010...
Page 740 Chapter 19 CAN Controller (CAN) Table 19-27 Settable bit rate combinations (3/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG13 to TSEG22 to (unit %) DBT length SEGMENT SEGMENT SEGMENT1 SEGMENT2 TSEG10 TSEG20 1000 83.3 1001...
Page 741: Representative Examples Of Baud Rate Settings
CAN Controller (CAN) Chapter 19 19.16.2 Representative examples of baud rate settings Table 19-28 and Table 19-29 show representative examples of baud rate settings. Table 19-28 Representative examples of baud rate settings = 8 MHz) (1/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud...
Page 742 Chapter 19 CAN Controller (CAN) Table 19-28 Representative examples of baud rate settings = 8 MHz) (2/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC...
Page 743 CAN Controller (CAN) Chapter 19 Table 19-29 Representative examples of baud rate settings = 16 MHz) (1/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC...
Page 744 Chapter 19 CAN Controller (CAN) Table 19-29 Representative examples of baud rate settings = 16 MHz) (2/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC...
Page 745: Operation Of Can Controller
CAN Controller (CAN) Chapter 19 19.17 Operation of CAN Controller START CnGMCS register. CnGMCTRL register (set GOM bit = 1) CnBRP register, CnBTR register. CnIE register. CnMASK register. Initialize message buffers. Set CnCTRL register (set OPMODE bit). Figure 19-34 Initialization Note OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single-shot mode, self-test mode...
Page 746 Chapter 19 CAN Controller (CAN) START Clear OPMODE. INIT mode? CnBRP register, Initialize message CnBTR register. buffers. CnIE register. CnERC and CnINFO register clear? CnMASK register. Set CCERC bit. Set CCERC bit = 1 Clear CCERC bit = 0 Set CnCTRL register. (set OPMODE bit) Figure 19-35...
Page 747 CAN Controller (CAN) Chapter 19 START = 1? Clear RDY bit. Set RDY Clear RDY = 0? CnMCONFm register. CnMIDHm register, CnMIDLm register. Transmit message buffer? CnMDLCm register. Clear CnMDATAm register. CnMCTRLm register. Set RDY bit. Set RDY Clear RDY Figure 19-36 Message buffer initialization Caution...
Page 748 Chapter 19 CAN Controller (CAN) Figure 19-37 shows the processing for a receive message buffer (CnMCONFm.MT2 to CnMCONFm.MT0 bits = 001B to 101B). START Clear VALID bit. = 1? Clear RDY bit. Set RDY Clear RDY = 0? message buffers. RSTAT = 0 or VALID...
Page 749 CAN Controller (CAN) Chapter 19 Figure 19-38 shows the processing for a transmit message buffer (CnMCONFm.MT2 to CnMCONFm.MT0 bits = 000B). START = 0? Clear RDY bit. Set RDY Clear RDY = 0? Data frame Remote frame Data frame remote frame? Clear RTR bit of Set RTR bit of CnMDLCm CnMDATAxm register,...
Page 750 Chapter 19 CAN Controller (CAN) Figure 19-39 shows the processing for a transmit message buffer (CnMCONFm.MT2 to CnMCONFm.MT0 bits = 000B) Start ABTTRG = 0? Clear RDY bit. Set RDY Clear RDY = 0? Clear RTR bit of CnMDATAxm register, CnMDLCm register, and CnMCONFm register.
Page 751 CAN Controller (CAN) Chapter 19 Start Transmit completion interrupt processing Read CnLOPT register. Clear RDY bit. Set RDY Clear RDY = 0? Data frame Remote frame Data frame remote frame? Clear RTR bit of Set RTR bit of CnMDATAxm register, CnMDLCm register and CnMDLCm register, CnMCONFm register.
Page 752 Chapter 19 CAN Controller (CAN) START Transmit completion interrupt processing Read CnTGPT register. TOVF = 1? Clear TOVF bit. Clear TOVF Clear RDY bit. Set RDY Clear RDY = 0? Set RDY bit. Set RDY Clear RDY Set TRQ bit. Data frame Remote frame Data frame...
Page 753 CAN Controller (CAN) Chapter 19 START CINTS0 bit = 1? Clear CINTS0 bit. Clear CINTS0 bit = 1 Read CnTGPT register. TOVF bit = 1? Clear TOVF bit. Clear TOVF bit = 1 Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 RDY bit = 0? Set RDY bit.
Page 754 Chapter 19 CAN Controller (CAN) START Clear TRQ bit. Set TRQ bit = 0 Clear TRQ bit = 1 Wait for 11 CAN data bits. TSTAT bit = 0? Read CnLOPT register. Message buffer to be aborted matches CnLOPT register? Transmit abort request was successful.
Page 755 CAN Controller (CAN) Chapter 19 Figure 19-44 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. START Clear ABTTRG bit. Set ABTTRG bit = 0 Clear ABTTRG bit = 1 ABTTRG bit = 0? Clear TRQ bit of message buffer whose transmission...
Page 756 Chapter 19 CAN Controller (CAN) Figure 19-45 shows the processing to not skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. START Clear TRQ bit of message buffer undergoing transmission. Clear ABTTRG bit. Set ABTTRG bit = 0 Clear ABTTRG bit = 1 ABTTRG bit = 0?
Page 757 CAN Controller (CAN) Chapter 19 START Transmit abort Read CnLIPT register. Clear DN bit. Clear DN bit = 1 Read CnMDATAxm, CnMDLCm, CnMIDLm, and CnMIDHm registers. DN bit = 0 Note MUC bit = 0 Clear CINTS1 bit. Clear CINTS1 bit = 1 Figure 19-46 Reception via interrupt (using CnLIPT register) Note...
Page 758 Chapter 19 CAN Controller (CAN) START Receive completion interrupt Read CnRGPT register. ROVF bit = 1? Clear ROVF bit. Clear ROVF bit = 1 DN bit = 0 Clear DN bit. Clear DN bit = 1 Note MUC bit = 0 Read CnMDATAxm, CnMDLCm, CnMIDLm, and...
Page 759 CAN Controller (CAN) Chapter 19 Start CINTS1 bit = 1? Clear CINTS1 bit. Clear CINTS1 bit = 1 Read CnRGPT register. ROVF bit = 1? Clear ROVF bit. Clear ROVF bit = 1 DN bit = 0 Clear DN bit. Clear DN bit = 1 Note MUC bit = 0...
Page 760 Chapter 19 CAN Controller (CAN) START (when PSMODE [1:0] = 00B) Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? Clear CINTS5 bit. Clear CINTS5 bit = 1 CAN sleep mode Set PSMODE1 bit. Set PSMODE1 bit = 1 Clear PSMODE1 bit = 0 PSMODE1 bit = 1?
Page 761 CAN Controller (CAN) Chapter 19 START CAN stop mode Clear PSMODE1 bit. Set PSMODE1 bit = 0 Clear PSMODE1 bit = 1 CAN sleep mode Releasing CAN sleep mode by CAN bus active Releasing CAN sleep mode Bus activity = 0 by user PSMODE0 bit = 0 CINTS5 bit = 1...
Page 762 Chapter 19 CAN Controller (CAN) START BOFF bit = 1? Set CnCTRL register. (clear OPMODE bit) DN = 0 INIT mode ? MUC = 0 Access to register other than CnCTRL and CnGMCTRL registers. Forced recovery from bus off? Set CCERC bit. Set CnCTRL register.
Page 763 CAN Controller (CAN) Chapter 19 START INIT mode Clear GOM bit. Set GOM bit = 0 Clear GOM bit = 1 GOM bit = 0? Shutdown successful GOM bit = 0, EFSD bit = 0 Figure 19-52 Normal shutdown process Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com...
Page 764 Chapter 19 CAN Controller (CAN) START Set EFSD bit. Set EFSD bit = 1 Must be a continuous write. Clear GOM bit. Set GOM bit = 0 Clear GOM bit = 1 GOM bit = 0? Shutdown successful GOM bit = 0, EFSD bit = 0 Figure 19-53 Forced shutdown process...
Page 765 CAN Controller (CAN) Chapter 19 START Error interrupt CINTS2 bit = 1? Check CAN module state. (read CnINFO register) Clear CINTS2 bit. Clear CINTS2 bit = 1 CINTS3 bit = 1? CINTS4 bit = 1? Check CAN protocol error state. Clear CINTS4 bit.
Page 766 Chapter 19 CAN Controller (CAN) START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? Clear CINTS5 bit. Clear CINTS5 bit = 1 CAN sleep mode CINTS5 bit = 1? MBON bit = 0? Set CPU standby mode.
Page 767 CAN Controller (CAN) Chapter 19 START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? Clear CINTS5 bit. Clear CINTS5 bit = 1 CAN sleep mode Set PSMODE1 bit. Set PSMODE1 bit = 1 Clear PSMODE1 bit = 0 PSMODE1 bit = 1? CAN stop mode...
Page 768: Operating Precautions
Chapter 19 CAN Controller (CAN) 19.18 Operating Precautions 19.18.1 Wake-up from sleep mode Description When the CAN macro is set into SLEEP mode, it can be waken up by CAN bus activity. This waking up is asynchronous to the operation of the macro and the CPU. By configuration setting, a WAKEUP interrupt can be generated by the CAN macro on the wakeup event.
Page 769: Chapter 20 A/D Converter (Adc)
Chapter 20 A/D Converter (ADC) These microcontrollers contain an n-channel 10-bit A/D Converter. The V850E/Dx3 microcontrollers have following number of the channels: µPD70F3427, µPD70F3426 µPD70F3423, µPD70(F)3422 µPD70F3425, µPD70F3424 µPD70(F)3421, µPD70(F)3420 Instances Throughout this chapter, the individual channels of the A/D Converter are identified by “n”, for example ADCR0n for the A/D conversion result register of...
Page 770 Chapter 20 A/D Converter (ADC) The block diagram of the A/D Converter is shown below. ADA0CE bit ADA0CE bit ANI0 Sample & hold circuit ANI1 ANI2 ADA0CE bit Voltage comparator ANIn SPCLK0 (16 MHz) ADCR00 INTTZ5UV Controller ADCR01 INTAD ADCR0n ADA0M0 ADA0M1 ADA0M2 ADA0S Internal bus Figure 20-1...
Page 771: Configuration
A/D Converter (ADC) Chapter 20 20.2 Configuration The A/D Converter includes the following hardware. Table 20-1 Configuration of A/D Converter Item Configuration Analog inputs ANI0 to ANIn pins Registers Successive approximation register (SAR) A/D conversion result registers ADCR00 to ADCR0n A/D conversion result registers ADCR0H0 to ADCR0Hn: only higher 8 bits can be read Control registers...
Page 772 Chapter 20 A/D Converter (ADC) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets a threshold value that is compared with the value of A/D conversion result register nH (ADCR0Hn). The 8-bit data set to the ADA0PFT register is compared with the higher 8 bits of the A/D conversion result register (ADCR0Hn).
Page 773: Adc Registers
A/D Converter (ADC) Chapter 20 20.3 ADC Registers The A/D Converter is controlled by the following registers: • A/D Converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) • A/D Converter channel specification register 0 (ADA0S) • Power-fail compare mode register (ADA0PFM) The following registers are also used: •...
Page 774 Chapter 20 A/D Converter (ADC) Caution If bit 0 is written, this is ignored. Changing the ADA0FR3 to ADA0FR0 bits of the ADA0M1 register during conversion (ADA0CE0 bit = 1) is prohibited. When not using the A/D Converter, stop the operation by setting the ADA0CE bit to 0 to reduce the current consumption.
Page 775 A/D Converter (ADC) Chapter 20 Table 20-2 Conversion time settings ADA0FR divider = 16 MHz = 4 MHz SPCLK0 SPCLK0 Stabilization conversion conversion time sampling time sampling time time time prohibited 7.75 µs 4.13 µs 16/f SPCLK0 3.88 µs 2.06 µs 15.50 µs 8.25 µs 31/f...
Page 776 Chapter 20 A/D Converter (ADC) ADA0M2 - ADC mode register 2 The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF203H ADA0TMD ADA0TMD...
Page 777 A/D Converter (ADC) Chapter 20 ADA0S - ADC channel specification register 0 The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 778 Chapter 20 A/D Converter (ADC) ADCR0n, ADCR0Hn - ADC conversion result registers The ADCR0n and ADCR0Hn registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, specify the ADCR0n register for 16-bit access and the ADCR0Hn register for 8-bit access. The 10 bits of the conversion result are read from the higher 10 bits of the ADCR0n register, and 0 is read from the lower 6 bits.
Page 779 A/D Converter (ADC) Chapter 20 The relationship between the analog voltage input to the analog input pins (ANI0 to ANI11) and the A/D conversion result (of A/D conversion result register n (ADCR0n)) is as follows: ----------------- - 1024 • ADCR0 •...
Page 780 Chapter 20 A/D Converter (ADC) ADA0PFM - ADC power-fail compare mode register The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. After reset: 00H Address: FFFFF204H ADA0PFM ADA0PFE...
Page 781: Operation
A/D Converter (ADC) Chapter 20 20.4 Operation 20.4.1 Basic operation 1. Set the operation mode, trigger mode, and conversion time for executing A/ D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is started in the software trigger mode and the A/D Converter waits for a trigger in the external or timer trigger mode.
Page 782: Trigger Mode
Chapter 20 A/D Converter (ADC) 20.4.2 Trigger mode The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode.
Page 783: Operation Modes
A/D Converter (ADC) Chapter 20 20.4.3 Operation modes Two operation modes are available as the modes in which to set the ANIn pins: continuous select mode and continuous scan mode. The operation mode is selected by the ADA0MD1 and ADA0MD0 bits of the ADA0M0 register.
Page 784 Chapter 20 A/D Converter (ADC) (a) Timing example ANI0 Data 1 Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 conversion (ANI0) (ANI1) (ANI2) (ANI3) (ANI0) (ANI1) (ANI2) Data 1...
Page 785: Power-Fail Compare Mode
A/D Converter (ADC) Chapter 20 20.4.4 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers. • If the power-fail compare mode is disabled (ADA0PFM.ADA0PFE = 0), the INTAD signal is generated each time conversion is completed.
Page 786 Chapter 20 A/D Converter (ADC) Continuous scan mode In this mode, the ADC channels starting from ANI0 to the one specified by the ADA0S register are sequentially converted and the conversion results are stored in the ADCR0n registers. Note In continuous scan mode power-fail comparison is performed only on ANI0. After each conversion of ANI0, the higher 8 bits of conversion result in ADA0CR0H0 is compared with the value of the ADA0PFT register.
Page 787 A/D Converter (ADC) Chapter 20 (a) Timing example ANI0 ANI1 ANI2 ANI3 ANI0 ANI1 ANI2 ANI3 ANI0 ANI1 conversion ADCR0n ANI3 ANI0 ANI1 ANI2 ANI3 ANI0 ANI1 INTAD ADA0PFT ADA0PFT unmatch match (b) Block diagram Analog input pin ADCR0n registers ANI0 ADCR00 ANI1...
Page 788: Cautions
Chapter 20 A/D Converter (ADC) 20.5 Cautions When A/D Converter is not used When the A/D Converter is not used, the power consumption can be reduced by clearing the ADA0CE bit of the ADA0M0 register to 0. Input range of ANIn pins Input the voltage within the specified range to the ANIn pins.
Page 789 A/D Converter (ADC) Chapter 20 Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten.
Page 790: How To Read A/D Converter Characteristics Table
Chapter 20 A/D Converter (ADC) 20.6 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D Converter. Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
Page 791 A/D Converter (ADC) Chapter 20 Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D Converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization error is unavoidable.
Page 792 Chapter 20 A/D Converter (ADC) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 0…111 (full scale - 3/2 LSB). Full-scale error 2 AV REF −...
Page 793 A/D Converter (ADC) Chapter 20 Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0.
Page 794 Chapter 20 A/D Converter (ADC) Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 795: Chapter 21 Stepper Motor Controller/Driver (Stepper-C/D)
(Stepper-C/D) The Stepper Motor Controller/Driver module is comprised of six drivers (k = 1 to 6) for external 360° type meters or for bipolar and unipolar stepper motors. The V850E/Dx3 microcontrollers have following instances of the Stepper Motor Controller/Driver: Stepper-C/D...
Page 796 Chapter 21 Stepper Motor Controller/Driver (Stepper-C/D) The Stepper Motor Controller/Driver 0 sub-module is comprised of 4 drivers (k = 1 to 4), Stepper Motor Controller/Driver 1 sub-module is comprised of 2 drivers (k = 5 to 6). Each Stepper Motor Controller/Driver sub-module includes a free running up counter (CNTm).
Page 797: Stepper Motor Controller/Driver Registers
Stepper Motor Controller/Driver (Stepper-C/D) Chapter 21 SPCLK1 SPCLK1/2 SPCLK1/4 SPCLK1/8 SPCLK1 8-bit free-running counter CNT1 SPCLK1/16 (8MHz) SPCLK1/32 SPCLK1/64 SM51 (sin5+) Output SPCLK1/128 1-bit add. Control SM52 (sin5-) 8-bit compare register MCPMn50 circuit SM53 (cos5+) Output Control 1-bit add. SM54 (cos5-) 8-bit compare register MCPMn51 circuit SM61 (sin6+)
Page 798 Chapter 21 Stepper Motor Controller/Driver (Stepper-C/D) Table 21-2 Stepper Motor Controller/Driver registers overview (2/2) Register name Shortcut Address Compare registers MCMPnk0 <base> + 2 (k = 1 to 6) , 18 MCMPnk1 <base> + 3 (k = 1 to 6) , 19 MCMPnkHW <base>...
Page 799 Stepper Motor Controller/Driver (Stepper-C/D) Chapter 21 MCNTCn0, MCNTCn1 - Timer mode control registers The 8-bit MCNTCnm registers control the operation of the free running up counters CNTm. Access These registers can be read/written in 8-bit or 1-bit units. Address MCNTCn0: <base> MCNTCn1: <base>...
Page 800 Chapter 21 Stepper Motor Controller/Driver (Stepper-C/D) Caution In register MCNTCn0, bits 3 and 6 must be 0. In register MCNTCn1, bits 3, 6 and 7 must be 0. Power save mode Before entering any power save mode the Stepper-C/D must be shut down in preparation advance in order to minimize power consumption.
Page 801 Stepper Motor Controller/Driver (Stepper-C/D) Chapter 21 MCMPnk1 - Compare registers for cosine side (k = 1 to 6) The 8-bit MCMPnk1 registers hold the values that define the PWM pulse width for the cosine side of the connected meters. The contents of the registers are continuously compared to the timer counter value: •...
Page 802 Chapter 21 Stepper Motor Controller/Driver (Stepper-C/D) MCMPCnk - Compare control registers (k = 1 to 6) The 8-bit MCMPCnk registers control the operation of the corresponding compare registers and the output direction of the PWM pin. Access These registers can be read/written in 8-bit units. Address <base>...
Page 803: Operation
Stepper Motor Controller/Driver (Stepper-C/D) Chapter 21 21.3 Operation In the following, the operation of the Stepper Motor Controller/Driver module as a driver for external meters is described. 21.3.1 Stepper Motor Controller/Driver operation This section describes the generation of PWM signals of the driver k for driving external meters.
Page 804 Chapter 21 Stepper Motor Controller/Driver (Stepper-C/D) Instruction When writing data to compare registers, proceed as follows: 1. Confirm that MCMPCnk.TEN = 0. 2. Write 8-bit PWM data to MCMPnk0 and MCMPnk1. 3. Set MCMPCnk.ADB0 and MCMPCnk.ADB1 as desired. 4. Set MCMPCnk.TEN = 1 to start the counting operation. The data in MCMPnk0/MCMPnk1 will automatically be copied to the compare slave register when the counter overflows.
Page 805 Stepper Motor Controller/Driver (Stepper-C/D) Chapter 21 MCMPnkm value N CNTm OVF (overflow) Match signal PWM output Figure 21-3 Output timing without 1-bit addition MCMPnkm value N CNTm OVF (overflow) Match signal PWM output one bit is added ADB0 / ADB1 Figure 21-4 Output timing with 1-bit addition Sequence...
Page 806: Timing
Chapter 21 Stepper Motor Controller/Driver (Stepper-C/D) 21.4 Timing This section starts with the timing of the timer counter and general output timing behaviour. Then, examples of output signal generation with and without 1-bit addition are presented. 21.4.1 Timer counter The free running up counter is clocked by the timer count clock selected in register MCNTCnm.
Page 807: Automatic Pwm Phase Shift
Stepper Motor Controller/Driver (Stepper-C/D) Chapter 21 21.4.2 Automatic PWM phase shift Simultaneous switching of sine and cosine output could lead to a fluctuation of the power supply and increase the susceptibility to electromagnetic interference. To prevent this for drivers 1 to 4, the output signals are automatically shifted by one timer count clock cycle defined in MCNTCn0.
Page 808 Chapter 21 Stepper Motor Controller/Driver (Stepper-C/D) Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 809: Chapter 22 Lcd Controller/Driver (Lcd-C/D)
Chapter 22 LCD Controller/Driver (LCD-C/D) The LCD Controller/Driver is provided with the µPD70(F)3420, µPD70(F)3421, µPD70(F)3422 and µPD70F3423 microcontrollers only. This LCD Controller/Driver is suitable for LC displays with up to 160 segments. The supported addressing method of the LCD is multiplex addressing. 22.1 Overview The LCD Controller/Driver generates the signals that are necessary for driving an LCD panel.
Page 810: Description
Chapter 22 LCD Controller/Driver (LCD-C/D) 22.1.1 Description The following figure shows the main components of the LCD Controller/Driver: LCD Clock Selection LCD Frame Frequency Selection LCDCLK LCD0 Prescaler SPCLK7 (125 KHz) Internal Bus SPCLK9 (31.25 KHz) LCD0 LCD0 LCD0 LCD0 Display Data Memory LCD1...
Page 811: Lcd Panel Addressing
LCD Controller/Driver (LCD-C/D) Chapter 22 22.1.2 LCD panel addressing Each individual segment of an LCD panel is addressed by a signal pair: a segment signal and a common signal. The segment becomes visible when the potential difference of the corresponding common signal and the segment signal reaches or exceeds the LCD drive voltage V Example Figure 22-2 shows how the eight LCD segments of a digit are allocated to...
Page 812: Lcd-C/D Registers
Chapter 22 LCD Controller/Driver (LCD-C/D) 22.2 LCD-C/D Registers The LCD Controller/Driver is controlled by means of the following registers: Table 22-3 LCD Controller/Driver registers overview Register name Shortcut Address LCD clock control register LCDC0 FFFF FB00 LCD mode control register LCDM0 FFFF FB01 LCD display control registers...
Page 813 LCD Controller/Driver (LCD-C/D) Chapter 22 LCDC0 - LCD clock control register The 8-bit LCDC0 register determines the duty cycle frequency f LCD1 Access This register can be read/written in 8-bit or 1-bit units. Address FFFF FB00 Initial Value . This register is cleared by any reset. LCDC03 LCDC02 LCDC01 LCDC00 Table 22-4 LCDC0 register contents...
Page 814 Chapter 22 LCD Controller/Driver (LCD-C/D) Possible frame Table 22-5 lists the possible frame frequencies. The values in Table 22-5 are frequencies only examples. Check “Clock Generator“ on page 129 for details. Selection of the following LCD clocks is provided: • LCDC0.LCDC0[3:2] = 00 LCD clock = LCDCLK = f / d, with –...
Page 815 LCD Controller/Driver (LCD-C/D) Chapter 22 LCDM0 - LCD mode control register The 8-bit LCDM0 register enables/disables the LCD operation, activates edge enhancement and selects the power supply. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF FB01 Initial Value .
Page 816: Operation
Chapter 22 LCD Controller/Driver (LCD-C/D) 22.3 Operation The following describes the timing of common and segment signals, the activation of an LCD segment and how edge enhancement can be applied. 22.3.1 Common signals and segment signals This section describes the timing of common signals and segment signals and at which conditions an individual LCD segment becomes visible.
Page 817 LCD Controller/Driver (LCD-C/D) Chapter 22 Segment Signals Segment signals correspond to the contents of the 40 LCD display control registers SEGREG0k. Bits 0 to 3 of these registers are read in synchronization with the common signals COM0 to COM3, this means bit 0 is read in synchronization with common signal COM0 and so on.
Page 818: Activation Of Lcd Segments
Chapter 22 LCD Controller/Driver (LCD-C/D) 22.3.2 Activation of LCD segments An LCD segment becomes visible when the potential difference of the corresponding common signal and segment signal reaches or exceeds the LCD drive voltage V . This is achieved if common and segment signal are at their selection levels.
Page 819 LCD Controller/Driver (LCD-C/D) Chapter 22 From this, it can be seen that 1101 must be prepared in the display control register SEGREG028 and 1111 must be prepared in SEGREG029. Examples of the LCD drive waveforms between SEG28 and the COM0 and COM1 signals are shown in Figure 22-8 on page 821 (for the sake of simplicity, waveforms for COM2 and COM3 have been omitted).
Page 820 Chapter 22 LCD Controller/Driver (LCD-C/D) COM3 COM2 COM1 COM0 SEG0 SEGREG000 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32...
Page 821 LCD Controller/Driver (LCD-C/D) Chapter 22 COM0 COM1 COM2 COM3 SEG28 +1/3V COM0-SEG28 –1/3V –V +1/3V COM1-SEG28 –1/3V –V Figure 22-8 4-time-division LCD drive waveforms – examples Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 822 Chapter 22 LCD Controller/Driver (LCD-C/D) Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 823: Chapter 23 Lcd Bus Interface (Lcd-I/F)
Chapter 23 LCD Bus Interface (LCD-I/F) The LCD Bus Interface connects the internal peripheral bus to an external LCD controller. It provides an asynchronous 8-bit parallel data bus and two control lines. The LCD Bus Interface supports bidirectional communication. You can send data to and query data from the LCD controller.
Page 824: Description
Chapter 23 LCD Bus Interface (LCD-I/F) Note The programmer has to make sure that the timing requirements of the external LCD controller are met. For electrical characteristics please refer to the Electrical Target Specification. If the concerned pins are configured as LCD Bus Interface pins change between input and output is performed automatically by LCD Bus Interface read and write operations.
Page 825: Lcd Bus Interface Access Modes
LCD Bus Interface (LCD-I/F) Chapter 23 The external signals are listed in the following table. Table 23-1 LCD Bus Interface external connections Signal Active Reset Function name level level DBWR mod80: Write strobe (WR) mod68: Read/Write (R/W) DBRD mod80: Read strobe (RD) mod68: E strobe (E) DBD[7:0] LCD data bus...
Page 826: Interrupt Generation
Chapter 23 LCD Bus Interface (LCD-I/F) Read operation When the CPU or the DMA reads the LBDATA0 register, the read operation on the LCD Bus Interface is started. If there is a write transfer in progress while the LBDATA0 register shall be read, the read transfer is stalled and started after the write transfer has completed.
Page 827: Lcd Bus Interface Registers
LCD Bus Interface (LCD-I/F) Chapter 23 23.2 LCD Bus Interface Registers The LCD Bus Interface is controlled and operated by means of the following registers: Table 23-3 LCD Bus Interface registers overview Register name Shortcut Address LCD Bus Interface control register LBCTL0 FFFF FB60 LCD Bus Interface cycle time register...
Page 828 Chapter 23 LCD Bus Interface (LCD-I/F) LBCTL0 - LCD Bus Interface control register The 8-bit LBCTL0 register controls the operation of the LCD Bus Interface. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF FB60 Initial Value .
Page 829 LCD Bus Interface (LCD-I/F) Chapter 23 LBCYC0 - LCD Bus Interface cycle time register The 8-bit LBCYC0 register determines the cycle time of the LCD Bus Interface. The cycle time is the duration of one bus access for transferring one byte. Access This register can be read/written in 8-bit or 1-bit units.
Page 830 Chapter 23 LCD Bus Interface (LCD-I/F) LBWST0 - LCD Bus Interface wait state register The 8-bit LBWST0 register determines the number of wait states of the LCD Bus Interface. The number of wait states defines the duration of the DBWR and DBRD signals.
Page 831 LCD Bus Interface (LCD-I/F) Chapter 23 LBDATA0 - LCD Bus Interface data register The 32-bit LBDATA0 register contains the data that is transferred via the LCD Bus Interface. Access This register can be read/written in 3 different units under following names: •...
Page 832 Chapter 23 LCD Bus Interface (LCD-I/F) Write to this register A write operation to this register sets the busy flag LBCTL0.BYF0 immediately. If there is no LCD bus transfer in progress (LBCTL0.TPF0 = 0), the data is copied to the write buffer and LBCTL0.BYF0 is cleared. If there is a transfer going on (LBCTL0.TPF0 = 1), the data is not copied to the write buffer until the transfer has completed.
Page 833 LCD Bus Interface (LCD-I/F) Chapter 23 LBDATAR0 - LCD Bus Interface data register The LBDATAR0 register is read-only. It contains the data of the last previous read transfer via the LCD Bus Interface. Reading this register does not start a new read transfer on the LCD Bus Interface.
Page 834: Timing
Chapter 23 LCD Bus Interface (LCD-I/F) 23.3 Timing This section starts with the general timing and then presents examples of consecutive write and read operations. 23.3.1 Timing dependencies The following figure shows the general timing when the mod80 mode is used. It illustrates the effect of the LBCYC0 and LBWST0 register settings.
Page 835: Lcd Bus I/F States During And After Accesses
LCD Bus Interface (LCD-I/F) Chapter 23 23.3.2 LCD Bus I/F states during and after accesses Changing between input and output mode of the LCD bus pins DB[7:0] is done automatically after they are configured as LCD Bus Interface pins via the port configuration registers.
Page 836 Chapter 23 LCD Bus Interface (LCD-I/F) 3. All four bytes of the word are transferred back-to-back via the external bus interface. 4. After the transfer on the external bus interface has been completed, the LBCTL0.TPF0 is cleared. Writing halfwords Writing a halfword transmits two bytes to the external LCD Controller/Driver. Write 2 halfword to LBDATA0 register Write 1...
Page 837 LCD Bus Interface (LCD-I/F) Chapter 23 Writing bytes Writing consecutive bytes transmits these bytes to the external LCD controller/ driver. write 3rd byte to LBDATA0 register write 2nd byte to LBDATA0 register write 1st byte to LBDATA0 register SPCLK LBDATA0 1st byte 2nd byte 3rd byte...
Page 838: Reading From The Lcd Bus
Chapter 23 LCD Bus Interface (LCD-I/F) 23.3.4 Reading from the LCD bus You can read from the LCD bus in word, halfword, or byte format. The following shows typical sequences of reading words and bytes. Reading words Reading a word requires the transmission of four bytes. Dummy read word from LBDATA0 register Read word from LBDATA0 register SPCLK...
Page 839 LCD Bus Interface (LCD-I/F) Chapter 23 Reading bytes The following figure shows a byte read operation in mod68 mode. Read 3 byte from LBDATA0 R register without initiating a new transfer Read 2 byte from LBDATA0 register Read 1 byte from LBDATA0 register Dummy read byte from LBDATA0 register SPCLK Byte...
Page 840: Write-Read-Write Sequence On The Lcd Bus
Chapter 23 LCD Bus Interface (LCD-I/F) 23.3.5 Write-Read-Write sequence on the LCD bus Figure 23-8 shows an example when a write access to the LCD bus is immediately followed by a read access and vice versa. The example is given in mod80 mode (LBCTL0.IMD0 = 0) with byte transfers.
Page 841: Chapter 24 Sound Generator (Sg)
Chapter 24 Sound Generator (SG) The Sound Generator (SG0) generates an audio-frequency tone signal and a high-frequency pulse-width modulated (PWM) signal. The duty cycle of the PWM signal defines the volume. By default, the two signal components are routed to separate pins. But both signals can also be combined to generate a composite signal that can be used to drive a loudspeaker circuit.
Page 842: Description
Chapter 24 Sound Generator (SG) 24.1.1 Description The following figure provides a functional block diagram of the Sound Generator. SG0CLK = Clear Clear PCLK0 9-bit S0GFL 6-bit S0GFH 9-bit S0GFH (16MHz) tone counter frequency counter Tone (32 to 64 kHz) Match Match SG0CTL.PWR...
Page 843: Principle Of Operation
Sound Generator (SG) Chapter 24 24.1.2 Principle of operation The software-controlled registers SG0FL, SG0FH, and SG0PWM are equipped with hardware buffers. The Sound Generator operates on these buffers. This approach eliminates audible artifacts, because the buffers are only updated in synchronization with the generated tone waveform. Note This section provides an overview.
Page 844: Sound Generator Registers
Chapter 24 Sound Generator (SG) When the volume register SG0PWM is cleared, the sound stops immediately. 24.2 Sound Generator Registers The Sound Generator is controlled by means of the following registers: Table 24-1 Sound Generator registers overview Register name Shortcut Address SG0 frequency low register SG0FL...
Page 845 Sound Generator (SG) Chapter 24 SG0CTL - SG0 control register The 8-bit SG0CTL register controls the operation of the Sound Generator. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 7 Initial Value . This register is cleared by any reset. The “0”...
Page 846 Chapter 24 Sound Generator (SG) SG0FL - SG0 frequency low register The 16-bit SG0FL register is used to specify the target value for the PWM frequency. It holds the target value for the 9-bit counter SG0FL. Access This register is can be read/written in 16-bit units. It cannot be written if bit SG0CTL.PWR = 0.
Page 847 Sound Generator (SG) Chapter 24 SG0FH - SG0 frequency high register The 16-bit SG0FH register is used to specify the final tone frequency. It holds the target value for the 6-bit counter SG0FH. Access This register is can be read/written in 16-bit units. It cannot be written if bit SG0CTL.PWR = 0.
Page 848 Chapter 24 Sound Generator (SG) SG0PWM - SG0 volume register The 16-bit register SG0PWM is used to specify the sound volume. It holds the target value for the sound amplitude that is given by the duty cycle of the PWM signal.
Page 849: Sound Generator Operation
Sound Generator (SG) Chapter 24 24.3 Sound Generator Operation This section explains the details of the Sound Generator. 24.3.1 Generating the tone The tone signal is generated by the compare match signal of the SG0FH counter value with the value of the SG0FH buffer, followed by a by-two-divider. At each compare match, the counter is reset to zero.
Page 850: Generating The Volume Information
Chapter 24 Sound Generator (SG) Tone frequency calculation The tone frequency can be calculated as: / (([SG0FL buffer] + 1) × ([SG0FH buffer] + 1) × 2) tone SG0CLK where: = frequency of the SG0 input clock SG0CLK [SG0FL buffer] = contents of the SG0FL buffer [SG0FH buffer] = contents of the SG0FH buffer Example –...
Page 851 Sound Generator (SG) Chapter 24 Note To achieve 100 % duty cycle for all PWM frequencies, SGOFL must not be set to a value above 1FE The PWM signal is continually low when the value of the volume buffer is zero—the sound has stopped.
Page 852 Chapter 24 Sound Generator (SG) PWM calculations PWM frequency The PWM frequency is generated by the counter SG0FL. It can be calculated / (([SG0FL buffer] + 1) SG0CLK where: = frequency of the SG0 input clock SG0CLK [SG0FL buffer] = contents of the SG0FL buffer Duty cycle The duty cycle of the PWM signal is calculated as follows: •...
Page 853: Sound Generator Application Hints
Sound Generator (SG) Chapter 24 24.4 Sound Generator Application Hints This section provides supplementary programming information. 24.4.1 Initialization To enable the Sound Generator, set SG0CTL.PWR to 1. This connects the SG0 to the clock SG0CLK. Check bit SG0CTL.OS. When SG0CTL.OS is 0, the signal at pin SGO is a symmetrical square waveform with the frequency f .
Page 854 Chapter 24 Sound Generator (SG) Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 855: Chapter 25 Power Supply Scheme
Chapter 25 Power Supply Scheme The microcontroller has general power supply pins for its core, internal memory and peripherals. These pins are connected to internal voltage regulators. The microcontroller also has dedicated power supply pins for certain I/O modules. These pins provide the power for the I/O operations. 25.1 Overview The following table gives the naming convention of the pins: Table 25-1...
Page 856 Chapter 25 Power Supply Scheme The following pins belong to the Power Supply Scheme: Table 25-2 Power supply pins Connected to µPD70(F)3420, µPD70F3424, µPD70F3425, µPD70(F)3421, µPD70F3427 µPD70F3426 µPD70(F)3422, µPD70F3423 VDD50 / CPU core VSS50 Pin pair is connected to voltage regulator 0. REGC0 Capacitor for voltage regulator 0 for pin pair VDD50 / VSS50.
Page 857: Description
Power Supply Scheme Chapter 25 25.2 Description 25.2.1 Devices µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 Figure 25-1 gives an overview of the allocation of power supply pins of the µPD70(F)3420, µPD70(F)3421, µPD70(F)3422, µPD70F3423 devices. Their functional assignment is depicted in more detail in Figure 25-2. Note The diagrams do not show the exact pin location.
Page 858: Devices Μpd70F3424, Μpd70F3425, Μpd70F3426
Chapter 25 Power Supply Scheme 25.2.2 Devices µPD70F3424, µPD70F3425, µPD70F3426 Figure 25-3 gives an overview of the allocation of power supply pins of the µPD70F3424, µPD70F3425, µPD70F3426 devices. Their functional assignment is depicted in more detail in Figure 25-4. Note The diagrams do not show the exact pin location.
Page 859: Device Μpd70F3427
Power Supply Scheme Chapter 25 25.2.3 Device µPD70F3427 Figure 25-5 gives an overview of the allocation of power supply pins of the µPD70F3427 devices. Their functional assignment is depicted in more detail in Figure 25-6. Note The diagrams do not show the exact pin location. LCD Bus I/F I/O Ext.
Page 860: Voltage Regulators
Chapter 25 Power Supply Scheme 25.3 Voltage regulators The on-chip voltage regulators generate the voltages for the internal circuitry (CPU core, clock generation circuit and peripherals), refer to Figure 25-2, Figure 25-4 and Figure 25-6. The regulators operate per default in all operation modes (normal operation, HALT, IDLE, STOP, WATCH, Sub-WATCH, and during RESET).
Page 861: Chapter 26 Reset
Chapter 26 Reset Several system reset functions are provided in order to initialize hardware and registers. 26.1 Overview Features summary A reset can be caused by the following events: • External reset signal RESET Noise in the external reset signal is eliminated by an analog filter. •...
Page 862 Chapter 26 Reset All resets are applied asynchronously. That means, resets are not synchronized to any internal clock. This ensures that the microcontroller can be kept in reset state even if all internal clocks fail to operate. The reset function provides two internal reset signals: •...
Page 863 Reset Chapter 26 Hardware status With each reset function the hardware is initialized (including the watchdog). When the reset status is released, program execution is started. The following table describes the status of the clocks during reset and after reset release. Note that the clock status "operates" does not inevitably mean that any function using this clock source operates as well.
Page 864 Chapter 26 Reset Register status With each reset function the registers of the CPU, internal RAM, and on-chip peripheral I/Os are initialized. Since after reset the internal firmware is processed, some resources hold a different value as after reset, when the user’s program is started. After a reset, make sure to set the registers to the values needed within your program.
Page 865: Reset At Power-On
Reset Chapter 26 Note In the table above, “Undefined” means either undefined at the time of a power-on reset, or undefined due to data destruction when the falling edge of the external RESET signal corrupts an ongoing RAM write access. The internal RAM of the microcontroller comprises several separate RAM blocks.
Page 866: External Reset
Chapter 26 Reset 26.1.3 External RESET Reset is performed when a low level signal is applied to the RESET pin. The reset status is released when the signal applied to the RESET pin changes from low to high. After the external RESET is released, the RESSTAT register is cleared and the RESSTAT.RESEXT bit is set (RESSTAT = 02 , refer also to “RESSTAT - Reset source flag register“...
Page 867: Reset By Watchdog Timer
Reset Chapter 26 26.1.4 Reset by Watchdog Timer The Watchdog Timer can be configured to generate a reset if the watchdog time expires. After watchdog reset, the RESSTAT.RESWDT bit is set. The system reset signal SYSRES is generated. After Watchdog Timer overflow, the reset status lasts for a specific time. Then the reset status is automatically released.
Page 868 Chapter 26 Reset RESSTAT - Reset source flag register The 8-bit RESSTAT register contains information about which type of resets occurred since the last Power-On-Clear or external RESET or after the last software clear of the register. Each following reset condition sets the corresponding flag in the register. For example, if a Power-On-Clear reset is finished and then a Watchdog Timer reset occurs, the RESSTAT reads xxx1 0001 Access...
Page 869 Reset Chapter 26 • If the Power-On-Clear reset and external RESET has been released simultaneously: RESSTAT = 03 . That means RESSTAT indicate the occurrence of both reset events. All other reset events just set their respective bit in RESSTAT and do not change the others.
Page 870 Chapter 26 Reset Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 871: Chapter 27 Voltage Comparator
Chapter 27 Voltage Comparator The microcontroller has two instances of a Voltage Comparator. Note Throughout this chapter, the individual instances of the Voltage Comparator are identified by “n”, for example INTVCn for the generated interrupt signal. 27.1 Overview The Voltage Comparator compares an external voltage V at pin VCMPn CMPn and the internal reference voltage V...
Page 872: Description
Chapter 27 Voltage Comparator 27.1.1 Description Each Voltage Comparator consists of an operation amplifier and a logic block. The operation amplifier is connected to the external voltage (V ) with one CMPn input and to an internal reference voltage (V ) with the other.
Page 873: Voltage Comparator Registers
Voltage Comparator Chapter 27 27.2 Voltage Comparator Registers The Voltage Comparator is controlled by means of the following registers: Table 27-1 Voltage Comparator registers overview Register name Shortcut Address Voltage Comparator n control register VCCTLn <base> Voltage Comparator n status register VCSTRn <base>...
Page 874 Chapter 27 Voltage Comparator Caution If the voltage comparator input level V is below the reference voltage V CMPn an INTVCn interrupt is generated under both following conditions: → • The comparator is enabled (VCCTLn.VCEn = 0 1) and falling or both edges are specified (VCCTLn.VCEn = 00 or 11 →...
Page 875: Timing
Voltage Comparator Chapter 27 27.3 Timing The following figure shows the timing of the Voltage Comparator 0. In this example, the interrupt INTVCn is generated at the falling edge (VCCTLn.ESTn[1:0] = 00 ) of the comparator’s output signal. External voltage Internal reference voltage Time...
Page 876 Chapter 27 Voltage Comparator Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 877: Chapter 28 On-Chip Debug Unit
Chapter 28 On-Chip Debug Unit The microcontroller includes an on-chip debug unit. By connecting an N-Wire emulator, on-chip debugging can be executed. 28.1 Functional Outline 28.1.1 Debug functions Debug interface Communication with the host machine is established by using the DRST, DCK, DMS, DDI, and DDO signals via an N-Wire emulator.
Page 878 Each of the following signals can be masked. That means these signals will not be effective during debugging. The correspondence with the mask functions of the debugger (ID850NWC) for the N-Wire emulator (IE-V850E1-CD-NW) of NEC Electronics is shown below. – NMI0 mask function: NMI pin –...
Page 879: Security Function
On-Chip Debug Unit Chapter 28 28.1.2 Security function This microcontroller has a N-Wire security function, that demands the user to input an ID code upon start of the debugger. The ID code is compared to a predefined ID code, written in advance to the internal flash memory by an external flash programmer.
Page 880 Chapter 28 On-Chip Debug Unit Security disable The entire ID code, i.e. also the security bit 7 of address 0000 0079 , can be made temporarily ineffective by software. This is achieved by setting the control bit RSUDISC.DIS = 1. Setting RSUDISC.DIS = 1 does not change the security bit.
Page 881 On-Chip Debug Unit Chapter 28 RSUDISCP - RSUDISC write protection register The 8-bit RSUDISCP register protects the register RSUDISC from inadvertent write access. After data has been written to the RSUDISCP register, the first write access to register RSUDISC is valid. All subsequent write accesses are ignored. Thus, the value of RSUDISC can only be rewritten in a specified sequence, and illegal write access is inhibited.
Page 882: Controlling The N-Wire Interface
Chapter 28 On-Chip Debug Unit 28.2 Controlling the N-Wire Interface The N-Wire interface pins DRST, DDI, DDO, DCK, DMS are shared with port functions, see Table 28-2. During debugging the respective device pins are forced into the N-Wire interface mode and port functions are not available. Note that N-Wire debugging must be generally permitted by the security bit in the ID code region (*0x0000 0079[bit7] = 1) of the flash memory.
Page 883 On-Chip Debug Unit Chapter 28 External RESET External reset by the RESET pin sets OCDM.OCDM0 = 1, i.e. the pins are defined as N-Wire interface pins. If connected the debugger can communicate with the on-chip debug unit and take over CPU control. During and after RESET the pins P05, P52…P55 are configured as follows: •...
Page 884: N-Wire Enabling Methods
Chapter 28 On-Chip Debug Unit 28.3 N-Wire Enabling Methods 28.3.1 Starting normal operation after RESET and RESPOC For “normal operation” it has to be assured that the pins P05, P52…P55 are available as port pins after either reset event. Therefore the software has to perform OCDM.OCDM0 = 0 to make the pins available as port pins after RESET.
Page 885: N-Wire Activation By Reset Pin
On-Chip Debug Unit Chapter 28 RESET Application software “1” RESPOC sets OCDM.OCDM0=1 “0” OCDM0 Debugger starts PC = 0 XXXXXXXXXXXXXX P05/DRST reset normal operation Debug Figure 28-2 Start with N-Wire activation 28.3.3 N-Wire activation by RESET pin The N-Wire interface can also be activated after power up by keeping RESET active for at least 2 sec after RESPOC release.
Page 886: Connection To N-Wire Emulator
28.4.1 KEL connector KEL connector product names: • 8830E-026-170S (KEL): straight type • 8830E-026-170L (KEL): right-angle type Figure 28-4 Connection to N-Wire emulator (NEC Electronics IE-V850E1-CD-NW: N-Wire Card) Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 887 On-Chip Debug Unit Chapter 28 Pin configuration Figure 28-5 shows the pin configuration of the connector for emulator connection (target system side), and Table 28-3 on page 888 shows the pin functions. Figure 28-5 Pin configuration of connector for emulator connection (target system side) Caution Evaluate the dimensions of the connector when actually mounting the...
Page 888 Chapter 28 On-Chip Debug Unit Pin functions The following table shows the pin functions of the connector for emulator connection (target system side). “I/O” indicates the direction viewed from the device. Table 28-3 Pin functions of connector for emulator connection (target system side) Pin no.
Page 889 On-Chip Debug Unit Chapter 28 Example of recommended circuit An example of the recommended circuit of the connector for emulator connection (target system side) is shown below. V850E/Dx3 KEL connector 8830E-026-170S Note 3 (Reserved 1) (Reserved 2) (Reserved 3) (Reserved 4)
Page 890: Restrictions And Cautions On On-Chip Debug Function
Chapter 28 On-Chip Debug Unit 28.5 Restrictions and Cautions on On-Chip Debug Function • Do not mount a device that was used for debugging on a mass-produced product (this is because the flash memory was rewritten during debugging and the number of rewrites of the flash memory cannot be guaranteed). •...
Page 891: Appendix A Special Function Registers
Appendix A Special Function Registers The following tables list all registers that are accessed via the NPB (NEC peripheral bus). The registers are called “special function registers” (SFR). Table A-1 lists all CAN special function registers. The addresses are given as offsets to programmable peripheral base address (refer to “CAN module...
Page 892 Appendix A Special Function Registers Table A-1 CAN special function registers (2/3) Address offset Register name Shortcut 0x057 CAN0 Module Interrupt Enable register high byte C0IEH 0x058 CAN0 Module Interrupt Status register C0INTS 0x058 CAN0 Module Interrupt Status register low byte C0INTSL 0x05A CAN0 Module Bit-Rate Prescaler register...
Page 893 Special Function Registers Appendix A Table A-1 CAN special function registers (3/3) Address offset Register name Shortcut 0x656 CAN1 Module Interrupt Enable register low byte C1IEL 0x657 CAN1 Module Interrupt Enable register high byte C1IEH 0x658 CAN1 Module Interrupt Status register C1INTS 0x658 CAN1 Module Interrupt Status register low byte...
Page 894 Appendix A Special Function Registers A.2 Other Special Function Registers Table A-2 Other special function registers (1/17) Address Register name Shortcut 0xFFFFF060 CPU: Chip Area Select Control register 0 CSC0 0xFFFFF062 CPU: Chip Area Select Control register 1 CSC1 0xFFFFF064 CPU: Peripheral Area Select Control register 0xFFFFF066 CPU: Bus Size Configuration register...
Page 895 Special Function Registers Appendix A Table A-2 Other special function registers (2/17) Address Register name Shortcut 0xFFFFF102 Interrupt Mask register 1L IMR1L 0xFFFFF103 Interrupt Mask register 1H IMR1H 0xFFFFF104 Interrupt Mask register 2 IMR2 0xFFFFF104 Interrupt Mask register 2L IMR2L 0xFFFFF105 Interrupt Mask register 2H IMR2H...
Page 896 Appendix A Special Function Registers Table A-2 Other special function registers (3/17) Address Register name Shortcut 0xFFFFF146 Interrupt control register of INTTP2CC1 TP2CC1IC 0xFFFFF148 Interrupt control register of INTTP3OV TP3OVIC 0xFFFFF14A Interrupt control register of INTTP3CC0 TP3CC0IC 0xFFFFF14C Interrupt control register of INTTP3CC1 TP3CC1IC 0xFFFFF14E Interrupt control register of INTTG0OV0...
Page 897 Special Function Registers Appendix A Table A-2 Other special function registers (4/17) Address Register name Shortcut 0xFFFFF19E Interrupt control register of INTSW1 SW11IC 0xFFFFF1A0 Interrupt control register of INTP7 P7IC 0xFFFFF1A2 Interrupt control register of INTC1ERR C1ERRIC 0xFFFFF1A4 Interrupt control register of INTC1WUP C1WUPIC 0xFFFFF1A6 Interrupt control register of INTC1REC...
Page 898 Appendix A Special Function Registers Table A-2 Other special function registers (5/17) Address Register name Shortcut 0xFFFFF217 ADC result register high byte channel 3 ADCR0H3 0xFFFFF218 ADC result register channel 4 ADCR04 0xFFFFF219 ADC result register high byte channel 4 ADCR0H4 0xFFFFF21A ADC result register channel 5...
Page 899 Special Function Registers Appendix A Table A-2 Other special function registers (6/17) Address Register name Shortcut 0xFFFFF354 Port LCD control register port 10 PLCDC10 0xFFFFF360 Port open drain control register P0 PODC0 0xFFFFF362 Port open drain control register P1 PODC1 0xFFFFF364 Port open drain control register P2 PODC2...
Page 900 Appendix A Special Function Registers Table A-2 Other special function registers (7/17) Address Register name Shortcut 0xFFFFF400 Port register port 0 0xFFFFF402 Port register port 1 0xFFFFF404 Port register port 2 0xFFFFF406 Port register port 3 0xFFFFF408 Port register port 4 0xFFFFF40A Port register port 5 0xFFFFF40C...
Page 901 Special Function Registers Appendix A Table A-2 Other special function registers (8/17) Address Register name Shortcut 0xFFFFF458 Port mode control register port 12 PMC12 0xFFFFF45A Port mode control register port 13 PMC13 0xFFFFF466 Port function control register port 3 PFC3 0xFFFFF46A Port function control register port 5 PFC5...
Page 902 Appendix A Special Function Registers Table A-2 Other special function registers (9/17) Address Register name Shortcut 0xFFFFF5C8 Compare register 40 MCMP040 0xFFFFF5C9 Compare register 41 MCMP041 0xFFFFF5CA Compare Control register 1 MCMPC01 0xFFFFF5CC Compare Control register 2 MCMPC02 0xFFFFF5CE Compare Control register 3 MCMPC03 0xFFFFF5D0 Compare Control register 4...
Page 903 Special Function Registers Appendix A Table A-2 Other special function registers (10/17) Address Register name Shortcut 0xFFFFF628 TMZ5 Synchronized counter read register TZ5CNT0 0xFFFFF62A TMZ5 non-synchronized counter read register TZ5CNT1 0xFFFFF62C TMZ5 counter reload register TZ5R 0xFFFFF62E TMZ5 control register TZ5CTL 0xFFFFF630 TMZ6 Synchronized counter read register...
Page 904 Appendix A Special Function Registers Table A-2 Other special function registers (11/17) Address Register name Shortcut 0xFFFFF683 TMP2 timer-specific I/O control register 1 TP2IOC1 0xFFFFF684 TMP2 timer-specific I/O control register 2 TP2IOC2 0xFFFFF685 TMP2 option register TP2OPT0 0xFFFFF686 TMP2 capture/compare register 0 TP2CCR0 0xFFFFF688 TMP2 capture/compare register 1...
Page 905 Special Function Registers Appendix A Table A-2 Other special function registers (12/17) Address Register name Shortcut 0xFFFFF6C5 Output control register TMG 1 high byte OCTLG1H 0xFFFFF6C6 Time base status TMG 1 TMGST1 0xFFFFF6C8 Timer count register 0 TMG 1 TMG10 0xFFFFF6CA Timer count register 1 TMG 1 TMG11...
Page 906 Appendix A Special Function Registers Table A-2 Other special function registers (13/17) Address Register name Shortcut 0xFFFFF800 Protection register PHCMD 0xFFFFF802 Peripheral status 0xFFFFF820 Power Save Mode 0xFFFFF822 Clock Control 0xFFFFF824 Clock Generator Status CGSTAT 0xFFFFF826 Watch Dog Clock Control 0xFFFFF828 Processor Clock Control 0xFFFFF82A...
Page 907 Special Function Registers Appendix A Table A-2 Other special function registers (14/17) Address Register name Shortcut 0xFFFFF880 VFB flash/ROM correction control register CORCN 0xFFFFF8A0 VSB flash correction address register 0 COR2AD0 0xFFFFF8A0 VSB flash correction address register 0L COR2AD0L 0xFFFFF8A2 VSB flash correction address register 0H COR2AD0H 0xFFFFF8A4...
Page 908 Appendix A Special Function Registers Table A-2 Other special function registers (15/17) Address Register name Shortcut 0xFFFFFB01 LCD display mode control LCDM0 0xFFFFFB20 LCD RAM data SEGREG000 0xFFFFFB20 LCD RAM data SEGREG020 0xFFFFFB21 LCD RAM data SEGREG001 0xFFFFFB21 LCD RAM data SEGREG021 0xFFFFFB22 LCD RAM data...
Page 909 Special Function Registers Appendix A Table A-2 Other special function registers (16/17) Address Register name Shortcut 0xFFFFFB60 LCD Bus Interface Control LBCTL0 0xFFFFFB61 LCD Bus Interface Cycle Time LBCYC0 0xFFFFFB62 LCD Bus Interface Wait States LBWST0 0xFFFFFB70 LCD Bus Interface Data LBDATA0W 0xFFFFFB70 LCD Bus Interface Data...
Page 910 Appendix A Special Function Registers Table A-2 Other special function registers (17/17) Address Register name Shortcut 0xFFFFFD83 IIC0 Slave address register SVA0 0xFFFFFD84 IIC0 combined IICCL0 and IICX0 register IICCL0IICX0 0xFFFFFD84 IIC0 clock selection register IICCL0 0xFFFFFD85 IIC0 function expansion register IICX0 0xFFFFFD86 IIC0 state register...
Page 911: Appendix B Registers Access Times
Appendix B Registers Access Times This chapter provides formulas to calculate the access time to registers, which are accessed via the peripheral I/O areas. All accesses to the peripheral I/O areas are passed over to the NPB bus via the VSB - NPB bus bridge BBR. Read and write access times to registers via the NPB depend on the register, the system clock VBCLK and the setting of the VSWC register.
Page 912 Appendix B Registers Access Times B.1 Timer P Register TPnCCR0, TPnCCR1 Access ⎧ ⎫ VBCLK ⋅ ⋅ ------------------------------------------------------ - ----------------- - SUWL VSWL VSWL Formula ⎨ ⎬ ⋅ VSWL ⎩ ⎭ PCLK0 VBCLK Access ⋅ ⎧ ⎫ VBCLK ⋅ ⋅ ------------------------------------------------------ - ----------------- - SUWL...
Page 913 Registers Access Times Appendix B B.2 Timer Z Register TZnCNT0 Access ⋅ ⋅ ----------------- - ----------------- - SUWL 3 VSWL Formular VBCLK PCLK2 Register TZnCNT1 Access ⋅ ----------------- - SUWL VSWL Formular VBCLK Register TZnR Access ⋅ ----------------- - SUWL VSWL Formular VBCLK...
Page 914 Appendix B Registers Access Times B.3 Timer G Register TMGn0, TMGn1 Access ⎧ ⎫ VBCLK ⋅ ⋅ --------------------------------------------------------- - ----------------- - SUWL VSWL VSWL Formular ⎨ ⎬ ⋅ VSWL ⎩ ⎭ SPCLK0 VBCLK Access W (no write access during timer operation) ⋅...
Page 915 Registers Access Times Appendix B B.4 Watch Timer Register WTnCNT1 Access ⋅ ----------------- - SUWL VSWL Formular VBCLK Register WTnR Access ⋅ ----------------- - SUWL VSWL Formular VBCLK Access ⋅ ⋅ ----------------- - SUWL 3 VSWL Formular VBCLK Register CR00 Access Read-Modify-Write ⋅...
Page 916 Appendix B Registers Access Times B.6 Watchdog Timer Register Access ⋅ ----------------- - SUWL VSWL Formular VBCLK B.7 Asynchronous Serial Interface (UARTA) Register Access ⋅ ----------------- - SUWL VSWL Formular VBCLK B.8 Clocked Serial Interface (CSIB) Register Access ⋅ SUWL VSWL ----------------- - Formular...
Page 917 Registers Access Times Appendix B B.10 CAN Controller Register CnMDATA[7:0]m Access ⋅ ⎧ ⎫ VBCLK ⋅ ⋅ ------------------------------------------------------ - ----------------- - SUWL VSWL VSWL Formular ⎨ ⎬ ⋅ VSWL ⎩ ⎭ PCLK0 VBCLK Access 8-bit Write ⋅ ⎧ ⎫ VBCLK ⋅...
Page 918 Appendix B Registers Access Times B.12 Stepper Motor Controller/Driver Register MCNTCn[1:0], MCMPCnk Access ⋅ ----------------- - SUWL VSWL Formular VBCLK Access ⋅ ⎧ ⎫ VBCLK ⋅ ⋅ --------------------------------------------------------- - ----------------- - SUWL VSWL VSWL Formular ⎨ ⎬ ⋅ VSWL ⎩ ⎭...
Page 919 Registers Access Times Appendix B B.15 Sound Generator Register SG0FL, SG0FH, SG0PWM Access ⋅ ----------------- - SUWL VSWL Formular VBCLK Access ⋅ ⋅ ----------------- - ----------------- - SUWL 3 VSWL Formular VBCLK PCLK0 Register all other Access ⋅ ----------------- - SUWL VSWL Formular...
Page 920 Appendix B Registers Access Times Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 921: Revision History
Revision History This revision list shows all functional changes of this document U17566EE1V2UM00 compared to the 2nd edition of previous manual version 1.0 U17566EE1V1UM00 (date published 16/05/06). Chapter Page Description 3 Timer G specified for all devices ordering information added section concerning external memory interface of µPD70F3427 added TOP01 to TOP31 Timer P outputs also available on ports P34 to P37 size and address of VSB RAM corrected...
Page 922 Revision History Preliminary User’s Manual U17566EE1V2UM00 Downloaded from Elcodis.com electronic components distributor...
Page 923: Index
Index ister (ASC) 273 Diagnosis functions 733 Address space 115 Functions 654 Numerics CPU 115 Initialization 711 Images 115 Internal registers 666 16-bit data busses Physical 115 Interrupt function 732 Access to 302 ADIC 210 Message Reception 714 8-bit data busses Analog filtered inputs 93 Message Access to 296...
Page 924 Index register (CnIE) 690 Clock Generator status register Control registers for peripheral (CGSTAT) 139 clocks 150 CANn module interrupt status register (CnINTS) 691 Clock monitors 132 COR2ADn 337 CANn module last error infor- Operation 185 COR2CN 335 mation register Registers 163 CORADn 336 (CnLEC) 687 Clock output FOUTCLK 184...
Page 925 Index DBCn 316 DMAnIC 210 with flash programmer 238 DBPC 108 DRST 320 FOUTCLK control register DBPSW 111 DSAHn 312 (FCC) 155 DCHCn 319 DSALn 313 DTFRn 321 DDAHn 314 DDALn 315 Duty factor (pulse width GCCn0 447 modulation) 804 Debug Function (on-chip) GCCn5 447 DWCn 274...
Page 926 Index (ICC) 156 IMRn 214 Link pointer 106 IIC clock select registers Interrupt/exception source reg- Local bus size configuration (IICCLn) 588 ister (ECR) 112 register (LBS) 272 IIC control registers Interval measurement (IICCn) 579 By restarting the Main oscillator clock monitor IIC division clock select regis- counter 495 register (CLMM) 163...
Page 927 Index OCTLGn 445 Pn 46 Prescaler compare registers (PRSCMn) 572 OCTLGnH 445 PnIC 210 Prescaler mode registers OCTLGnL 445 POC (Power-On Clear) 865 (PRSMn) 571 On-chip debug mode register PODCn 49 PRM0 490 (OCDM) 45 Port drive strength control regis- Processor clock control register Operation modes 114 ter (PDSCn) 48...
Page 928 Index ROM correction address regis- Software exception 220 TGnCCmIC 210 ters Sound Generator 841 TGnOV0IC 210 COR2ADn 337 Application hints 853 TGnOV1IC 210 CORADn 336 Operation 849 Time base status register ROM correction control regis- (TMGSTn) 446 Registers 844 ters Timer G 437 SPCLK control register COR2CN 335...
Page 929 Index mode 420 TPnIOC1 350 Registers 873 PWM output mode 394 TPnIOC2 351 Voltage Comparator n control register (VCCTLn) 873 Timer output TPnOPT0 352 operations 426 Voltage Comparator n status TPnOVIC 210 register (VCSTRn) 874 TM0 492 TZnCNT0 433 Voltage regulators 860 TM01IC 210 TZnCNT1 433 VSWC 263...
Page 930 Index WDTM 504 WPHS 506 Write protected registers 124 WT (Watch Timer) 477 WT0 (Watch Timer 0) 477 WT1 (Watch Timer 1) 477 WTn non-synchronized counter read register (WTnCNT1) 483 WTn synchronized counter reg- ister (WTnCNT0) 483 WTn timer control register (WTnCTL) 482 WTnCNT0 483 WTnCNT1 483...

NEC V850E/Dx3 Preliminary User's Manual

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 CPU System Functions

Chapter 4 Clock Generator

Chapter 5 Interrupt Controller (INTC)

Chapter 6 Flash Memory

Chapter 7 Bus and Memory Control (BCU, MEMC)

Chapter 8 DMA Controller (DMAC)

Chapter 9 ROM Correction Function (ROMC)

Chapter 10 Code Protection and Security

Chapter 11 16-Bit Timer/Event Counter P (TMP)

Chapter 12 16-Bit Interval Timer Z (TMZ)

Chapter 13 16-Bit Multi-Purpose Timer G (TMG)

Chapter 14 Watch Timer (WT)

Chapter 15 Watchdog Timer (WDT)

Chapter 16 Asynchronous Serial Interface (UARTA)

Chapter 17 Clocked Serial Interface (CSIB)

Chapter 18 I 2 C Bus (IIC)

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