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PD750008
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NEC PD750008 manual available for free PDF download: User Manual
NEC PD750008 User Manual (342 pages)
4 BIT SINGLE-CHIP MICROCOMPUTER
Brand:
NEC
| Category:
Computer Hardware
| Size: 1.22 MB
Table of Contents
Table of Contents
9
Chapter 1 General
21
Features of the Products
21
Function Overview
22
Ordering Information
23
Differences Among Subseries Products
24
Block Diagram
25
Pin Configuration (Top View)
26
Chapter 2 Pin Functions
29
PIN FUNCTIONS of the Μpd750008
29
Digital I/O Port Pins
29
Non-Port Pin Functions
31
Pin Functions
32
P00-P03 (Port0)
32
P10-P13 (Port1)
32
P20-P23 (Port2)
33
P30-P33 (Port3)
33
P40-P43 (Port4), P50-P53 (Port5)
33
P60-P63 (Port6), P70-P73 (Port7)
33
P80, P81 (Port8)
33
Pto0, Pto1
33
Ti0
33
Buz
34
Int0, Int1
34
Int4
34
Pcl
34
Sck, So/Sb0, Si/Sb1
34
Int2
35
Kr0-Kr3
35
Kr4-Kr7
35
X1, X2
35
Reset
36
VDD
36
Vss
36
Xt1, Xt2
36
IC (for the Μpd750004, Μpd750006, and Μpd750008 Only)
37
MD0-MD3 (for the Μpd75P0016 Only)
37
VPP (for the Μpd75P0016 Only)
37
Pin Input/Output Circuits
38
Connection of Unused Pins
40
Chapter 3 Features of the Architecture and Memory Map
41
Data Memory Bank Structure and Addressing Modes
41
Data Memory Bank Structure
41
Data Memory Addressing Modes
43
Data Memory Organization and Addressing Range of each Addressing Mode
44
Addressing Modes
45
Updating Static RAM Addresses
48
General Register Bank Configuration
54
Register Bank to be Selected with the RBE and RBS
54
Recommended Use of Register Banks with Normal Routines and Interrupt Routines
54
Example of Register Bank Selection
55
General Register Configuration (4-Bit Processing)
57
General Register Configuration (8-Bit Processing)
58
Memory-Mapped I/O
59
Addressing Modes Applicable to Peripheral Hardware Operation
59
Μpd750008 I/O Map
60
Chapter 3 Features of the Architecture and Memory Map
63
Chapter 4 Internal Cpu Functions
65
Mk I Mode/Mk II MODE SWITCH FUNCTIONS
65
Differences between Mk I Mode and Mk II Mode
65
Setting of the Stack Bank Selection Register (SBS)
66
Stack Bank Selection Register Format
66
Program Counter (Pc)
67
Program Counter Organization
67
Program Memory (Rom)
68
Program Memory Map (in Μpd750004)
69
Program Memory Map (in Μpd750006)
70
Program Memory Map (in Μpd750008)
71
Program Memory Map (in Μpd75P0016)
72
Data Memory (Ram)
73
Data Memory Configuration
73
Specification of a Data Memory Bank
74
Data Memory Map
74
General Register
76
General Register Format
76
Register Pair Format
77
Accumulator
77
Stack Pointer (Sp) and Stack Bank Select Register (Sbs)
78
Stack Area to be Selected by the SBS
78
Format of Stack Pointer and Stack Bank Select Register
79
Data Saved to the Stack Memory (Mk I Mode)
79
Data Restored from the Stack Memory (Mk I Mode)
80
Data Saved to the Stack Memory (Mk II Mode)
80
Data Restored from the Stack Memory (Mk II Mode)
81
Program Status Word (Psw)
82
PSW Flags Saved/Restored in Stack Operation
82
Carry Flag Manipulation Instructions
83
Information Indicated by the Interrupt Status Flag
84
Bank Select Register (Bs)
85
Bank Select Register Format
85
Register Bank to be Selected with the RBE and RBS
86
Chapter 5 Peripheral Hardware Functions
87
Digital I/O Ports
87
Data Memory Addresses of Digital Ports
87
Types, Features, and Configurations of Digital I/O Ports
88
Types and Features of Digital Ports
88
Configurations of Ports 0 and 1
89
Configurations of Ports 2 and 7
90
Configurations of Ports 3N and 6N (N = 0 to 3)
91
Configurations of Ports 4 and 5
92
Configuration of Port 8
93
I/O Mode Setting
94
Formats of Port Mode Registers
95
Digital I/O Port Manipulation Instructions
96
I/O Pin Manipulation Instructions
98
Digital I/O Port Operation
99
Operations by I/O Port Manipulation Instructions
100
Specification of Bilt-In Pull-Up Resistors
101
Specification of Built-In Pull-Up Resistors
101
I/O Timing of Digital I/O Ports
102
Pull-Up Resistor Specification Register Format
102
I/O Timing Chart of Digital I/O Ports
102
ON Timing Chart of Built-In Pull-Up Resistor Connected by Software
103
Clock Generator
104
Block Diagram of the Clock Generator
104
Clock Generator Configuration
104
Functions and Operations of the Clock Generator
105
Format of the Processor Clock Control Register
107
Format of the System Clock Control Register
108
External Circuit for the Main System Clock Oscillator
109
External Circuit for the Subsystem Clock Oscillator
109
Examples of Oscillator Connections Which Should be Avoided
110
Subsystem Clock Oscillator
112
Sub-Oscillator Control Register (SOS) Format
113
System Clock and CPU Clock Setting
114
Maximum Time Required to Change the System Clock and CPU Clock
114
Changing the System Clock and CPU Clock
115
Clock Output Circuit
116
Configuration of the Clock Output Circuit
116
Format of the Clock Output Mode Register
117
Application to Remote Control Output
118
Basic Interval Timer/Watchdog Timer
119
Basic Interval Timer Mode Register (BTM)
119
Block Diagram of the Basic Interval Timer/Watchdog Timer
119
Configuration of the Basic Interval Timer/Watchdog Timer
119
Format of the Basic Interval Timer Mode Register
120
Watchdog Timer Enable Flag (WDTM)
121
Operation of the Basic Interval Timer
121
Format of the Watchdog Timer Enable Flag (WDTM)
121
Operation of the Watchdog Timer
122
Other Functions
123
Clock Timer
125
Clock Mode Register
126
Configuration of the Clock Timer
126
Block Diagram of the Clock Timer
126
Clock Mode Register Format
127
Timer/Event Counter
128
Configuration of Timer/Event Counter
128
Timer/Event Counter Mode Register (Channel 0) Format
132
Timer Counter Mode Register (Channel 1) Format
133
8-Bit Timer/Event Counter Mode Operation
134
Timer/Event Counter Output Enable Flag Format
134
Timer/Event Counter Mode Register Setup
135
Timer/Event Counter Output Enable Flag Setup
136
Resolution and Longest Setup Time
137
Configuration of Timer/Event Counter
138
Count Operation Timing
139
Notes on Timer/Event Counter Applications
140
Error at the Start of the Timer
140
Serial Interface
143
Serial Interface Functions
143
Configuration of Serial Interface
144
Example of the SBI System Configuration
144
Block Diagram of the Serial Interface
144
Register Functions
147
Format of Serial Operation Mode Register (CSIM)
147
Format of Serial Bus Interface Control Register (SBIC)
151
Peripheral Hardware of Shift Register
154
Operation Halt Mode
155
Three-Wire Serial I/O Mode Operations
157
Example of Three-Wire Serial I/O System Configuration
157
Timing of Three-Wire Serial I/O Mode
160
Serial Clock Selection and Application (in the Three-Wire Serial I/O Mode)
160
Operations of RELT and CMDT
161
Transfer Bit Switching Circuit
161
Two-Wire Serial I/O Mode
164
Example of Two-Wire Serial I/O System Configuration
164
Timing of Two-Wire Serial I/O Mode
167
Serial Clock Selection and Application (in the Two-Wire Serial I/O Mode)
168
Operations of RELT and CMDT
168
SBI Mode Operation
170
Example of SBI System Configuration
170
Timing of SBI Transfer
172
Bus Release Signal
173
Command Signal
173
Address
173
Slave Selection Using an Address
174
Command
174
Data
174
Acknowledge Signal
175
Busy and Ready Signals
176
Serial Clock Selection and Application (in the SBI Mode)
180
Operations of RELT, CMDT, RELD, and CMDD (Slave)
181
Operation of ACKT
182
Operation of ACKE
182
Operation of ACKD
183
Operation of BSYE
184
Pin Configuration
187
Example of Serial Bus Configuration
194
Transfer Format of the READ Command
195
Transfer Format of the WRITE and END Commands
196
Transfer Format of the STOP Command
196
Transfer Format of the STATUS Command
197
Status Format of the STATUS Command
197
Transfer Format of the RESET Command
198
Transfer Format of the CHGMST Command
198
Manipulation of SCK Pin Output
199
Master and Slave Operation in Case of Error
199
SCK/P01 Pin Circuit Configuration
200
Bit Sequential Buffer
201
Format of the Bit Sequential Buffer
201
Chapter 6 Interrupt and Test Functions
203
Configuration of the Interrupt Control Circuit
203
Types of Interrupt Sources and Vector Tables
205
Interrupt Vector Table
205
Interrupt Sources
205
Various Devices to Control Interrupt Functions
207
Set Signals for Interrupt Request Flags
208
Interrupt Priority Specification Register
209
Configurations of the INT0, INT1, and INT4 Circuits
211
I/O Timing of a Noise Eliminator
212
Format of Edge Detection Mode Registers
213
Interrupt Processing Statuses of IST0 and IST1
214
Interrupt Sequence
215
Multiple Interrupt Processing Control
216
Multiple Interrupt Processing by a High-Order Interrupt
216
Multiple Interrupt Processing by Changing the Interrupt Status Flags
217
Processing of Interrupts Sharing a Vector Address
218
Identifying Interrupt Sharing Vector Table Address
218
Machine Cycles for Starting Interrupt Processing
220
Effective Use of Interrupts
222
Interrupt Applications
222
Test Function
230
Hardware to Control Test Functions
230
Test Sources
230
Signals Setting Test Request Flags
230
Format of INT2 Edge Detection Mode Register (IM2)
233
Chapter 7 Standby Function
235
Setting of Standby Modes and Operation Status
236
Operation Statuses in the Standby Mode
236
Release of the Standby Modes
237
Standby Mode Release Operation
238
Operation after a Standby Mode Is Released
239
Wait Time When the STOP Mode Is Released
239
Selection of a Wait Time with BTM
239
Applications of the Standby Modes
240
Selection of a Mask Option
240
Chapter 8 Reset Function
245
Configuration of Reset Functions
245
Reset Operation by Generation of RESET Signal
245
Status of the Hardware after a Reset
246
Chapter 9 Writing to and Verifying Program Memory (Prom)
249
Operating Modes When Writing to and Verifying the Program Memory
250
Writing to the Program Memory
250
Reading the Program Memory
252
Screening of One-Time Prom
253
Chapter 10 Mask Option
255
Pin
255
Mask Option of Standby Function
255
Selecting Mask Option of Pin
255
Mask Option for Feedback Resistor of Subsystem Clock
256
Chapter 11 Instruction Set
257
Unique Instructions
257
GETI Instruction
257
Bit Manipulation Instructions
258
String-Effect Instructions
258
Number System Conversion Instructions
259
Skip Instructions and the Number of Machine Cycles Required for a Skip
260
Instruction Set and Operation
261
Instruction Codes of each Instruction
278
Functions and Applications of the Instructions
284
Transfer Instructions
284
Table Reference Instructions
290
Bit Transfer Instructions
293
Arithmetic/Logical Instructions
293
Accumulator Manipulation Instructions
299
Increment/Decrement Instructions
299
Compare Instructions
300
Carry Flag Manipulation Instructions
301
Memory Bit Manipulation Instructions
302
Branch Instructions
304
Subroutine Stack Control Instructions
309
Interrupt Control Instructions
313
I/O Instructions
314
CPU Control Instructions
315
Special Instructions
315
APPENDIX Afunctions of the Μpd75008, Μpd750008, and Μpd75P0016
319
Appendix Bdevelopment Tools
321
B-1 Drawings of the EV-9200G-44 (Reference)
326
B-2 Recommended Pattern on Boards for the EV-9200G-44 (Reference)
327
Appendix Cmasked Rom Ordering Procedure
329
Appendix Dinstruction Index
331
Instruction Index (by Function)
331
Instruction Index (Alphabetical Order)
334
Appendix E Hardware Index
337
Hardware Index
337
Hardware Name)
337
E.1 Hardware Index (Alphabetical Order with Respect to the Hardware Name)
337
Hardware Index
339
E.2 Hardware Index (Alphabetical Order with Respect to the Hardware Symbol)
339
Appendix F Revision History
341
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