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NEC PD75P402 Computer Hardware Manuals
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NEC PD75P402 Computer Hardware manual available for free PDF download: User Manual
NEC PD75P402 User Manual (195 pages)
4-BIT SINGLE-CHIP MICROCOMPUTER
Brand:
NEC
| Category:
Computer Hardware
| Size: 0.9 MB
Table of Contents
Table of Contents
6
Title
10
Chapter 1. General
12
Outline of Functions
13
Ordering Information and Quality Grade
14
Differences between Pd75402A and Pd75402, 75P402
15
Block Diagram
16
Pin Configuration
17
28-Pin Plastic DIP (600 Mil), Shrink DIP (400 Mil)
17
44-Pin Plastic QFP ( 10Mm)
19
Chapter 2. Pin Functions
21
Pd75402A Pin Function List
22
Port Pin List
22
List of Pins Other than Port Pins
23
Normal Operating Mode
24
P00 to P03 (Port 0), P10, P12 (Port 1)
24
Port 0'S, 1'S Dual-Function Pins
24
P20 to P23 (Port 2), P30 to P33 (Port 3), P50 to P53 (Port 5), P60 to P63 (Port 6)
25
Sck, So/Sb0, si
25
Int0
25
Int2
25
Pcl
25
X1, X2
26
RESET (Reset)
26
VDD
26
Vss
26
Prom Mode
27
A0 to A14 (Address)
27
CE (Chip Enable)
27
O0 to O7 (Data)
27
OE (Output Enable)
27
VDD
27
Vpp
27
Vss
27
Pin Input/Output Circuits
28
Pin Input/Output Types
28
Unused Pin Treatment
31
Notes on Use of P00 Pin and Reset Pin
31
Chapter 3. Features of Architecture and Memory Map
32
Data Memory Bank Configuration and Addressing Modes
32
Data Memory Bank Configuration
32
Data Memory Configuration and Address Range in each Addressing Mode
33
Addressing Mode List
34
Data Memory Addressing Modes
35
Static RAM Address Updating Method
36
Memory-Mapped I/O
39
Applicable Addressing Modes at Peripheral Hardware Operation
39
PD75402A I/O Map
40
Chapter 4. Internal Cpu Functions
42
Program Counter (Pc)
42
Program Counter Configuration
42
Program Memory (Rom)
43
Program Memory Map
43
Data Memory (Ram)
44
Data Memory Map
44
General Register
46
General Register Configuration
46
Register Pair Configuration
46
Accumulator
47
Accumulators
47
Stack Pointer (Sp)
48
Stack Pointer Configuration
48
Data Restored from Stack Memory
49
Program Status Word (Psw)
50
Data Saved to Stack Memory
49
Carry Flag Manipulation Instructions
50
Program Status Word Configuration
50
Interrupt Status Flag Indication Content
51
Chapter 5. Peripheral Hardware Functions
52
Digital Input/Output Ports
52
Digital Input/Output Port Data Memory Addresses
52
Digital Input/Output Port Types, Characteristics and Configuration
53
Digital Input/Output Port Types and Characteristics
53
Configuration of Ports 0 and 1
54
Configuration of Port 3
55
Configuration of Ports 2 and 6
56
Input/Output Mode Setting
57
Configuration of Port 5
57
Digital Input/Output Port Handling Instructions
58
Format of Port Mode Registers
58
List of Input/Output Pin Handling Instructions
59
Digital Input/Output Port Operations
60
Operations with Input/Output Port Handling Instructions
61
Internal Pull-Up Resistors
62
Internal Pull-Up Resister Specification for each Port
62
Format of Pull-Up Resistor Specification Register
63
Pull-Up Resistor Incorporation Switching Timing
63
Digital Input/Output Port Input/Output Timing
64
Clock Generation Circuit
65
Clock Generation Circuit Block Diagram
65
Clock Generation Circuit Function and Operation
66
Clock Generation Circuit Configuration
65
Processor Clock Control Register Format
67
Example of Poor Resonator Connection Circuit
68
CPU Clock Setting
70
System Clock Oscillation Circuit External Circuitry
68
Use of Variable Minimum Instruction Execution Time Function
70
Change of after Power-On Reset
71
Maximum Time Required for Change of CPU Clock
71
Differences between PD75402A and PD75402
72
Clock Generation Circuit - Differences between PD75402A and PD75402
72
PD75402 Processor Clock Control Register Format
73
Clock Output Circuit
74
Clock Output Circuit Configuration
74
Clock Output Mode Register (CLOM)
75
Clock Output Mode Register Format
75
Clock Output Procedure
76
Example of Remote Control Application
76
Basic Interval Timer
77
Basic Interval Timer Configuration
77
Basic Interval Timer Mode Register (BTM)
78
Basic Interval Timer Mode Register Format
78
Basic Interval Timer Operation
79
Examples of Basic Interval Timer Applications
80
Serial Interface
81
Serial Interface Functions
81
Example of SBI System Configuration
82
Serial Interface Configuration
82
Serial Interface Block Diagram
83
Register Functions
85
Serial Operating Mode Register (CSIM) Format
86
Serial Bus Interface Control Register (SBIC) Format
89
Configuration Around Shift Register
92
Operation-Halt Mode
94
3-Wire Serial I/O Mode Operation
95
Example of 3-Wire Serial I/O System Configuration
95
3-Wire Serial I/O Mode Timing
99
RELT & CMDT Operation
100
Serial Clock Selection and Use (in 3-Wire Serial I/O Mode)
100
Shift Register (SIO) and Internal Bus Configuration
101
SBI Mode Operation
104
Example of SBI Serial Bus System Configuration
104
SBI Transfer Timing
106
Bus Release Signal
107
Command Signal
107
Address
108
Slave Selection by Address
108
Command
109
Data
109
Acknowledge Signal
110
Busy Signal & Ready Signal
111
Serial Clock Selection and Use (in SBI Mode)
116
RELT, CMDT, RELD & CMDD Operation (Master)
117
RELT, CMDT, RELD & CMDD Operation (Slave)
117
ACKT Operation
118
ACKE Operation
119
ACKD Operation
120
BSYE Operation
120
Signals in SBI Mode
121
Pin Configuration Diagram
123
Address Transmission from Master Device to Slave Device (WUP = 1)
125
Command Transmission from Master Device to Slave Device
126
Data Transmission from Master Device to Slave Device
127
Data Transmission from Slave Device to Master Device
128
Example of Serial Bus Configuration
130
READ Command Transfer Format
132
WRITE & END Command Transfer Format
132
STOP Command Transfer Format
133
STATUS Command Status Format
134
STATUS Command Transfer Format
134
CHGMST Command Transfer Format
135
RESET Command Transfer Format
135
Master and Slave Operations after an Error
136
Chapter 6. Interrupt Functions
137
Interrupt Control Circuit Configuration
137
Interrupt Control Circuit Block Diagram
138
Interrupt Source Types and Vector Table
139
Interrupt Request Source Types
139
6.3 Interrupt Control Circuit Hardware
140
Interrupt Vector Table
139
Interrupt Request Flag Setting Signal
140
Configuration of INT0 and INT2
141
INT0 Noise Elimination Circuit Input/Output Timing
142
INT2 Input Noise Elimination
142
Edge Detection Mode Register Format
143
IME Format
143
IST0 Interrupt Servicing Status
144
Interrupt Sequence
145
Interrupt Servicing Procedure
145
Machine Cycles before Interrupt Servicing
146
Interrupt Applications
148
Chapter 7. Standby Function
152
Standby Mode Setting and Operation States
153
Standby Mode Operation States
153
Standby Mode Reset
154
Standby Mode Reset Operation
155
Operation after Standby Mode Reset
156
Standby Mode Application
156
Chapter 8. Reset Function
157
Reset Signal Acceptance
157
Reset at Power-On
157
State of Hardware after Reset
158
Chapter 9. Instruction Set
159
Special Instruction
160
Bit Operation Instructions
160
Stack Instructions
160
Base Correction Instructions
161
Skip Instruction and Number of Machine Cycles Required by Skip
161
Instruction Set and Its Operation
162
Operation Code of each Instruction
167
Instruction Functions and Application
170
Move Instructions
170
Table Reference Instructions
173
Arithmetic and Logic Instructions
174
Accumulator Operation Instructions
176
Increment/Decrement Instructions
177
Compare Instructions
178
Carry Flag Operation Instructions
179
Bit Manipulation Instructions
180
Branch Instructions
182
9.4.10 Subroutine Stack Control Instructions
183
9.4.11 Interrupt Control Instructions
185
9.4.12 Input/Output Instructions
186
9.4.13 CPU Control Instructions
187
Appendix A. Table of Instruction Usable with Evakit-75X Only
188
Appendix B. Development Tools
190
Appendix C. Mask Rom Ordering Procedure
193
Appendix D. Instruction Index (Alphabetic Order)
194
Appendix E. Hardware Index (Alphabetic Order)
195
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