NEC V850 Series 32-bit RISC CPU Manuals

Manuals and User Guides for NEC V850 Series 32-bit RISC CPU. We have 1 NEC V850 Series 32-bit RISC CPU manual available for free PDF download: User Manual

NEC V850 Series User Manual

NEC V850 Series User Manual (692 pages)

V850E/IA2 32-Bit Single-Chip Microcontrollers

Brand: NEC | Category: Microcontrollers | Size: 4.05 MB

Table of Contents

Table of Contents
9
Chapter 1 Introduction

17
- Outline
  17
- Features
  19
- Applications
  21
- Ordering Information
  21
- Pin Configuration (Top View)
  22
- Configuration of Function Block
  25
- Internal Block Diagram
  25
- Internal Units
  26
Chapter 2 Pin Functions

28
- List of Pin Functions
  28
- Pin Status
  33
- Description of Pin Functions
  34
- Types of Pin I/O Circuits and Connection of Unused Pins
  43
- Pin I/O Circuits
  45
Chapter 3 Cpu Function

46
- Features
  46
- CPU Register Set
  47
- Program Register Set
  48
- System Register Set
  49
- Operation Modes
  55
- Operation Mode Specification
  56
- Address Space
  57
- CPU Address Space
  57
- Image
  58
- Wrap-Around of CPU Address Space
  59
- Memory Map
  60
- Area
  61
- External Memory Expansion
  65
- Recommended Use of Address Space
  66
- On-Chip Peripheral I/O Registers
  68
- Specific Registers
  78
- System Wait Control Register (VSWC)
  78
- Cautions
  78
Chapter 4 Bus Control Function

80
- Features
  80
- Bus Control Pins
  80
- Pin Status During Internal ROM, Internal RAM, and On-Chip Peripheral I/O Access
  80
- Memory Block Function
  81
- Chip Select Control Function
  82
- Bus Cycle Type Control Function
  85
- Bus Access
  86
- Number of Access Clocks
  86
- Bus Sizing Function
  87
- Bus Width
  88
- Wait Function
  94
- Programmable Wait Function
  94
- External Wait Function
  96
- Relationship between Programmable Wait and External Wait
  96
- Idle State Insertion Function
  97
- Bus Priority Order
  98
- Boundary Operation Conditions
  99
- Program Space
  99
- Data Space
  99
Chapter 5 Memory Access Control Function

100
- SRAM, External ROM, External I/O Interface
  100
- Features
  100
- SRAM, External ROM, External I/O Access
  101
Chapter 6 Dma Functions (Dma Controller)

105
- Features
  105
- Configuration
  106
- Control Registers
  107
- DMA Source Address Registers 0 to 3 (DSA0 to DSA3)
  107
- DMA Destination Address Registers 0 to 3 (DDA0 to DDA3)
  109
- DMA Transfer Count Registers 0 to 3 (DBC0 to DBC3)
  111
- DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3)
  112
- DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3)
  114
- DMA Disable Status Register (DDIS)
  116
- DMA Restart Register (DRST)
  116
- DMA Trigger Factor Registers 0 to 3 (DTFR0 to DTFR3)
  117
- Transfer Modes
  120
- Single Transfer Mode
  120
- Single-Step Transfer Mode
  122
- Block Transfer Mode
  123
- Transfer Types
  123
- Two-Cycle Transfer
  123
- Transfer Target
  124
- Transfer Type and Transfer Target
  124
- External Bus Cycles During DMA Transfer (Two-Cycle Transfer)
  125
- DMA Channel Priorities
  125
- Next Address Setting Function
  125
- DMA Transfer Start Factors
  127
- Forcible Suspension
  128
- DMA Transfer End
  128
- Forcible Termination
  129
- Restrictions on Forcible Termination of DMA Transfer
  130
- Time Required for DMA Transfer
  131
- Cautions
  132
Chapter 7 Interrupt/Exception Processing Function

134
- Features
  134
- Non-Maskable Interrupt
  138
- Operation
  139
- Restore
  141
- Non-Maskable Interrupt Status Flag (NP)
  142
- Edge Detection Function
  142
- Maskable Interrupts
  143
- Operation
  143
- Restore
  145
- Priorities of Maskable Interrupts
  146
- Interrupt Control Register (Xxicn)
  150
- Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
  153
- In-Service Priority Register (ISPR)
  154
- Maskable Interrupt Status Flag (ID)
  155
- Interrupt Trigger Mode Selection
  155
- Software Exception
  163
- Operation
  163
- Restore
  164
- Exception Status Flag (EP)
  165
- Exception Trap
  166
- Illegal Opcode Definition
  166
- Debug Trap
  168
- Multiple Interrupt Servicing Control
  170
- Interrupt Response Time
  172
- Periods in Which CPU Does Not Acknowledge Interrupts
  173
Chapter 8 Clock Generation Function

174
- Features
  174
- Configuration
  174
- Input Clock Selection
  175
- Direct Mode
  175
- PLL Mode
  175
- Peripheral Command Register (PHCMD)
  176
- Clock Control Register (CKC)
  177
- Peripheral Status Register (PHS)
  179
- PLL Lockup
  180
- Power Save Control
  181
- Overview
  181
- Control Registers
  184
- HALT Mode
  187
- IDLE Mode
  189
- Software STOP Mode
  191
- Securing Oscillation Stabilization Time
  193
- Oscillation Stabilization Time Security Specification
  193
- Time Base Counter (TBC)
  194
Chapter 9 Timer/Counter Function

195
- Timer 0
  195
- Features (Timer 0)
  195
- Function Overview (Timer 0)
  196
- Functions Added to V850E/IA2
  197
- Basic Configuration
  198
- Control Registers
  205
- Operation
  229
- Operation Timing
  285
- Timer 1
  294
- Features (Timer 1)
  294
- Function Overview (Timer 1)
  294
- Basic Configuration
  296
- Control Registers
  299
- Operation
  310
- Supplementary Description of Internal Operation
  319
- Timer 2
  322
- Features (Timer 2)
  322
- Function Overview (Timer 2)
  322
- Basic Configuration
  324
- Control Registers
  330
- Operation
  347
- PWM Output Operation in Timer 2 Compare Mode
  365
- Timer 3
  368
- Features (Timer 3)
  368
- Function Overview (Timer 3)
  368
- Function Added to V850E/IA2
  369
- Basic Configuration
  369
- Control Registers
  373
- Operation
  380
- Application Examples
  388
- Cautions
  394
- Timer 4
  395
- Features (Timer 4)
  395
- Function Overview (Timer 4)
  395
- Basic Configuration
  396
- Control Register
  400
- Operation
  401
- Application Example
  403
- Cautions
  403
- Timer Connection Function
  404
- Overview
  404
- Control Register
  405
Chapter 10 Serial Interface Function

406
- Features
  406
- Selecting UART1 or CSI1 Mode
  407
- Asynchronous Serial Interface 0 (UART0)
  408
- Features
  408
- Configuration
  409
- Control Registers
  411
- Interrupt Requests
  418
- Operation
  419
- Dedicated Baud Rate Generator 0 (BRG0)
  431
- Cautions
  438
- Asynchronous Serial Interface 1 (UART1)
  439
- Features
  439
- Configuration
  440
- Control Registers
  442
- Interrupt Requests
  451
- Operation
  452
- Synchronous Mode
  462
- Dedicated Baud Rate Generator 1 (BRG1)
  467
- Clocked Serial Interfaces 0, 1 (CSI0, CSI1)
  474
- Features
  474
- Configuration
  475
- Control Registers
  478
- Operation
  492
- Output Pins
  507
- Dedicated Baud Rate Generator 3 (BRG3)
  508
Chapter 11 A/D Converter

512
- Features
  512
- Configuration
  512
- Functions Added to V850E/IA2
  516
- Control Registers
  517
- Interrupt Requests
  528
- A/D Converter Operation
  529
- A/D Converter Basic Operation
  529
- Operation Modes and Trigger Modes
  530
- Operation in A/D Trigger Mode
  533
- Operation in Select Mode
  533
- Operation in Scan Mode
  534
- Operation in A/D Trigger Polling Mode
  535
- Operation in Select Mode
  535
- Operation in Scan Mode
  536
- Operation in Timer Trigger Mode
  537
- Operation in Select Mode
  537
- Operation in Scan Mode
  538
- Operation in External Trigger Mode
  539
- Operation in Select Mode
  539

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