NEC V850E/Dx3 Single-Chip Microcontroller Manuals

Manuals and User Guides for NEC V850E/Dx3 Single-Chip Microcontroller. We have 1 NEC V850E/Dx3 Single-Chip Microcontroller manual available for free PDF download: Preliminary User's Manual

NEC V850E/Dx3 Preliminary User's Manual (930 pages)

32-bit Single-Chip Microcontroller

Brand: NEC | Category: Microcontrollers | Size: 15.44 MB

Table of Contents
9
Chapter 1 Introduction

23
- General
  23
- Features Summary
  24
- Product Series Overview
  28
- Description
  30
- Ordering Information
  34
Chapter 2 Pin Functions

35
- Overview
  35
- Description
  36
- Terms
  39
- Noise Elimination
  39
- Port Group Configuration Registers
  40
- Overview
  40
- Pin Function Configuration
  41
- Pin Data Input/Output
  46
- Configuration of Electrical Characteristics
  48
- Alternative Input Selection
  50
- Port Types Diagrams
  52
- Port Group Configuration
  56
- Port Group Configuration Lists
  56
- Alphabetic Pin Function List
  65
- External Memory Interface of Μpd70F3427
  71
- Port Group 0
  72
- Port Group 1
  74
- Port Group 2
  75
- Port Group 3
  76
- Port Group 4
  78
- Port Group 5
  79
- Port Group 6
  81
- Port Group 7
  83
- Port Group 8
  85
- Port Group 9
  87
- Port Group 10
  88
- Port Group 11
  89
- Port Group 12
  90
- Port Group 13
  91
- Port Group 14 (Μpd70F3427 Only)
  92
- Noise Elimination
  93
- Analog Filtered Inputs
  93
- Digitally Filtered Inputs
  93
- Pin Functions in Reset and Power Save Modes
  97
- Recommended Connection of Unused Pins
  98
- Package Pins Assignment
  99
- Μpd70F3424, Μpd70F3425, Μpd70F3426 - 144 Pin Package
  100
- Μpd70F3427 - 208 Pin Package
  101
Chapter 3 CPU System Functions

103
- Overview
  103
- Description
  104
- CPU Register Set
  105
- General Purpose Registers (R0 to R31)
  106
- System Register Set
  107
- Operation Modes
  114
- Normal Operation Mode
  115
- Flash Programming Mode (Flash Memory Devices Only)
  115
- Address Space
  115
- CPU Address Space and Physical Address Space
  115
- Program and Data Space
  117
- Memory
  119
- Memory Areas
  119
- Recommended Use of Data Address Space
  123
- Write Protected Registers
  124
- Instructions and Data Access Times
  126
Chapter 4 Clock Generator

129
- Overview
  129
- Description
  130
- Clock Monitors
  132
- Power Save Modes Overview
  133
- Start Conditions
  134
- Start-Up Guideline
  135
- Clock Generator Registers
  136
- General Clock Generator Registers
  138
- SSCG Control Registers
  144
- Control Registers for Peripheral Clocks
  150
- Control Registers for Power Save Modes
  157
- Clock Monitor Registers
  163
- Power Save Modes
  167
- Power Save Modes Description
  167
- Clock Generator State Transistions
  177
- Preliminary User's Manual U17566EE1V2UM00
  177
- Power Save Mode Activation
  179
- CPU Operation after Power Save Mode Release
  181
- Clock Generator Operation
  184
- Ring and Sub Oscillator Operation
  184
- Watch Timer and Watch Calibration Timer Clocks
  184
- Clock Output FOUTCLK
  184
- Operation of the Clock Monitors
  185
Chapter 5 Interrupt Controller (INTC)

187
- Features
  187
- Non-Maskable Interrupts
  197
- Operation
  200
- Restore
  201
- Non-Maskable Interrupt Status Flag (NP)
  202
- NMI0 Control
  202
- Maskable Interrupts
  203
- Operation
  203
- Restore
  205
- Priorities of Maskable Interrupts
  206
- XXIC - Maskable Interrupts Control Register
  210
- IMR0 to IMR5 - Interrupt Mask Registers
  214
- ISPR - In-Service Priority Register
  216
- Maskable Interrupt Status Flag (ID)
  216
- External Maskable Interrupts
  217
- Software Interrupts
  217
- Edge and Level Detection Configuration
  218
- Software Exception
  220
- Operation
  220
- Restore
  221
- Exception Status Flag (EP)
  222
- Exception Trap
  222
- Illegal Opcode Definition
  222
- Debug Trap
  224
- Multiple Interrupt Processing Control
  225
- Interrupt Response Time
  227
- Periods in Which Interrupts Are Not Acknowledged
  228
Chapter 6 Flash Memory

229
- Overview
  229
- Flash Memory Address Assignment
  230
- Flash Memory Erasure and Rewrite
  232
- Flash Memory Programming
  233
- Boot Block Swapping
  233
- Flash Self-Programming
  234
- Flash Self-Programming Registers
  234
- Interrupt Handling During Flash Self-Programming
  236
- Flash Programming Via N-Wire
  237
- Flash Programming with Flash Programmer
  238
- Programming Environment
  238
- Communication Mode
  239
- Pin Connection
  242
- Programming Method
  244
Chapter 7 Bus and Memory Control (BCU, MEMC)

249
- Overview
  249
- Description
  250
- Memory Banks and Chip Select Signals
  252
- Chips Select Priority Control
  255
- Peripheral I/O Area
  255
- NPB Access Timing
  257
- Bus Properties
  257
- Boundary Operation Conditions
  258
- Initialization for Access to External Devices
  259
- External Bus Mute Function
  259
- Registers
  260
- BCU Registers
  261
- Memory Controller Registers (Μpd70F3427 Only)
  271
- Page ROM Controller
  279
- Configuration of Memory Access
  282
- Endian Format
  282
- Wait Function
  282
- Idle State Insertion
  284
- External Devices Interface Timing
  284
- Writing to External Devices
  285
- Reading from External Devices
  287
- Read-Write Operation on External Devices
  289
- Write-Read Operation on External Devices
  290
- Page ROM Access Timing
  291
- Half Word/Word Access with 8-Bit Bus or Word Access with 16-Bit Bus
  292
- Byte Access with 8-Bit Bus or Byte/Half Word Access with 16-Bit Bus
  294
- Data Access Order
  296
- Access to 8-Bit Data Busses
  296
- Access to 16-Bit Data Busses
  302
Chapter 8 DMA Controller (DMAC)

309
- Features
  309
- Preliminary User's Manual U17566EE1V2UM00
  309
- Peripheral and CPU Clock Settings
  310
- DMAC Registers
  312
- DMA Source Address Registers
  312
- DMA Destination Address Registers
  314
- Dbcn - DMA Transfer Count Registers
  316
- Dadcn - DMA Addressing Control Registers
  317
- Dchcn - DMA Channel Control Registers
  319
- DRST - DMA Restart Register
  320
- Dtfrn - DMA Trigger Source Select Register
  321
- Automatic Restart Function
  323
- Transfer Type
  324
- Transfer Object
  324
- DMA Channel Priorities
  325
- DMA Transfer Start Factors
  325
- Forcible Interruption
  325
- Forcible Termination
  326
- DMA Transfer Completion
  327
- Transfer Mode
  328
- Single Transfer Mode
  328
- Block Transfer Mode
  330
Chapter 9 ROM Correction Function (ROMC)

331
- Overview
  331
- DBTRAP" ROM Correction Unit
  332
- DBTRAP" ROM Correction Operation
  333
- DBTRAP" ROM Correction Registers
  335
Chapter 10 Code Protection and Security

339
- Overview
  339
- Boot ROM
  339
- N-Wire Debug Interface
  339
- Flash Writer and Self-Programming Protection
  341
- Variable Reset Vector
  341
Chapter 11 16-Bit Timer/Event Counter P (TMP)

343
Chapter 12 16-Bit Interval Timer Z (TMZ)

429
- Overview
  429
- Description
  430
- Principle of Operation
  430
- TMZ Registers
  431
- Timing
  435
- Steady Operation
  435
- Timer Start and Stop
  436
Chapter 13 16-Bit Multi-Purpose Timer G (TMG)

437
- Features of Timer G
  437
- Function Overview of each Timer Gn
  438
- Basic Configuration
  440
- TMG Registers
  441
- Output Delay Operation
  449
- Explanation of Basic Operation
  450
- Operation in Free-Run Mode
  451
- Match and Clear Mode
  462
- Edge Noise Elimination
  473
- Precautions Timer Gn
  474
Chapter 14 Watch Timer (WT)

477
- Overview
  477
- Description
  479
- Principle of Operation
  480
- Watch Timer Registers
  482
- Preliminary User's Manual U17566EE1V2UM00
  483
- Watch Timer Operation
  485
- Timing of Steady Operation
  485
- Watch Timer Start-Up
  486
- Watch Calibration Timer Registers
  488
- Watch Calibration Timer Operation
  493
- INTWT0UV Interval Measurement with Free-Running Counter
  494
- INTWT0UV Interval Measurement by Restarting the Counter
  495
Chapter 15 Watchdog Timer (WDT)

497
- Overview
  497
- Description
  498
- Principle of Operation
  498
- Watchdog Timer Clock
  499
- Reset Behavior
  500
- Watchdog Timer Registers
  501
Chapter 16 Asynchronous Serial Interface (UARTA)

507
- Features
  507
- Configuration
  508
- UARTA Registers
  510
- Interrupt Request Signals
  518
- Operation
  519
- Data Format
  519
- SBF Transmission/Reception Format
  521
- SBF Transmission
  523
- SBF Reception
  523
- UART Transmission
  525
- Continuous Transmission Procedure
  526
- UART Reception
  528
- Reception Errors
  530
- Parity Types and Operations
  530
- Receive Data Noise Filter
  532
- Baud Rate Generator
  533
- Baud Rate Generator Configuration
  533
- Baud Rate Generator Registers
  534
- Baud Rate Calculation
  536
- Baud Rate Error
  536
- Baud Rate Setting Example
  537
- Allowable Baud Rate Range During Reception
  537
- Baud Rate During Continuous Transmission
  540
- Cautions
  540
Chapter 17 Clocked Serial Interface (CSIB)

541
- Features
  541
- Configuration
  542
- CSIB Control Registers
  543
- Operation
  552
- Single Transfer Mode (Master Mode, Transmission/Reception Mode)
  552
- Single Transfer Mode (Master Mode, Reception Mode)
  554
- Continuous Mode (Master Mode, Transmission/Reception Mode)
  555
- Continuous Mode (Master Mode, Reception Mode)
  556
- Continuous Reception Mode (Error)
  557
- Continuous Mode (Slave Mode, Transmission/Reception Mode)
  558
- Continuous Mode (Slave Mode, Reception Mode)
  560
- Clock Timing
  561
- Output Pins
  563
- Operation Flow
  564
- Baud Rate Generator
  570
- Overview
  570
- Baud Rate Generator Registers
  571
- Baud Rate Calculation
  572
Chapter 18 I 2 C Bus (IIC)

573
- Features
  573
- I2C Pin Configuration
  574
- Configuration
  575
- IIC Registers
  578
- I 2 C Bus Pin Functions
  593
- I 2 C Bus Definitions and Control Methods
  593
- Start Condition
  594
- Addresses
  595
- Transfer Direction Specification
  596
- Acknowledge Signal (ACK)
  596
- Stop Condition
  598
- Wait Signal (WAIT)
  599
- I 2 C Interrupt Request Signals (Intiicn)
  601
- Master Device Operation
  601
- Slave Device Operation
  604
- Slave Device Operation (When Receiving Extension Code)
  608
- Operation Without Communication
  612
- Arbitration Loss Operation (Operation as Slave after Arbitration Loss)
  612
- Operation When Arbitration Loss Occurs
  614
- Interrupt Request Signal (Intiicn)
  619
- Address Match Detection Method
  620
- Error Detection
  620
- Extension Code
  621
- Arbitration
  622
- Wakeup Function
  623
- Cautions
  624
- Communication Operations
  624
- Master Operation 1
  624
- Master Operation 2
  626
- Slave Operation
  627
- Timing of Data Communication
  631
Chapter 19 CAN Controller (CAN)

639
- Features
  640
- Overview of Functions
  641
- Configuration
  642
- CAN Protocol
  643
- Frame Format
  643
- Frame Types
  644
- Data Frame and Remote Frame
  644
- Error Frame
  652
- Overload Frame
  653
- Functions
  654
- Determining Bus Priority
  654
- Bit Stuffing
  654
- Multi Masters
  655
- Multi Cast
  655
- CAN Sleep Mode/Can Stop Mode Function
  655
- Error Control Function
  655
- Baud Rate Control Function
  662
- Connection with Target System
  665
- Internal Registers of CAN Controller
  666
- CAN Module Register and Message Buffer Addresses
  666
- CAN Controller Configuration
  667
- CAN Registers Overview
  668
- Register Bit Configuration
  672
- Control Registers
  675
- Bit Set/Clear Function
  709
- CAN Controller Initialization
  711
- Initialization of CAN Module
  711
- Initialization of Message Buffer
  711
- Redefinition of Message Buffer
  711
- Transition from Initialization Mode to Operation Mode
  713
- Resetting Error Counter CNERC of CAN Module
  714
- Message Reception
  714
- Receive History List Function
  715
- Mask Function
  717
- Multi Buffer Receive Block Function
  719
- Remote Frame Reception
  720
- Message Transmission
  721
- Transmit History List Function
  723
- Automatic Block Transmission (ABT)
  725
- Transmission Abort Process
  727
- Remote Frame Transmission
  727
- Power Saving Modes
  728
- CAN Sleep Mode
  728
- CAN Stop Mode
  730
- Example of Using Power Saving Modes
  731
- Interrupt Function
  732
- Diagnosis Functions and Special Operational Modes
  733
- Receive-Only Mode
  733
- Single-Shot Mode
  734
- Self-Test Mode
  735
- Time Stamp Function
  736
- Baud Rate Settings
  737
- Baud Rate Setting Conditions
  737
- Representative Examples of Baud Rate Settings
  741
- Operation of CAN Controller
  745
- Operating Precautions
  768
- Wake-Up from Sleep Mode
  768
Chapter 20 A/D Converter (ADC)

769
- Functions
  769
- Configuration
  771
- ADC Registers
  773
- Operation
  781
- Basic Operation
  781
- Trigger Mode
  782
- Operation Modes
  783
- Power-Fail Compare Mode
  785
- Cautions
  788
- How to Read A/D Converter Characteristics Table
  790
Chapter 21 Stepper Motor Controller/Driver (Stepper-C/D)

795
- Overview
  795
- Driver Overview
  795
- Stepper Motor Controller/Driver Registers
  797
- Operation
  803
- Stepper Motor Controller/Driver Operation
  803
- Timing
  806
- Timer Counter
  806
- Automatic PWM Phase Shift
  807
Chapter 22 LCD Controller/Driver (LCD-C/D)

809
- Overview
  809
- Description
  810
- LCD Panel Addressing
  811
- LCD-C/D Registers
  812
- Operation
  816
- Common Signals and Segment Signals
  816
- Activation of LCD Segments
  818
- Display Example
  818
Chapter 23 LCD Bus Interface (LCD-I/F)

823
- Overview
  823
- Description
  824
- LCD Bus Interface Access Modes
  825
- Access Types to the LBDATA0 Register
  825
- Interrupt Generation
  826
- LCD Bus Interface Registers
  827
- Timing
  834
- Timing Dependencies
  834
- LCD Bus I/F States During and after Accesses
  835
- Writing to the LCD Bus
  835
- Reading from the LCD Bus
  838
- Write-Read-Write Sequence on the LCD Bus
  840
Chapter 24 Sound Generator (SG)

841
- Overview
  841
- Description
  842
- Principle of Operation
  843
- Sound Generator Registers
  844
- Sound Generator Operation
  849
- Generating the Tone
  849
- Generating the Volume Information
  850
- Sound Generator Application Hints
  853
- Initialization
  853
- Start and Stop Sound
  853
- Change Sound Volume
  853
- Generate Special Sounds
  853
Chapter 25 Power Supply Scheme

855
- Overview
  855
- Description
  857
- Devices Μpd70(F)3420, Μpd70(F)3421, Μpd70(F)3422, Μpd70F3423
  857
- Devices Μpd70F3424, Μpd70F3425, Μpd70F3426
  858
- Device Μpd70F3427
  859
- Voltage Regulators
  860
Chapter 26 Reset

861
- Overview
  861
- General Reset Performance
  861
- Reset at Power-On
  865
- External RESET
  866
- Reset by Watchdog Timer
  867
- Reset by Clock Monitor
  867
- Reset Registers
  867
Chapter 27 Voltage Comparator

871
- Overview
  871
- Description
  872
- Comparison Results
  872
- Stand-By Mode
  872
- Voltage Comparator Registers
  873
- Timing
  875
Chapter 28 On-Chip Debug Unit

877
- Functional Outline
  877
- Debug Functions
  877
- Security Function
  879
- Controlling the N-Wire Interface
  882
- N-Wire Enabling Methods
  884
- Starting Normal Operation after RESET and RESPOC
  884
- Starting Debugger after RESET and RESPOC
  884
- N-Wire Activation by RESET Pin
  885
- Connection to N-Wire Emulator
  886
- KEL Connector
  886
- Restrictions and Cautions on On-Chip Debug Function
  890
Appendix A Special Function Registers

891
Appendix B Registers Access Times

911
- Revision History
  921
- Index
  923

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NEC V850E/Dx3 Single-Chip Microcontroller Manuals

NEC V850E/Dx3 Preliminary User's Manual (930 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 CPU System Functions

Chapter 4 Clock Generator

Chapter 5 Interrupt Controller (INTC)

Chapter 6 Flash Memory

Chapter 7 Bus and Memory Control (BCU, MEMC)

Chapter 8 DMA Controller (DMAC)

Chapter 9 ROM Correction Function (ROMC)

Chapter 10 Code Protection and Security

Chapter 11 16-Bit Timer/Event Counter P (TMP)

Chapter 12 16-Bit Interval Timer Z (TMZ)

Chapter 13 16-Bit Multi-Purpose Timer G (TMG)

Chapter 14 Watch Timer (WT)

Chapter 15 Watchdog Timer (WDT)

Chapter 16 Asynchronous Serial Interface (UARTA)

Chapter 17 Clocked Serial Interface (CSIB)

Chapter 18 I 2 C Bus (IIC)

Chapter 19 CAN Controller (CAN)

Chapter 20 A/D Converter (ADC)

Chapter 21 Stepper Motor Controller/Driver (Stepper-C/D)

Chapter 22 LCD Controller/Driver (LCD-C/D)

Chapter 23 LCD Bus Interface (LCD-I/F)

Chapter 24 Sound Generator (SG)

Chapter 25 Power Supply Scheme

Chapter 26 Reset

Chapter 27 Voltage Comparator

Chapter 28 On-Chip Debug Unit

Appendix A Special Function Registers

Appendix B Registers Access Times

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