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MuPD70F3187
NEC MuPD70F3187 Microcontroller Manuals
Manuals and User Guides for NEC MuPD70F3187 Microcontroller. We have
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NEC MuPD70F3187 Microcontroller manual available for free PDF download: User Manual
NEC MuPD70F3187 User Manual (1053 pages)
32-Bit Single-Chip Microcontroller
Brand:
NEC
| Category:
Microcontrollers
| Size: 7.31 MB
Table of Contents
Preface
7
Preface
5
Table of Contents
7
Table of Contents
17
Chapter 1 Introduction
33
Outline
33
Device Features
34
Applications
36
Ordering Information
36
Pin Configuration (Top View)
37
Figure 1-1: Pin Configuration 208-Pin Plastic LQFP
37
Figure 1-2: Pin Configuration 256-Pin Plastic BGA (21 × 21)
38
Table 1-1: Differences in Pin Assignment of 256-Pin Plastic BGA
39
Function Blocks
44
Internal Block Diagrams
44
Figure 1-3: Internal Block Diagram of Mpd70F3187
44
Figure 1-4: Internal Block Diagram of Mpd70F3447
45
On-Chip Units
46
Pin Functions
49
List of Pin Functions
49
Table 2-1: Port Pins
49
CPU Functions
85
Features
85
CPU Register Set
86
Figure 3-1: CPU Register Set
86
Program Register Set
87
Figure 3-2: Program Counter (PC)
87
Table 3-1: Program Registers
87
System Register Set
88
Table 3-2: System Register Numbers
88
Figure 3-3: Interrupt Status Saving Registers (EIPC, EIPSW)
89
Figure 3-4: NMI Status Saving Registers (FEPC, FEPSW)
90
Figure 3-5: Interrupt Source Register (ECR)
90
Figure 3-6: Program Status Word (PSW)
91
Figure 3-7: CALLT Execution Status Saving Registers (CTPC, CTPSW)
92
Table 3-3: Saturated Operation Results
92
Figure 3-8: Exception/Debug Trap Status Saving Registers (DBPC, DBPSW)
93
Figure 3-9: CALLT Base Pointer (CTBP)
93
Floating Point Arithmetic Unit Register Set
94
Figure 3-10: Floating Point Arithmetic Control Register (ECT)
94
Table 3-4: Floating Point Arithmetic Unit Registers
94
Figure 3-11: Floating Point Arithmetic Status Register (EFG)
95
Operating Modes
96
Operating Modes Outline
96
Operation Mode Specification
97
Address Space
98
CPU Address Space
98
Figure 3-12: CPU Address Space
98
Images
99
Figure 3-13: Address Space Image
99
Wrap-Around of CPU Address Space
100
Figure 3-14: Program Space
100
Figure 3-15: Data Space
100
Memory Map
101
Figure 3-16: Memory Map of Μpd70F3187
101
Figure 3-17: Memory Map of Μpd70F3447
102
Areas
103
Figure 3-18: Internal ROM / Internal Flash Memory Area of Μpd70F3187
103
Figure 3-19: Internal ROM / Internal Flash Memory Area of Μpd70F3447
104
Figure 3-20: Internal RAM Area of Μpd70F3187
105
Figure 3-21: Internal RAM Area of Μpd70F3447
105
Figure 3-22: On-Chip Peripheral I/O Area
106
Peripheral I/O Registers List
107
Table 3-5: Peripheral I/O Registers
107
Programmable Peripheral I/O Area
121
Figure 3-23: Programmable Peripheral I/O Area (Outline)
121
Figure 3-24: Programmable Peripheral Area Control Register BPC
122
Table 3-6: Programmable Peripheral I/O Registers
123
Specific Registers
139
Figure 3-25: Processor Command Register (PRCMD)
140
Figure 3-26: System Status Register Format PHS
141
System Wait Control Register (VSWC)
142
DMA Wait Control Registers 0 and 1 (DMAWC0, DMAWC1)
142
Cautions
143
Bus Control Function (Μpd70F3187 Only)
145
Features
145
Bus Control Pins
145
Memory Block Function
146
Figure 4-1: Memory Block Function
146
Chip Select Control Function
147
Figure 4-2: Chip Area Select Control Registers 0, 1 (1/2)
147
Bus Cycle Type Control Function
149
Bus Cycle Type Configuration
150
Figure 4-3: Bus Cycle Configuration Registers 0, 1 (BCT0, BCT1)
150
Bus Access
151
Number of Access Clocks
151
Table 4-1: Number of Bus Access Clocks
151
Bus Sizing Function
152
Figure 4-4: Bus Size Configuration Register (BSC)
152
Endian Control Function
153
Figure 4-5: Big Endian Addresses Within Word
153
Figure 4-6: Little Endian Addresses Within Word
153
Figure 4-7: Endian Configuration Register (BEC)
154
Bus Width
155
Wait Function
174
Programmable Wait Function
174
Figure 4-8: Data Wait Control Registers 0, 1 (DWC0, DWC1) Format
174
Figure 4-9: Address Wait Control Register (AWC)
175
Idle State Insertion Function
176
Figure 4-10: Bus Cycle Control Register (BCC)
177
Figure 4-11: Bus Clock Dividing Control Register (DVC)
178
Bus Priority Order
179
Table 4-2: Bus Priority Order
179
Boundary Operation Conditions
180
Program Space
180
Data Space
180
Chapter 2 Pin Functions
49
Table 2-2: Non-Port Pins
54
Pin Status
60
Table 2-3: Pin Status in Reset and Standby Mode
60
Description of Pin Functions
61
Pin I/O Circuits and Recommended Connection of Unused Pins
76
Table 2-4: I/O Circuit Types
76
Figure 2-1: Pin I/O Circuits
80
Noise Suppression
81
Table 2-5: Noise Suppression Timing
81
Figure 2-2: Noise Removal Time Control Register (1/2)
82
Chapter 5 Memory Access Control Function (Μpd70F3187 Only)
181
SRAM, External ROM, External I/O Interface
181
Features
181
SRAM Connection
182
Figure 5-1: Examples of Connection to SRAM (1/2)
182
SRAM, External ROM, External I/O Access
184
Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/8)
184
Chapter 6 DMA Functions (DMA Controller)
193
Features
193
Control Registers
194
Figure 6-1: DMA Transfer Memory Start Address Registers 0 to 7 (MAR0 to MAR7)
194
Figure 6-2: DMA Transfer SFR Start Address Registers 2, 3 (SAR2, SAR3)
195
Figure 6-3: DMA Transfer Count Registers 0 to 7 (DTCR0 to DTCR7)
196
Figure 6-4: DMA Mode Control Register (DMAMC)
197
Figure 6-5: DMA Status Register (DMAS)
197
Figure 6-6: DMA Data Size Control Register (DMDSC)
198
Figure 6-7: DMA Trigger Factor Registers 4 to 7 (DTFR4 to DTFR7)
199
DMA Channel Priorities
200
DMA Operation
200
DMA Transfer of A/D Converter Result Registers (ADC0, ADC1)
200
Figure 6-8: Initialization of DMA Transfer for A/D Conversion Result
201
Figure 6-9: Operation of DMA Channel 0/1
202
Figure 6-10: DMA Channel 0 and 1 Trigger Signal Timing
203
DMA Transfer of PWM Timer Reload (TMR0, TMR1)
204
Table 6-1: Timer TMR Address Mapping for DMA Transfer
204
Figure 6-11: Initialization of DMA Transfer for Tmrn Compare Registers
205
Figure 6-12: Operation of DMA Channel 2/3
206
Figure 6-13: DMA Channel 2 and 3 Trigger Signal Timing
207
DMA Transfer of Serial Interfaces
208
Table 6-2: DMA Configuration of Serial Data Reception
208
Figure 6-14: Initialization of DMA Transfer for Serial Data Reception
209
Figure 6-15: Operation of DMA Channel 4/5
210
Figure 6-16: DMA Channel 4 and 5 Trigger Signal Timing
211
Table 6-3: DMA Configuration of Serial Data Transmission
212
Figure 6-17: Initialization of DMA Transfer for Serial Data Transmission
213
Figure 6-18: DMA Channel 6 and 7 Trigger Signal Timing
214
Figure 6-19: Operation of DMA Channel 6/7
215
Forcible Termination of DMA Transfer
216
Figure 6-20: CPU and DMA Controller Processing of DMA Transfer Termination (Example)
216
DMA Interrupt Function
217
Table 6-4: Relations between DMA Trigger Factors and DMA Completion Interrupts
217
Table 7-1: Interrupt/Exception Source List
217
Figure 6-21: Correlation between Serial I/O Interface Interrupts and DMA Completion Interrupts
218
Chapter 7 Interrupt/Exception Processing Function
219
Features
219
Non-Maskable Interrupt
224
Operation
225
Figure 7-1: Processing Configuration of Non-Maskable Interrupt
225
Figure 7-2: Acknowledging Non-Maskable Interrupt Request
226
Restore
227
Figure 7-3: RETI Instruction Processing
227
Non-Maskable Interrupt Status Flag (NP)
228
Edge Detection Function
228
Figure 7-4: Non-Maskable Interrupt Status Flag (NP)
228
Figure 7-5: NMI Edge Detection Specification: Interrupt Mode Register 0 (INTM0)
228
Maskable Interrupts
229
Operation
229
Figure 7-6: Maskable Interrupt Processing
230
Restore
231
Figure 7-7: RETI Instruction Processing
231
Priorities of Maskable Interrupts
232
Figure 7-8: Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Processed (1/2)
233
Figure 7-9: Example of Processing Interrupt Requests Simultaneously Generated
235
Interrupt Control Register (Picn)
236
Figure 7-10: Interrupt Control Register (Picn)
236
Table 7-2: Addresses and Bits of Interrupt Control Registers
237
Interrupt Mask Registers 0 to 6 (IMR0 to IMR6)
240
Figure 7-11: Interrupt Mask Registers 0 to 2 (IMR0 to IMR2)
240
Figure 7-12: Interrupt Mask Registers 3 to 6 (IMR3 to IMR6)
241
In-Service Priority Register (ISPR)
242
Figure 7-13: Interrupt Service Priority Register (ISPR)
242
Maskable Interrupt Status Flag (ID)
243
Figure 7-14: Maskable Interrupt Status Flag (ID)
243
Interrupt Trigger Mode Selection
244
Figure 7-15: Interrupt Mode Register 0 (INTM0)
245
Figure 7-16: Interrupt Mode Register 1 (INTM1)
246
Figure 7-17: Interrupt Mode Register 2 (INTM2)
247
Figure 7-18: Interrupt Mode Register 3 (INTM3)
248
Software Exception
249
Operation
249
Figure 7-19: Software Exception Processing
249
Restore
250
Figure 7-20: RETI Instruction Processing
250
Exception Status Flag (EP)
251
Figure 7-21: Exception Status Flag (EP)
251
Exception Trap
252
Illegal Opcode Definition
252
Figure 7-22: Illegal Opcode
252
Figure 7-23: Exception Trap Processing
253
Figure 7-24: Restore Processing from Exception Trap
253
Periods in Which CPU Does Not Acknowledge Interrupts
254
Chapter 8 Clock Generator
255
Features
255
Configuration
255
Figure 8-1: Clock Generator
255
Power Save Control
256
Overview
256
Figure 8-2: Power Save Mode State Transition Diagram
256
HALT Mode
257
Table 8-1: Operation Status in HALT Mode
257
Table 8-2: Operation after Releasing HALT Mode by Interrupt Request Signal
258
Chapter 9 16-Bit Timer/Event Counter P
259
Features
259
Function Outline
259
Configuration
260
Figure 9-1: Block Diagram of Timer P
260
Table 9-1: Configuration of TMP0 to TMP8
260
Figure 9-2: Tmpn Capture/Compare Register 0 (Tpnccr0)
261
Figure 9-3: Tmpn Capture/Compare Register 1 (Tpnccr1)
262
Figure 9-4: Tmpn Counter Register (Tpncnt)
263
Control Registers
264
Figure 9-5: Tmpn Control Register 0 (Tpnctl0)
264
Figure 9-6: Tmpn Control Register 1 (Tpnctl1) (1/2)
265
Figure 9-7: Tmpn I/O Control Register 0 (Tpnioc0)
267
Figure 9-8: Tmpn I/O Control Register 1 (Tpnioc1)
268
Figure 9-9: Tmpn I/O Control Register 2 (Tpnioc2)
269
Figure 9-10: Tmpn Option Register 0 (Tpnopt0)
270
Figure 9-11: Tmpn Input Control Register 0 (TPIC0)
271
Figure 9-12: TMP Input Control Register 1 (TPIC1)
272
Figure 9-13: TMP Input Control Register 1 (TPIC1)
272
Operation
274
Anytime Rewrite and Reload
274
Figure 9-14: Basic Operation Flow for Anytime Write
275
Figure 9-15: Timing Diagram for Anytime Write
276
Figure 9-16: Basic Operation Flow for Reload (Batch Rewrite)
277
Figure 9-17: Timing Chart for Reload
278
Interval Timer Mode (Tpnmd2 to Tpnmd0 = 000B)
279
Figure 9-18: Flowchart of Basic Operation in Interval Timer Mode
279
Figure 9-19: Basic Operation Timing in Interval Timer Mode (1/2)
280
External Event Count Mode (Tpnmd2 to Tpnmd0 = 001B)
282
Figure 9-20: Flowchart of Basic Operation in External Event Count Mode
283
Figure 9-21: Basic Operation Timing in External Event Count Mode (1/2)
284
External Trigger Pulse Output Mode (Tpnmd2 to Tpnmd0 = 010B)
286
Figure 9-22: Flowchart of Basic Operation in External Trigger Pulse Output Mode
287
Figure 9-23: Basic Operation Timing in External Trigger Pulse Output Mode
288
One-Shot Pulse Mode (Tpnmd2 to Tpnmd0 = 011B)
289
Figure 9-24: Flowchart of Basic Operation in One-Shot Pulse Mode
290
Figure 9-25: Timing of Basic Operation in One-Shot Pulse Mode
291
PWM Mode (Tpnmd2 to Tpnmd0 = 100B)
292
Figure 9-26: Flowchart of Basic Operation in PWM Mode (1/2)
293
Figure 9-27: Basic Operation Timing in PWM Mode (1/2)
295
Free-Running Mode (Tpnmd2 to Tpnmd0 = 101B)
297
Figure 9-28: Flowchart of Basic Operation in Free-Running Mode
299
Figure 9-29: Basic Operation Timing in Free-Running Mode (Tpnccs1 = 0, Tpnccs0 = 0)
300
Figure 9-30: Basic Operation Timing in Free-Running Mode (Tpnccs1 = 1, Tpnccs0 = 1)
301
Figure 9-31: Basic Operation Timing in Free-Running Mode (Tpnccs1 = 1, Tpnccs0 = 0)
302
Figure 9-32: Basic Operation Timing in Free-Running Mode (Tpnccs1 = 0, Tpnccs0 = 1)
303
Pulse Width Measurement Mode (Tpnmd2 to Tpnmd0 = 110B)
304
Figure 9-33: Flowchart of Pulse Period Measurement
305
Figure 9-34: Basic Operation Timing of Pulse Period Measurement
306
Figure 9-35: Flowchart of Alternating Pulse Width and Pulse Space Measurement
307
Figure 9-36: Basic Operation Timing of Alternating Pulse Width and Pulse Space Measurement
308
Figure 9-37: Flowchart of Simultaneous Pulse Width and Pulse Space Measurement
309
Figure 9-38: Basic Operation Timing of Simultaneous Pulse Width and Pulse Space Measurement
310
Counter Synchronous Operation Function
311
Chapter 10 16-Bit Inverter Timer/Counter R
313
Features
313
Configuration
314
Table 10-1: Timer R Configuration
314
Figure 10-1: Timer Rn Block Diagram
315
Figure 10-2: Tmrn Capture/Compare Register 0 (Trnccr0)
316
Figure 10-3: Tmrn Capture/Compare Register 1 (Trnccr1)
317
Figure 10-4: Tmrn Capture/Compare Register 2 (Trnccr2)
318
Figure 10-5: Tmrn Capture/Compare Register 3 (Trnccr3)
319
Figure 10-6: Tmrn Compare Register 4 (Trnccr4)
320
Figure 10-7: Tmrn Compare Register 5 (Trnccr5)
321
Figure 10-8: Tmrn Counter Read Register (Trncnt)
322
Figure 10-9: Tmrn Sub-Counter Read Register (Trnsbc)
322
Figure 10-10: Tmrn Dead Time Setting Register 0 (Trndtc0)
323
Figure 10-11: Tmrn Dead Time Setting Register 1 (Trndtc1)
323
Control Registers
324
Figure 10-12: Tmrn Control Register 0 (Trnctl0) (1/2)
324
Table 10-2: Tmrn Count Clock and Count Delay
325
Figure 10-13: Tmrn Control Register 1 (Trnctl1) (1/2)
326
Figure 10-14: Tmrn I/O Control Register 0 (Trnioc0)
328
Figure 10-15: TMR1 I/O Control Register 1 (TR1IOC1)
329
Figure 10-16: TMR1 I/O Control Register 2 (TR1IOC2)
330
Figure 10-17: Tmrn I/O Control Register 3 (Trnioc3)
331
Figure 10-18: Tmrn I/O Control Register 4 (Trnioc4)
332
Figure 10-19: Tmrn Option Register 0 (Trnopt0) (1/2)
333
Figure 10-20: Tmrn Option Register 1 (Trnopt1) (1/2)
335
Figure 10-21: Tmrn Option Register 2 (Trnopt2) (1/2)
337
Figure 10-22: Tmrn Option Register 3 (Trnopt3) (1/2)
339
Figure 10-23: Tmrn Option Register 6 (Trnopt6)
341
Figure 10-24: Tmrn Option Register 7 (Trnopt7)
342
Basic Operation
343
Basic Counter Operation
343
Compare Register Rewrite Operation
345
Figure 10-25: Anytime Rewrite Timing
347
Figure 10-26: Basic Operation Flow During Batch Rewrite
352
Figure 10-27: Batch Rewrite Timing (1/2)
353
List of Outputs in each Mode
358
Table 10-3: List of Timer Outputs in each Mode (1/2)
358
Figure 10-28: Torn7 Pin Output Timing 1
360
Table 10-4: List of Interrupts in each Mode (1/2)
361
Table 10-5: List of A/D Conversion Triggers, Peak Interrupts and Valley Interrupts in each Mode
363
Match Interrupts
364
Figure 10-29: Interrupt Signal Output Example (1/2)
364
Compare Match Interrupt Related Cautions
366
Flags
368
Up Count Flags
368
Figure 10-30: up Count Flags Timings (1/2)
368
Normal Phase/Inverted Phase Simultaneous Active Detection Flag
369
Figure 10-31: Normal Phase/Inverted Phase Simultaneous Active Detection Flag Timing
369
Reload Hold Flag
370
Figure 10-32: Reload Hold Flag Timings
370
Interrupt Thinning out Function
371
Operation of Interrupt Thinning out Function
372
Figure 10-33: Interrupt Thinning out Operations (1/2)
372
Operation Examples When Peak Interrupts and Valley Interrupts Occur Alternately
374
Figure 10-34: Examples When Peak Interrupts and Valley Interrupts Occur Alternately (1/2)
374
Interrupt Thinning out Function During Counter Saw Tooth Wave Operation
375
A/D Conversion Trigger Function
376
Figure 10-35: A/D Conversion Trigger Output Controller
376
A/D Conversion Trigger Operation
377
Figure 10-36: A/D Conversion Trigger Timings (1/2)
378
Error Interrupts
380
Error Interrupt and Error Signal Output Functions
380
Figure 10-37: Error Interrupt (Inttrner) and Error Signal (Trner) Output Controller
380
Figure 10-38: Error Interrupt and Error Signal Output Controller in PWM Mode
381
Figure 10-39: Error Interrupt and Error Signal Output Controller in Triangular Wave PWM Mode
382
Figure 10-40: Error Interrupt and Error Signal Output Controller
383
Operation in each Mode
384
Interval Timer Mode
384
Figure 10-41: Basic Operation Flow in Interval Timer Mode
384
Chapter 10 16-Bit Inverter Timer/Counter R
385
Figure 10-42: Basic Timing in Interval Timer Mode (1/2)
386
External Event Count Mode
388
Figure 10-43: Basic Operation Timing in External Event Count Mode (1/4)
390
External Trigger Pulse Output Mode (TMR1 Only)
394
Figure 10-44: Basic Operation Flow in External Trigger Pulse Output Mode
396
Figure 10-45: Basic Operation Timing in External Trigger Pulse Output Mode
397
One-Shot Pulse Mode
398
Figure 10-46: Basic Operation Flow in One-Shot Pulse Mode
400
Figure 10-47: Basic Operation Timing in One-Shot Pulse Mode
401
PWM Mode
402
Figure 10-48: Basic Operation Mode in PWM Mode (1/2)
404
Figure 10-49: Basic Operation Timing in PWM Mode (1/2)
406
Free-Running Mode
408
Figure 10-50: Basic Operation Flow in Free-Running Mode
408
Figure 10-51: Basic Operation Timing in Free-Running Mode (Compare Function)
411
Figure 10-52: Basic Operation Timing in Free-Running Mode (Capture Function)
412
Figure 10-53: Basic Operation Timing in Free-Running Mode (Compare/Capture Function)
413
Pulse Width Measurement Mode (TMR1 Only)
415
Figure 10-54: Basic Operation Timing in Pulse Width Measurement Mode
415
Triangular Wave PWM Mode
417
Figure 10-55: Basic Operation Timing in Triangular Wave PWM Mode
419
High-Accuracy T-PWM Mode
420
Figure 10-56: High-Accuracy T-PWM Mode Block Diagram
420
Figure 10-57: Counter Operation in High-Accuracy T-PWM Mode
424
Figure 10-58: Sub-Counter Operation in High-Accuracy T-PWM Mode
424
Figure 10-59: Timer Output Example When Trnce = 1 Is Set (Initial) (High-Accuracy T-PWM Mode)
425
Figure 10-60: Timer Output Example During Operation (High-Accuracy T-PWM Mode)
426
Figure 10-61: Torn1 Pin Output Example When Performing Additional Pulse Control
427
Figure 10-62: Torn1 Pin Output Example When Additional Pulse Control Is Not Performed
428
Figure 10-63: Timings of Timer Output in High-Accuracy T-PWM Mode (1/3)
429
Table 10-1: Positive Phase Operation Condition List
432
Table 10-2: Negative Phase Operation Condition List
432
Figure 10-64: Timer Output Change after Compare Register Updating Timings (1/3)
433
Table 10-3: Compare Register Value after Trough Reload (Trndtc0 < Trndtc1)
433
Figure 10-65: Compare Register Value after Trough Reload Timing (1/3)
436
Table 10-4: Compare Register Value after Trough Reload
436
Table 10-5: Compare Register Value after Trough Reload (Trndtc1 < Trndtc0)
438
Figure 10-66: Compare Register Value after Trough Reload (Trndtc1 < Trndtc0) (1/3)
439
Figure 10-67: Compare Register Value after Trough Reload (1/3)
442
Table 10-6: Compare Register Value after Trough Reload
442
Figure 10-68: Output Waveform Example When Dead Time Is Set
445
Figure 10-69: Dead Time Control in High-Accuracy T-PWM Mode
446
Figure 10-70: Operation Example Setting Is out of Range
447
Figure 10-71: Error Interrupt Operation Example
448
PWM Mode with Dead Time
449
Figure 10-72: Block Diagram in PWM Mode with Dead Time
449
Figure 10-73: Output Waveform Example in PWM Mode with Dead Time
451
Figure 10-74: Timer Output Example When Trnce = 1 Is Set (Initial) (PWM Mode with Dead Time)
454
Figure 10-75: Output Waveform Example in PWM Mode with Dead Time
455
Figure 10-76: Error Interrupt (Inttrner) in PWM Mode with Dead Time
456
Chapter 11 16-Bit Timer/Event Counter T
457
Features
457
Function Outline
457
Configuration
458
Table 11-1: Timer T Configuration
458
Table 11-2: List of Timer T Registers
459
Figure 11-1: Block Diagram of Timer T
460
Figure 11-2: Tmtn Capture/Compare Register 0 (Ttnccr0)
461
Table 11-3: Capture/Compare Functions in each Mode
461
Figure 11-3: Tmtn Capture/Compare Register 1 (Ttnccr1)
462
Table 11-4: Capture/Compare Functions in each Mode
463
Figure 11-4: Tmtn Counter Write Buffer Register (Ttntcw)
464
Figure 11-5: Tmtn Counter Read Buffer Register (Ttncnt)
464
Control Registers
465
Figure 11-6: Tmtn Control Register 0 (Ttnctl0) (1/2)
465
Table 11-5: Tmtn Count Clock and Count Delay
466
Figure 11-7: Tmtn Control Register 1 (Ttnctl1) (1/2)
467
Figure 11-8: Tmtn Control Register 2 (Ttnctl2) (1/2)
469
Figure 11-9: Tmtn I/O Control Register 0 (Ttnioc0)
471
Figure 11-10: Tmtn I/O Control Register 1 (Ttnioc1)
472
Figure 11-11: Tmtn I/O Control Register 2 (Ttnioc2)
473
Figure 11-12: Tmtn I/O Control Register 3 (Ttnioc3) (1/2)
474
Figure 11-13: Tmtn Option Register 0 (Ttnopt0)
476
Figure 11-14: Tmtn Option Register 1 (Ttnopt1) (1/2)
477
Figure 11-15: Tmtn Option Register 2 (Ttnopt2)
479
Basic Operation
480
Basic Counter Operation
480
Table 11-6: Counter Clear Operation
481
Method for Writing to Compare Register
483
Figure 11-16: Basic Operation Flow for Anytime Rewrite
483
Figure 11-17: Basic Anytime Rewrite Operation Timing
484
Figure 11-18: Basic Operation Flow for Reload (Batch Rewrite)
485
Figure 11-19: Basic Reload Operation Timing
486
Table 11-7: Capture/Compare Rewrite Methods in each Mode
486
Operation in each Mode
487
Interval Timer Mode
487
Figure 11-20: Basic Operation Flow in Interval Timer Mode
487
Figure 11-21: Basic Timing in Interval Timer Mode (1/2)
488
External Event Count Mode
490
Figure 11-22: Basic Operation Timing in External Event Count Mode (1/4)
491
External Trigger Pulse Output Mode
495
Figure 11-23: Basic Operation Flow in External Trigger Pulse Output Mode
496
Figure 11-24: Basic Operation Timing in External Trigger Pulse Output Mode
497
One-Shot Pulse Mode
498
Figure 11-25: Basic Operation Flow in One-Shot Pulse Mode
499
Figure 11-26: Basic Operation Timing in One-Shot Pulse Mode
500
PWM Mode
501
Figure 11-27: Basic Operation Mode in PWM Mode (1/2)
501
Figure 11-28: Basic Operation Timing in PWM Mode (1/2)
503
Free-Running Mode
505
Figure 11-29: Basic Operation Flow in Free-Running Mode
505
Figure 11-30: Basic Operation Timing in Free-Running Mode (Compare Function)
507
Figure 11-31: Basic Operation Timing in Free-Running Mode (Capture Function)
508
Figure 11-32: Basic Operation Timing in Free-Running Mode (Compare/Capture Function)
509
Pulse Width Measurement Mode
511
Figure 11-33: Basic Operation Timing in Pulse Width Measurement Mode
511
Triangular Wave PWM Mode
512
Figure 11-34: Basic Operation Timing in Triangular Wave PWM Mode
513
Encoder Count Function
514
Figure 11-35: Encoder Count Function Up/Down Count Selection Specification Timings (1/6)
516
Figure 11-36: Counter Clearing to 0000H through Encoder Clear Input (Pin Tecrtn)
523
Figure 11-37: Counter Hold through Bit Ttnecc Timings (1/5)
527
Offset Trigger Generation Mode
532
Figure 11-38: Basic Timing in Offset Trigger Generation Mode
533
Chapter 12 16-Bit 2-Phase Encoder Input Up/Down Counter/General Purpose
535
Timer (TMENC10) (Μpd70F3187 Only)
535
Features
535
Function Outline
535
Basic Configuration
537
Table 12-1: Timer ENC10 Configuration List
537
Figure 12-1: Block Diagram of Timer ENC10 (TMENC10)
538
Figure 12-2: Timer ENC10 (TMENC10)
539
Table 12-2: Timer ENC10 (TMENC10) Clear Conditions
540
Figure 12-3: Compare Register 100 (CM100)
541
Figure 12-4: Compare Register 101 (CM101)
542
Figure 12-5: Capture/Compare Register 100 (CC100)
543
Figure 12-6: Capture/Compare Register 101 (CC101)
544
Control Registers
545
Figure 12-7: Timer Unit Mode Register 10 (TUM10)
545
Figure 12-8: Timer Control Register 10 (TMC10) (1/2)
546
Figure 12-9: Capture/Compare Control Register 10(CCR10)
548
Figure 12-10: Signal Edge Selection Register 10 (SESA10) (1/2)
549
Figure 12-11: Prescaler Mode Register 10 (PRM10)
551
Figure 12-12: Status Register 10 (STATUS10)
553
Operation
554
Basic Operation
554
Operation in General-Purpose Timer Mode
555
Figure 12-13: TMENC10 Block Diagram (During PWM Output Operation)
556
Table 12-3: Capture Trigger Signal to 16-Bit Capture Register
556
Figure 12-14: PWM Signal Output Example (When ALVT10 Bit = 0 Is Set)
557
Operation in UDC Mode
558
Table 12-4: List of Count Operations in UDC Mode
558
Figure 12-15: Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin)
559
Figure 12-16: Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin): in Case of Simultaneous TIUD1, TCUD1 Pin Edge Timing
559
Figure 12-17: Mode 2 (When Rising Edge Is Specified as Valid Edge of TIUD1, TCUD1 Pins)
560
Figure 12-18: Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin)
561
Figure 12-19: Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin): in Case of Simultaneous TIUD1, TCUD1 Pin Edge Timing
561
Figure 12-20: Mode 4
562
Figure 12-21: Example of TMENC10 Operation When Interval Operation and Transfer Operation Are Combined
563
Figure 12-22: Example of Tm1Operation in UDC Mode
564
Supplementary Description of Internal Operation
566
Clearing of Count Value in UDC Mode B
566
Figure 12-23: Clear Operation Upon Match with CM100 During TMENC10 up Count Operation
566
Figure 12-24: Clear Operation Upon Match with CM101 During TMENC10 down Count Operation
566
Clearing of Count Value Upon Occurrence of Compare Match
567
Transfer Operation
567
Figure 12-25: Count Value Clear Operation Upon Compare Match
567
Figure 12-26: Internal Operation During Transfer Operation
567
Interrupt Signal Output Upon Compare Match
568
TM1UBD Flag (Bit 0 of STATUS Register) Operation
568
Figure 12-27: Interrupt Output Upon Compare Match (CM101 with Operation Mode Set to General-Purpose Timer Mode and Count Clock Set to F XX /8)
568
Figure 12-28: Tm1Ubdn Flag Operation
568
Chapter 13 Auxiliary Frequency Output Function (AFO)
569
Features
569
Configuration
569
Figure 13-1: Block Diagram of Auxiliary Frequency Output Function
569
Table 13-1: AFO Configuration
569
Control Registers
570
Figure 13-2: Prescaler Mode Register 2 (PRSM2)
570
Figure 13-3: Prescaler Compare Register 2 (PRSCM2)
571
Operation
572
Auxiliary Frequency Output
572
Auxiliary Frequency Generation
572
Interval Timer Function
572
Chapter 14 A/D Converter
573
Features
573
Configuration
574
Figure 14-1: Block Diagram of A/D Converter (Adcn)
575
Control Registers
576
Figure 14-2: A/D Converter N Mode Register 0 (Admn0)
576
Figure 14-3: A/D Converter N Mode Register 1 (Admn1) (1/2)
577
Figure 14-4: A/D Converter N Mode Register 2 (Admn2)
579
Figure 14-5: A/D Converter N Trigger Source Select Register (Adtrseln)
580
Figure 14-6: A/D Conversion Result Registers N0 to N9, N0H to N9H (Adcrn0 to Adcrn9, Adcrn0H to Adcrn9H)
581
Table 14-1: Assignment of A/D Conversion Result Registers to Analog Input Pins
582
Figure 14-7: Relationship between Analog Input Voltage and A/D Conversion Results
583
Figure 14-8: A/D Conversion Result Registers N0 to N9, N0H to N9H (Adcrn0 to Adcrn9, Adcrn0H to Adcrn9H)
584
Operation
585
Basic Operation
585
Operation Mode and Trigger Mode
586
Table 14-2: Relationship between Operation Mode and Trigger Mode
586
Figure 14-9: Select Mode Operation Timing: 1-Buffer Mode (Anin1)
588
Figure 14-10: Select Mode Operation Timing: 4-Buffer Mode (Anin2)
589
Figure 14-11: Scan Mode Operation Timing: 4-Channel Scan (ANI0 to ANI3)
590
Operation in A/D Trigger Mode
591
Select Mode Operation
591
Figure 14-12: Example of 1-Buffer Mode Operation (A/D Trigger Select: 1 Buffer)
591
Table 14-3: Correspondence between Analog Input Pins and Adcrnm Register (A/D Trigger Select: 1 Buffer)
591
Table 14-4: Correspondence between Analog Input Pins and Adcrnm Register (A/D Trigger Select: 4 Buffers)
592
Figure 14-13: Example of 4-Buffer Mode Operation (A/D Trigger Select: 4 Buffers)
593
Scan Mode Operations
594
Table 14-5: Correspondence between Analog Input Pins and Adcrnm Register (A/D Trigger Scan)
594
Figure 14-14: Example of Scan Mode Operation (A/D Trigger Scan)
595
Operation in Timer Trigger Mode
596
Select Mode Operation
596
Figure 14-15: Example of 1-Buffer Mode Operation (Timer Trigger Select: 1 Buffer) (Anin1)
597
Table 14-6: Correspondence between Analog Input Pins and Adcrnm Register (1-Buffer Mode (Timer Trigger Select: 1 Buffer))
597
Table 14-7: Correspondence between Analog Input Pins and Adcrnm Register (4-Buffer Mode (Timer Trigger Select: 4 Buffers))
598
Figure 14-16: Example of 4-Buffer Mode Operation (Timer Trigger Select: 4 Buffers) (Anin3)
599
Scan Mode Operation
600
Table 14-8: Correspondence between Analog Input Pins and Adcrnm Register (Scan Mode (Timer Trigger Scan))
600
Figure 14-17: Example of Scan Mode Operation (Timer Trigger Scan) (Anin0 to Anin4)
601
Operation in External Trigger Mode
602
Select Mode Operations
602
Table 14-9: Correspondence between Analog Input Pins and Adcrnm Register (External Trigger Select: 1 Buffer)
602
Figure 14-18: Example of 1-Buffer Mode Operation (External Trigger Select: 1 Buffer) (Anin1)
603
Table 14-10: Correspondence between Analog Input Pins and Adcrnm Register (External Trigger Select: 4 Buffers))
604
Figure 14-19: Example of 4-Buffer Mode Operation (External Trigger Select: 4 Buffers) (Anin2)
605
Scan Mode Operation
606
Table 14-11: Correspondence between Analog Input Pins and Adcrnm Register (External Trigger Scan)
606
Figure 14-20: Example of Scan Mode Operation (External Trigger Scan) (Anin0 to Anin3)
607
Precautions
608
Chapter 15 Asynchronous Serial Interface C (UARTC)
609
Features
609
Configuration
610
Figure 15-1: Block Diagram of Asynchronous Serial Interface N
611
Control Registers
612
Figure 15-2: Uartcn Control Register 0 (Ucnctl0) (1/2)
612
Figure 15-3: Uartcn Control Register 1 (Ucnctl1)
614
Figure 15-4: Uartcn Control Register 2 (Ucnctl2)
615
Figure 15-5: Uartcn Option Control Register 0 (Ucnopt0) (1/2)
616
Figure 15-6: Uartcn Option Control Register 1 (Ucnopt1)
618
Table 15-1: Relation between Uartcn Register Settings and Data Format
619
Figure 15-7: Uartcn Status Register (Ucnstr) (1/2)
620
Figure 15-8: Uartcn Status Register 1 (Ucnstr1)
622
Figure 15-9: Uartcn Receive Data Register (Ucnrx, Ucnrxl)
623
Figure 15-10: Uartcn Transmit Data Register (Ucntx, Ucntxl)
624
Interrupt Requests
625
Table 15-2: Default Priorities of Uartcn Interrupts
625
Operation
626
Data Format
626
Figure 15-11: UARTC Transmit/Receive Data Format (1/2)
626
SBF Transmission/Reception Format
628
Figure 15-12: LIN Transmission Manipulation Outline
628
Figure 15-13: LIN Reception Manipulation Outline
629
SBF Transmit Operation
630
Figure 15-14: SBF Transmission Timing
630
SBF Receive Operation
631
Figure 15-15: SBF Reception Timing
631
UART Transmit Operation
632
Figure 15-16: UART Transmission
632
Continuous Transmit Operation
633
Figure 15-17: Continuous Transmission Processing Flow
633
Figure 15-18: Continuous Transfer Operation Timing
634
UART Receive Operation
635
Figure 15-19: UART Reception Timing
635
Receive Error
636
Table 15-3: Reception Error Causes
636
Parity Types and Operations
637
Receive Data Noise Filter
638
Figure 15-20: Noise Filter Circuit
638
Dedicated Baud Rate Generator
639
Baud Rate Generator Configuration
639
Figure 15-21: Configuration of Baud Rate Generator
639
Baud Rate
640
Baud Rate Error
640
Baud Rate Setting Example
641
Table 15-4: Baud Rate Generator Setting Data
641
Allowable Baud Rate Range During Reception
642
Figure 15-22: Allowable Baud Rate Range During Reception
642
Table 15-5: Maximum/Minimum Allowable Baud Rate Error
643
Baud Rate During Continuous Transmission
644
Figure 15-23: Transfer Rate During Continuous Transfer
644
Chapter 16 Clocked Serial Interface B (CSIB)
645
Features
645
Configuration
645
Table 16-1: Csibn Configuration
645
Figure 16-1: Block Diagram of Csibn
646
Figure 16-2: Csibn Receive Data Register (Cbnrx, Cbnrxl)
647
Figure 16-3: Csibn Transmit Data Register (Cbntx, Cbntxl)
648
Control Registers
649
Figure 16-4: Csibn Control Register 0 (Cbnctl0) (1/2)
649
Figure 16-5: Csibn Control Register 1 (Cbnctl1)
651
Figure 16-6: Csibn Control Register 2 (Cbnctl2)
652
Figure 16-7: Effect of Transfer Data Length Setting
653
Figure 16-8: Csibn Status Register (Cbnstr)
654
Operation
655
Single Transfer Mode (Master Mode, Transmission/Reception Mode)
655
Figure 16-9: Single Transfer Mode (Master Mode, Transmission/Reception Mode)
655
Single Transfer Mode (Master Mode, Transmission Mode)
656
Figure 16-10: Single Transfer Mode (Master Mode, Transmission Mode)
656
Single Transfer Mode (Master Mode, Reception Mode)
657
Figure 16-11: Single Transfer Mode (Master Mode, Reception Mode)
657
Continuous Mode (Master Mode, Transmission/Reception Mode)
658
Figure 16-12: Continuous Mode (Master Mode, Transmission/Reception Mode)
658
Continuous Mode (Master Mode, Transmission Mode)
659
Figure 16-13: Continuous Mode (Master Mode, Transmission Mode)
659
Continuous Mode (Master Mode, Reception Mode)
660
Figure 16-14: Continuous Mode (Master Mode, Reception Mode)
660
Continuous Reception Mode (Error)
661
Figure 16-15: Continuous Reception Mode (Error)
661
Continuous Mode (Slave Mode, Transmission/Reception Mode)
662
Figure 16-16: Continuous Mode (Slave Mode, Transmission/Reception Mode)
662
Continuous Mode (Slave Mode, Reception Mode)
663
Figure 16-17: Continuous Mode (Slave Mode, Reception Mode)
663
Clock Timing
664
Figure 16-18: Csibn Clock Timing (1/2)
664
Output Pins
666
Operation Flow
667
Figure 16-19: Operation Flow of Single Transmission
667
Figure 16-20: Operation Flow of Single Reception (Master)
668
Figure 16-21: Operation Flow of Single Reception (Slave)
669
Figure 16-22: Operation Flow of Continuous Transmission
670
Figure 16-23: Operation Flow of Continuous Reception (Master)
671
Figure 16-24: Operation Flow of Continuous Reception (Slave)
672
Baud Rate Generator
673
Configuration
673
Figure 16-25: Block Diagram of Baud Rate Generators 0 and 1 (BRG0, BRG1)
673
Figure 16-26: Block Diagram of Csibn Baud Rate Generators
673
Control Registers
674
Figure 16-27: Prescaler Mode Registers 0 and 1 (PRSM0, PRSM1)
674
Figure 16-28: Prescaler Compare Registers 0 and 1 (PRSCM0, PRSCM1)
675
Baud Rate Generation
676
Cautions
676
Chapter 17 Clocked Serial Interface 3 (CSI3)
677
Features
677
Configuration
678
Figure 17-1: Block Diagram of Clocked Serial Interface 3N (Csi3N)
679
Control Registers
680
Figure 17-2: Clocked Serial Interface Mode Register 3N (Csim3N) (1/2)
680
Figure 17-3: Clocked Serial Interface Clock Select Register 3N (Csic3N) (1/3)
682
Figure 17-4: Receive Data Buffer Register 3N (Sirb3N, Sirb3Nl, Sirb3Nh)
685
Figure 17-5: Chip Select CSI Buffer Register 3N (Sfcs3N, Sfcs3Nl)
686
Figure 17-6: Transmit Data CSI Buffer Register 3N (Sfdb3N, Sfdb3Nl, Sfdb3Nh)
687
Figure 17-7: CSIBUF Status Register 3N (Sfa3N)(1/3)
688
Figure 17-8: Transfer Data Length Select Register 3N (Csil3N)
691
Figure 17-9: Transfer Data Number Specification Register 3N (Sfn3N)
692
Dedicated Baud Rate Generator 3N (Brg3N)
693
Figure 17-10: Transfer Clock of Csi3N
693
Operation
695
Operation Modes
695
Table 17-1: Operation Modes
695
Function of CSI Data Buffer Register (Csibufn)
696
Figure 17-11: Function of CSI Data Buffer Register N (Csibufn)
696
Data Transfer Direction Specification Function
697
Figure 17-12: Data Transfer Direction Specification (MSB First)
697
Figure 17-13: Data Transfer Direction Specification (LSB First)
698
Transfer Data Length Changing Function
699
Figure 17-14: Transfer Data Length Changing Function
699
Function to Select Serial Clock and Data Phase
700
Figure 17-15: Clock Timing
700
Master Mode
701
Figure 17-16: Master Mode
701
Slave Mode
702
Figure 17-17: Slave Mode
702
Table 17-2: Conditions under Which Data Can be Transferred in Slave Mode
702
Transfer Clock Selection Function
703
Single Mode
703
Figure 17-18: Single Mode
704
Consecutive Mode
705
Figure 17-19: Consecutive Mode
706
Transmission Mode
707
Reception Mode
707
Transmission/Reception Mode
707
Delay Control of Transmission/Reception Completion Interrupt (Intc3N)
708
Figure 17-20: Delay Control of Transmission/Reception Completion Interrupt (Intc3N)
708
Transfer Wait Function
709
Figure 17-21: Transfer Wait Function (1/3)
709
Output Pins
712
Table 17-3: Default Output Level of Sck3N Pin
712
Table 17-4: Default Output Level of So3N Pin
712
Csibufn Overflow Interrupt Signal (Intc3Novf)
713
Table 17-5: Default Output Level of Scs3N0 to Scs3N3 Pins
713
Operating Procedures
714
Single Mode (Master Mode, Transmission Mode)
714
Figure 17-22: Single Mode (Master Mode, Transmission Mode)
714
Single Mode (Master Mode, Reception Mode)
716
Figure 17-23: Single Mode (Master Mode, Reception Mode)
716
Single Mode (Master Mode, Transmission/Reception Mode)
718
Figure 17-24: Single Mode (Master Mode, Transmission/Reception Mode)
718
Single Mode (Slave Mode, Transmission Mode)
720
Figure 17-25: Single Mode (Slave Mode, Transmission Mode)
720
Single Mode (Slave Mode, Reception Mode)
722
Figure 17-26: Single Mode (Slave Mode, Reception Mode)
722
Single Mode (Slave Mode, Transmission/Reception Mode)
724
Figure 17-27: Single Mode (Slave Mode, Transmission/Reception Mode)
724
Consecutive Mode (Master Mode, Transmission Mode)
726
Figure 17-28: Consecutive Mode (Master Mode, Transmission Mode)
726
Consecutive Mode (Master Mode, Reception Mode)
728
Figure 17-29: Consecutive Mode (Master Mode, Reception Mode)
728
Consecutive Mode (Master Mode, Transmission/Reception Mode)
730
Figure 17-30: Consecutive Mode (Master Mode, Transmission/Reception Mode)
730
Consecutive Mode (Slave Mode, Transmission Mode)
732
Figure 17-31: Consecutive Mode (Slave Mode, Transmission Mode)
732
Consecutive Mode (Slave Mode, Reception Mode)
734
Figure 17-32: Consecutive Mode (Slave Mode, Reception Mode)
734
Consecutive Mode (in Slave Mode and Transmission/Reception Mode)
736
Figure 17-33: Consecutive Mode (Slave Mode, Transmission/Reception Mode)
736
Cautions
738
Chapter 18 AFCAN Controller
739
Features
739
Overview of Functions
740
Table 18-1: Overview of Functions
740
Configuration
741
Figure 18-1: Block Diagram of CAN Module
741
CAN Protocol
742
Frame Format
742
Figure 18-2: Composition of Layers
742
Frame Types
743
Data Frame and Remote Frame
743
Figure 18-3: Data Frame
743
Table 18-2: Frame Types
743
Figure 18-4: Remote Frame
744
Figure 18-5: Start of Frame (SOF)
744
Figure 18-6: Arbitration Field (in Standard Format Mode)
745
Figure 18-7: Arbitration Field (in Extended Format Mode)
745
Table 18-3: RTR Frame Settings
745
Figure 18-8: Control Field
746
Table 18-4: Frame Format Setting (IDE Bit) and Number of Identifier (ID) Bits
746
Table 18-5: Data Length Setting
746
Figure 18-9: Data Field
747
Figure 18-10: CRC Field
747
Figure 18-11: ACK Field
748
Figure 18-12: End of Frame (EOF)
748
Figure 18-13: Interframe Space (Error Active Node)
749
Figure 18-14: Interframe Space (Error Passive Node)
749
Error Frame
750
Figure 18-15: Error Frame
750
Table 18-6: Operation in Error Status
750
Table 18-7: Definition of Error Frame Fields
750
Overload Frame
751
Figure 18-16: Overload Frame
751
Table 18-8: Definition of Overload Frame Fields
751
Chapter 3 Functions
752
Determining Bus Priority
752
Bit Stuffing
752
Table 18-9: Determining Bus Priority
752
Table 18-10: Bit Stuffing
752
Multi Masters
753
Multi Cast
753
CAN Sleep Mode/Can Stop Mode Function
753
Error Control Function
753
Table 18-11: Error Types
753
Table 18-12: Output Timing of Error Frame
754
Table 18-13: Types of Error States
755
Table 18-14: Error Counter
756
Figure 18-17: Recovery from Bus-Off State through Normal Recovery Sequence
758
Baud Rate Control Function
759
Figure 18-18: Segment Setting
759
Table 18-15: Segment Setting
759
Figure 18-19: Configuration of Data Bit Time Defined by CAN Specification
760
Table 18-16: Configuration of Data Bit Time Defined by CAN Specification
760
Figure 18-20: Adjusting Synchronization of Data Bit
761
Figure 18-21: Re-Synchronization
762
Connection with Target System
763
Figure 18-22: Connection to CAN Bus
763
Internal Registers of CAN Controller
764
CAN Module Register and Message Buffer Addresses
764
Table 18-17: CAN Module Base Addresses
764
CAN Controller Configuration
765
Table 18-18: List of CAN Controller Registers
765
CAN Registers Overview
766
Table 18-19: CAN0 Global and Module Registers
766
Register Bit Configuration
767
Table 18-20: CAN0 Message Buffer Registers
767
Table 18-21: CAN Global Register Bit Configuration
767
Table 18-22: CAN Module Register Bit Configuration
768
Table 18-23: Message Buffer Register Bit Configuration
770
Bit Set/Clear Function
771
Figure 18-23: Example of Bit Setting/Clearing Operations
771
Control Registers
773
Figure 18-24: CAN Module Clock
791
Figure 18-25: Data Bit Time
792
CAN Controller Initialization
807
Initialization of CAN Module
807
Initialization of Message Buffer
807
Redefinition of Message Buffer
807
Transition from Initialization Mode to Operation Mode
808
Figure 18-26: Setting Transmission Request (TRQ) to Transmit Message Buffer after Redefinition
808
Resetting Error Counter Cnerc of CAN Module
809
Figure 18-27: Transition to Operation Modes
809
Message Reception
810
Receive Data Read
810
Receive History List Function
811
Figure 18-28: DN and MUC Bit Setting Period (for Standard ID Format)
811
Figure 18-29: Receive History List
812
Mask Function
813
Multi Buffer Receive Block Function
814
Remote Frame Reception
815
Message Transmission
816
Figure 18-30: Message Processing Example
816
Transmit History List Function
817
Automatic Block Transmission (ABT)
819
Figure 18-31: Transmit History List
819
Transmission Abort Process
820
Remote Frame Transmission
821
Power Saving Modes
822
CAN Sleep Mode
822
CAN Stop Mode
824
Example of Using Power Saving Modes
825
Interrupt Function
827
Table 18-1: List of CAN Module Interrupt Sources
827
Diagnosis Functions and Special Operational Modes
828
Receive-Only Mode
828
Figure 18-32: CAN Module Terminal Connection in Receive-Only Mode
828
Single-Shot Mode
829
Self-Test Mode
829
Receive/Transmit Operation in each Operation Mode
830
Figure 18-33: CAN Module Terminal Connection in Self-Test Mode
830
Table 18-2: Outline of the Receive/Transmit in each Operation Mode
830
Time Stamp Function
831
Figure 18-34: Timing Diagram of Capture Signal TSOUT
831
Baud Rate Settings
832
Baud Rate Setting Conditions
832
Table 18-3: Settable Bit Rate Combinations
833
Representative Examples of Baud Rate Settings
836
Table 18-4: Representative Examples of Baud Rate Settings (Fcanmod = 8 Mhz)
836
Table 18-5: Representative Examples of Baud Rate Settings (Fcanmod = 16 Mhz)
838
Operation of CAN Controller
840
Figure 18-35: Initialization
840
Figure 18-36: Re-Initialization
841
Figure 18-37: Message Buffer Initialization
842
Figure 18-38: Message Buffer Redefinition
843
Figure 18-39: Message Buffer Redefinition During Transmission
844
Figure 18-40: Message Transmit Processing
845
Figure 18-41: ABT Message Transmit Processing
846
Figure 18-42: Transmission Via Interrupt (Using Cnlopt Register)
847
Figure 18-43: Transmission Via Interrupt (Using Cntgpt Register)
848
Figure 18-44: Transmission Via Software Polling
849
Figure 18-45: Transmission Abort Processing (Except Normal Operation Mode with ABT)
850
Figure 18-46: Transmission Abort Processing Except for ABT Transmission (Normal Operation Mode with ABT)
850
Figure 18-47: Transmission Abort Processing (Normal Operation Mode with ABT)
852
Figure 18-48: Transmission Request Abort Processing (Normal Operation Mode with ABT)
853
Figure 18-49: Reception Via Interrupt (Using Cnlipt Register)
854
Figure 18-50: Reception Via Interrupt (Using Cnrgpt Register)
855
Figure 18-51: Reception Via Software Polling
856
Figure 18-52: Setting CAN Sleep Mode/Stop Mode
857
Figure 18-53: Clear CAN Sleep/Stop Mode
858
Figure 18-54: Bus-Off Recovery (Except Normal Operation Mode with ABT)
859
Figure 18-55: Bus-Off Recovery (Normal Operation Mode with ABT)
860
Figure 18-56: Normal Shutdown Process
861
Figure 18-57: Forced Shutdown Process
861
Figure 18-58: Error Handling
862
Figure 18-59: Setting CPU Stand-By (from CAN Sleep Mode)
863
Figure 18-60: Setting CPU Stand-By (from CAN Stop Mode)
864
Chapter 19 Random Number Generator (Μpd70F3187 Only)
865
Features
865
Configuration
865
Figure 19-1: Random Number Register (RNG)
865
Operation
866
Access Timing
866
Chapter 20 Port Functions
867
Features
867
Port Configuration
868
Figure 20-1: Port Configuration
868
Function of each Port
869
Table 20-1: Port Type and Function Overview
869
Port Types
870
Figure 20-2: Port Type 1
870
Figure 20-3: Port Type 1S
871
Figure 20-4: Port Type 1E
872
Figure 20-5: Port Type 2
873
Figure 20-6: Port Type 2A
874
Figure 20-7: Port Type 2C
875
Figure 20-8: Port Type 3
876
Figure 20-9: Port Type 4
877
Figure 20-10: Port Type 4C
878
Figure 20-11: Port Type 5
879
Figure 20-12: Port Type 6
880
Figure 20-13: Port Type 7
881
Figure 20-14: Port Type 8
882
Figure 20-15: Port Type 9
883
Figure 20-16: Port Type 10
884
Figure 20-17: Port Type 11
885
Figure 20-18: Port Type 12
886
Figure 20-19: Port Type 13
888
Figure 20-20: Port Type 14
890
Figure 20-21: Port Type 15
891
Figure 20-22: Port Type 15A
892
Peripheral Registers of I/O Ports
893
Table 20-2: Peripheral Registers of I/O Ports
893
Peripheral Registers of Valid Edge Control
896
Table 20-3: Peripheral Registers of Valid Edge Control
896
Port Pin Functions
897
Port 0
897
Figure 20-23: Port Register 0 (P0)
897
Table 20-4: Alternate Function Pins and Port Types of Port 0
897
Port 1
898
Table 20-5: Alternate Function Pins and Port Types of Port 1
898
Figure 20-24: Port Register 1 (P1)
899
Figure 20-25: Port Mode Register 1 (PM1)
899
Figure 20-26: Port Mode Control Register 1 (PMC1) (1/2)
900
Port 2
902
Table 20-6: Alternate Function Pins and Port Types of Port 2
902
Figure 20-27: Port Register 2 (P2)
903
Figure 20-28: Port Mode Register 2 (PM2)
903
Figure 20-29: Port Mode Control Register 2 (PMC2) (1/2)
904
Port 3
906
Table 20-7: Alternate Function Pins and Port Types of Port 3
906
Figure 20-30: Port Register 3 (P3)
907
Figure 20-31: Port Mode Register 3 (PM3)
907
Figure 20-32: Port Mode Control Register 3 (PMC3) (1/2)
908
Port 4
910
Table 20-8: Alternate Function Pins and Port Types of Port 4
910
Figure 20-33: Port Register 4 (P4)
911
Figure 20-34: Port Mode Register 4 (PM4)
911
Figure 20-35: Port Mode Control Register 4 (PMC4)
912
Port 5
913
Table 20-9: Alternate Function Pins and Port Types of Port 5
913
Figure 20-36: Port Register 5 (P5)
914
Figure 20-37: Port Mode Register 5 (PM5)
914
Figure 20-38: Port Mode Control Register 5 (PMC5))
915
Figure 20-39: Port Emergency Shut off Control Register 5 (PESC5)
916
Figure 20-40: Port Emergency Shut off Status Register 5 (ESOST5))
917
Port 6
918
Table 20-10: Alternate Function Pins and Port Types of Port 6
918
Figure 20-41: Port Register 6 (P6)
919
Figure 20-42: Port Mode Register 6 (PM6)
919
Figure 20-43: Port Mode Control Register 6 (PMC6) (1/2)
920
Figure 20-44: Port Emergency Shut off Control Register 6 (PESC6)
922
Figure 20-45: Port Emergency Shut off Status Register 6 (ESOST6))
923
Port 7
924
Table 20-11: Alternate Function Pins and Port Types of Port 7
924
Figure 20-46: Port Register 7 (P7)
925
Figure 20-47: Port Mode Register 7 (PM7)
925
Figure 20-48: Port Mode Control Register 7 (PMC7) (1/2)
926
Port 8
928
Table 20-12: Alternate Function Pins and Port Types of Port 8
928
Figure 20-49: Port Register 8 (P8)
929
Figure 20-50: Port Mode Register 8 (PM8)
929
Figure 20-51: Port Mode Control Register 8 (PMC8) (1/2)
930
Port 9
932
Table 20-13: Alternate Function Pins and Port Types of Port 9
932
Figure 20-52: Port Register 9 (P9)
933
Figure 20-53: Port Mode Register 9 (PM9)
933
Figure 20-54: Port Mode Control Register 9 (PMC9) (1/2)
934
Port 10
936
Table 20-14: Alternate Function Pins and Port Types of Port 10
936
Figure 20-55: Port Register 10 (P10)
937
Figure 20-56: Port Mode Register 10 (PM10)
937
Figure 20-57: Port Mode Control Register 10 (PMC10)
938
Port al
939
Table 20-15: Alternate Function Pins and Port Types of Port al
939
Figure 20-58: Port Register al(PAL)
940
Figure 20-59: Port Mode Register al(PMAL)
941
Figure 20-60: Port Mode Control Register al (PMCAL)
942
Port AH
943
Figure 20-61: Port Register AH (PAH)
943
Table 20-16: Alternate Function Pins and Port Types of Port AH
943
Figure 20-62: Port Mode Register AH (PMAH)
944
Figure 20-63: Port Mode Control Register AH (PMCAH)
944
Port DL
945
Table 20-17: Alternate Function Pins and Port Types of Port DL
945
Figure 20-64: Port Register DL(PDL)
946
Figure 20-65: Port Mode Register DL(PMDL)
947
Figure 20-66: Port Mode Control Register DL (PMCDL)
948
Port DH
949
Table 20-18: Alternate Function Pins and Port Types of Port DH
949
Figure 20-67: Port Register DH(PDH)
950
Figure 20-68: Port Mode Register DH(PMDH)
951
Figure 20-69: Port Mode Control Register DH (PMCDH)
952
Port CS
953
Figure 20-70: Port Register CS (PCS)
953
Table 20-19: Alternate Function Pins and Port Types of Port CS
953
Figure 20-71: Port Mode Register CS (PMCS)
954
Figure 20-72: Port Mode Control Register CS (PMCCS)
954
Port CT
955
Figure 20-73: Port Register CT (PCT)
955
Table 20-20: Alternate Function Pins and Port Types of Port CT
955
Figure 20-74: Port Mode Register CT (PMCT)
956
Figure 20-75: Port Mode Control Register CT (PMCCT)
957
Port CM
958
Figure 20-76: Port Register CM (PCM)
958
Table 20-21: Alternate Function Pins and Port Types of Port CM
958
Figure 20-77: Port Mode Register CM (PMCM)
959
Figure 20-78: Port Mode Control Register CM (PMCCM)
960
Port CD
961
Figure 20-79: Port Register CD (PCD)
961
Table 20-22: Alternate Function Pins and Port Types of Port CD
961
Figure 20-80: Port Mode Register CD (PMCD)
963
Figure 20-81: Port Mode Control Register CD (PMCCD)
964
Noise Elimination
965
Table 20-23: Noise Elimination
965
Figure 20-82: Noise Elimination Control Register (NRC) (1/2)
967
Chapter 21 Reset Function
971
Features
971
Configuration
971
Operation
972
Figure 21-1: Reset Timing
972
Chapter 22 Internal RAM Parity Check Function
973
Features
973
Operation
973
Control Registers
974
Figure 22-1: Internal RAM Parity Error Status Register (RAMERR)
974
Figure 22-2: Internal RAM Parity Error Address Register (RAMPADD)
975
Chapter 23 On-Chip Debug Function (OCD)
977
Function Overview
977
On-Chip Debug Unit Type
977
Debug Function
977
Connection with N-Wire Type Emulator
979
KEL Connector
979
Figure 23-1: Connecting N-Wire Type Emulator (IE-V850E1-CD-NW (N-Wire Card))
979
Figure 23-2: Pin Configuration of Emulator Connector (on Target System Side)
980
Table 23-1: Pin Functions of Connector for IE-V850E1-CD-NW (on Target System Side)
981
Figure 23-3: Example of Recommended Emulator Connection of V850E/PH2
982
Precautions
983
Chapter 24 Flash Memory
985
Features
985
Memory Configuration
986
Figure 24-1: Flash Memory Mapping of Μpd70F3187
986
Figure 24-2: Flash Memory Mapping of Μpd70F3447
987
Functional Outline
988
Table 24-1: Rewrite Method
988
Table 24-2: Basic Functions
989
Table 24-3: Protection Functions
990
Rewriting by Dedicated Flash Programmer
991
Programming Environment
991
Figure 24-3: Environment Required for Writing Programs to Flash Memory
991
Communication Mode
992
Figure 24-4: Communication with Dedicated Flash Programmer (UARTC0)
992
Figure 24-5: Communication with Dedicated Flash Programmer (CSIB0)
992
Figure 24-6: Communication with Dedicated Flash Programmer (CSIB0 + HS)
993
Table 24-4: Signal Connections of Dedicated Flash Programmer (PG-FP4)
994
Flash Memory Control
995
Figure 24-7: Procedure for Manipulating Flash Memory
995
Selection of Communication Mode
996
Figure 24-8: Selection of Communication Mode
996
Communication Commands
997
Figure 24-9: Communication Commands
997
Table 24-5: Communication Commands
997
Pin Connection
998
Figure 24-10: FLMD0 Pin Connection Example
998
Figure 24-11: FLMD1 Pin Connection Example
999
Table 24-6: Relationship between FLMD0 and FLMD1 Pins and Operation Mode When Reset Is Released
999
Figure 24-12: Conflict of Signals (Serial Interface Input Pin)
1000
Table 24-7: Pins Used by Serial Interfaces
1000
Figure 24-13: Malfunction of Other Device
1001
Figure 24-14: Conflict of Signals (RESET Pin)
1002
Rewriting by Self Programming
1003
Overview
1003
Figure 24-15: Concept of Self Programming
1003
Features
1004
Figure 24-16: Rewriting Entire Memory Area (Boot Swap)
1005
Chapter 25 Electrical Specifications
1007
Absolute Maximum Ratings
1007
Table 25-1: Absolute Maximum Ratings
1007
General Characteristics
1008
Capacitance
1008
Operating Conditions
1008
Table 25-2: Capacitance
1008
Table 25-3: Operating Conditions
1008
Oscillator Characteristics
1009
Figure 25-1: Oscillator Recommendations
1009
Table 25-4: Oscillator Characteristics
1009
DC Characteristics
1010
Table 25-5: DC Characteristics
1010
AC Characteristics
1011
Figure 25-2: AC Test Input/Output Waveform
1011
Figure 25-3: AC Test Load Condition
1011
External Asynchronous Memory Access Read Timing
1012
Table 25-6: External Asynchronous Memory Access Read Timing
1012
Figure 25-4: External Asynchronous Memory Access Read Timing
1013
External Asynchronous Memory Access Write Timing
1014
Table 25-7: External Asynchronous Memory Access Write Timing
1014
Figure 25-5: External Asynchronous Memory Access Write Timing
1015
Reset Timing (Power Up/Down Sequence)
1016
Figure 25-6: Reset Timing
1016
Table 25-8: Reset Timing
1016
Interrupt Timing
1017
Figure 25-7: Interrupt Timing
1017
Table 25-9: Interrupt Timing
1017
Peripheral Characteristics
1018
Timer Characteristics
1018
Figure 25-8: Timer P Characteristics
1018
Table 25-10: Timer P Characteristics
1018
Figure 25-9: Timer R Characteristics
1019
Table 25-11: Timer R Characteristics
1019
Figure 25-10: Timer T Characteristics
1020
Table 25-12: Timer T Characteristics
1020
Serial Interface Characteristics
1021
Table 25-13: CSIB Characteristics (Master Mode)
1021
Table 25-14: CSIB Characteristics (Slave Mode)
1021
Figure 25-11: CSIB Timing in Master Mode (CKP, DAP Bits = 00B or 11B)
1022
Figure 25-12: CSIB Timing in Master Mode (CKP, DAP Bits = 01B or 10B)
1022
Figure 25-13: CSIB Timing in Slave Mode (CKP, DAP Bits = 00B or 11B)
1023
Figure 25-14: CSIB Timing in Slave Mode (CKP, DAP Bits = 01B or 10B)
1023
Table 25-15: CSI3 Characteristics (Master Mode)
1024
Table 25-16: CSI3 Characteristics (Slave Mode)
1024
Figure 25-15: CSI3 Timing in Master Mode (CKP, DAP Bits = 00B or 11B)
1025
Figure 25-16: CSI3 Timing in Master Mode (CKP, DAP Bits = 01B or 10B)
1025
Figure 25-17: CSI3 Timing in Slave Mode (CKP, DAP Bits = 00B or 11B)
1026
Figure 25-18: CSI3 Timing in Slave Mode (CKP, DAP Bits = 01B or 10B)
1026
Figure 25-19: CSI3 Chip Select Timing (Master Mode Only) (CSIT = 0, CSWE = 0, CSMD = 0)
1027
Figure 25-20: CSI3 Chip Select Timing (Master Mode Only) (CSIT = 0, CSWE = 1, CSMD = 0)
1027
Figure 25-21: CSI3 Chip Select Timing (Master Mode Only) (CSIT = 0, CSWE = 1, CSMD = 1)
1028
Figure 25-22: CSI3 Chip Select Timing (Master Mode Only) (CSIT = 1, CSWE = 0, CSMD = 0)
1028
Figure 25-23: CSI3 Chip Select Timing (Master Mode Only) (CSIT = 1, CSWE = 1, CSMD = 0)
1029
Figure 25-24: CSI3 Chip Select Timing (Master Mode Only) (CSIT = 1, CSWE = 1, CSMD = 1)
1029
A/D Converter Characteristics
1030
Figure 25-25: Equivalent Circuit of Analog Inputs
1030
Table 25-17: A/D Converter Characteristics
1030
Table 25-18: Analog Input Characteristics
1030
Flash Programming Characteristics
1031
Table 25-19: Flash Memory Basic Characteristics
1031
Table 25-20: Flash Memory Programming Characteristics
1031
Figure 25-26: Serial Write Operation Characteristics
1032
Table 25-21: Serial Write Operation Characteristics
1032
Chapter 26 Package Drawings
1033
Figure 26-1: 208-Pin Plastic QFP (Fine Pitch) (28 X 28)
1033
Figure 26-2: 256-Pin Plastic BGA (Fine Pitch) (21 X 21)
1034
Table 27-1: Soldering Conditions
1035
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