Page 1 User’s Manual V850E/PH2 32-Bit Single-Chip Microcontroller Hardware μPD70F3187 μPD70F3447 Document No. U16580EE3V1UD00 Date Published January 2007 © NEC Electronics Corporation 2007 Printed in Germany...
Page 2 All (other) product, brand, or trade names used in this pamphlet are the trademarks or registered trademarks of their respective owners. Product specifications are subject to change without notice. To ensure that you have the latest product data, please contact your local NEC Electronics sales office. User’s Manual U16580EE3V1UD00...
Page 3 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 4 Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [Asia & Oceania] [America] [Europe] NEC Electronics (China) Co., Ltd NEC Electronics America, Inc. NEC Electronics (Europe) GmbH 7th Floor, Quantum Plaza, No. 27 ZhiChunLu 2880 Scott Blvd. Arcadiastrasse 10 District, Beijing 100083, P.R.China Santa Clara, CA 95050-2554, U.S.A.
Page 5: Preface
Preface Readers This manual is intended for users who want to understand the functions of the V850E/PH2 (PHOENIX-F). Purpose This manual presents the hardware manual of V850E/PH2. Organization This system specification describes the following sections: • Pin function • CPU function •...
Page 6 Preface User’s Manual U16580EE3V1UD00...
Page 7: Table Of Contents
Table of Contents Preface ............5 Chapter 1 Introduction.
Page 8 Idle State Insertion Function..........176 Bus Priority Order .
Page 9 Control Registers ........... . . 264 Operation .
Page 10 11.6.1 Interval timer mode ..........487 11.6.2 External event count mode .
Page 11 15.3 Control Registers ........... . . 612 15.4 Interrupt Requests .
Page 12 17.5.9 Single mode ........... 703 17.5.10 Consecutive mode .
Page 13 18.9.2 Receive Data Read..........810 18.9.3 Receive history list function .
Page 14 20.3.17 Port CT ............955 20.3.18 Port CM.
Page 15 Chapter 27 Recommended Soldering Conditions ......1035 Appendix A Index ............1037 Appendix B Revision History .
Page 16 User’s Manual U16580EE3V1UD00...
Page 17 List of Figures Figure 1-1: Pin Configuration 208-pin Plastic LQFP ..............37 Figure 1-2: Pin Configuration 256-pin Plastic BGA (21 × 21) ............38 Figure 1-3: Internal Block Diagram of mPD70F3187 ..............44 Figure 1-4: Internal Block Diagram of mPD70F3447 ..............45 Figure 2-1: Pin I/O Circuits ......................
Page 18 Figure 6-12: Operation of DMA Channel 2/3 ................. 206 Figure 6-13: DMA Channel 2 and 3 Trigger Signal Timing ............207 Figure 6-14: Initialization of DMA Transfer for Serial Data Reception ........... 209 Figure 6-15: Operation of DMA Channel 4/5 ................. 210 Figure 6-16: DMA Channel 4 and 5 Trigger Signal Timing ............
Page 19 Figure 9-22: Flowchart of Basic Operation in External Trigger Pulse Output Mode ...... 287 Figure 9-23: Basic Operation Timing in External Trigger Pulse Output Mode ....... 288 Figure 9-24: Flowchart of Basic Operation in One-Shot Pulse Mode ..........290 Figure 9-25: Timing of Basic Operation in One-Shot Pulse Mode ..........
Page 20 in High-Accuracy T-PWM Mode / PWM Mode with Dead Time ........ 383 Figure 10-41: Basic Operation Flow in Interval Timer Mode............384 Figure 10-42: Basic Timing in Interval Timer Mode (1/2)..............386 Figure 10-43: Basic Operation Timing in External Event Count Mode (1/4) ........390 Figure 10-44: Basic Operation Flow in External Trigger Pulse Output Mode ........
Page 21 Figure 11-20: Basic Operation Flow in Interval Timer Mode............487 Figure 11-21: Basic Timing in Interval Timer Mode (1/2)..............488 Figure 11-22: Basic Operation Timing in External Event Count Mode (1/4) ........491 Figure 11-23: Basic Operation Flow in External Trigger Pulse Output Mode ........496 Figure 11-24: Basic Operation Timing in External Trigger Pulse Output Mode .......
Page 22 Figure 14-3: A/D Converter n Mode Register 1 (ADMn1) (1/2) ............. 577 Figure 14-4: A/D Converter n Mode Register 2 (ADMn2) ............579 Figure 14-5: A/D Converter n Trigger Source Select Register (ADTRSELn) ....... 580 Figure 14-6: A/D Conversion Result Registers n0 to n9, n0H to n9H (ADCRn0 to ADCRn9, ADCRn0H to ADCRn9H) .............
Page 23 Figure 16-16: Continuous Mode (Slave Mode, Transmission/Reception Mode) ......662 Figure 16-17: Continuous Mode (Slave Mode, Reception Mode)............ 663 Figure 16-18: CSIBn Clock Timing (1/2) ..................664 Figure 16-19: Operation Flow of Single Transmission..............667 Figure 16-20: Operation Flow of Single Reception (Master)............668 Figure 16-21: Operation Flow of Single Reception (Slave) .............
Page 24 Figure 18-13: Interframe space (error active node) ................. 749 Figure 18-14: Interframe space (error passive node) ..............749 Figure 18-15: Error frame ........................ 750 Figure 18-16: Overload frame......................751 Figure 18-17: Recovery from bus-off state through normal recovery sequence......758 Figure 18-18: Segment setting......................
Page 25 Figure 20-9: Port Type 4 ........................ 877 Figure 20-10: Port Type 4C ......................878 Figure 20-11: Port Type 5 ........................ 879 Figure 20-12: Port Type 6 ........................ 880 Figure 20-13: Port Type 7 ........................ 881 Figure 20-14: Port Type 8 ........................ 882 Figure 20-15: Port Type 9 ........................
Page 26 Connecting N-Wire Type Emulator (IE-V850E1-CD-NW (N-Wire Card)) ....979 Figure 23-2: Pin Configuration of Emulator Connector (on Target System Side) ......980 Figure 23-3: Example of Recommended Emulator Connection of V850E/PH2......982 Flash Memory Mapping of μPD70F3187..............986 Figure 24-1: Flash Memory Mapping of μPD70F3447..............987...
Page 27 Figure 25-21: CSI3 Chip Select Timing (Master Mode only) (CSIT = 0, CSWE = 1, CSMD = 1) .. 1028 Figure 25-22: CSI3 Chip Select Timing (Master Mode only) (CSIT = 1, CSWE = 0, CSMD = 0) .. 1028 Figure 25-23: CSI3 Chip Select Timing (Master Mode only) (CSIT = 1, CSWE = 1, CSMD = 0) ..
Page 28 User’s Manual U16580EE3V1UD00...
Page 29 List of Tables Table 1-1: Differences in Pin Assignment of 256-pin Plastic BGA ..........39 Table 2-1: Port Pins ......................... 49 Table 2-2: Non-Port Pins ......................... 54 Table 2-3: Pin Status in Reset and Standby Mode................60 Table 2-4: I/O Circuit Types......................76 Table 2-5: Noise Suppression Timing....................
Page 30 Table 14-7: Correspondence Between Analog Input Pins and ADCRnm Register (4-Buffer Mode (Timer Trigger Select: 4 Buffers)) ............598 Table 14-8: Correspondence Between Analog Input Pins and ADCRnm Register (Scan Mode (Timer Trigger Scan))................600 Table 14-9: Correspondence Between Analog Input Pins and ADCRnm Register (External Trigger Select: 1 Buffer) ................
Page 31 Table 20-8: Alternate Function Pins and Port Types of Port 4 ............910 Table 20-9: Alternate Function Pins and Port Types of Port 5 ............913 Table 20-10: Alternate Function Pins and Port Types of Port 6 ............918 Table 20-11: Alternate Function Pins and Port Types of Port 7 ............924 Table 20-12: Alternate Function Pins and Port Types of Port 8 ............
Page 32 User’s Manual U16580EE3V1UD00...
Page 33: Introduction
“V850 series™”. This chapter gives a short outline of the V850E/PH2 microcontroller. 1.1 Outline The V850E/PH2 is a 32-bit single-chip microcontroller that realizes high-precision inverter control of a motor due to high-speed operation. It uses the V850E1 CPU (NU85EFC) of the V850 Series including...
Page 34: Device Features
Chapter 1 Introduction 1.2 Device Features • Number of instructions: 15.625 ns (@ φ = 64 MHz) • Instruction execution time: • General-purpose registers: 32 bits × 32 • Instruction set: V850E1 CPU (NU85EFC) (compatible with V850 plus additional powerful instructions for reducing code and increasing execution speed) Single-precision floating point arithmetic operation Signed multiplication (16 bits ×...
Page 35 Chapter 1 Introduction • Timer: 16-bit timer for 3-phase PWM inverter control: 2 channels Note 1 16-bit up/down counter for 4-quadrant encoding: 1 channel 16-bit general purpose timers: 9 channels 16-bit general purpose timers with encoding capability: 2 channels • Serial interfaces: Asynchronous serial interface (UARTC): 2 channels Note 2...
Page 36: Applications
Chapter 1 Introduction 1.3 Applications The V850E/PH2 microcontroller is ideally suited for automotive applications, like electrical power steering and electric car control. It is also an excellent choice for other applications where a combination of general-purpose inverter control functions and CAN network support is required.
Page 37: Pin Configuration (Top View)
Chapter 1 Introduction 1.5 Pin Configuration (Top View) • 208-pin plastic LQFP (fine pitch) (28 × 28) μPD70F3187GD-64-LML μPD70F3187GD(A1)-64-LML μPD70F3187GD(A2)-64-LML Figure 1-1: Pin Configuration 208-pin Plastic LQFP PAH5/A21 P32/RXDC1/INTP5 PCS4/CS4 P31/TXDC0 PDL0/D0 P30/RXDC0/INTP4 PDL1/D1 P37/FCTXD1 PDL2/D2 P36/FCRXD1 PDL3/D3 P35/FCTXD0 P34/FCRXD0 DD35 SS35 SS32...
Page 38: Figure 1-2: Pin Configuration 256-Pin Plastic Bga (21 × 21)
Chapter 1 Introduction • 256-pin plastic BGA (21 × 21) μPD70F3187F1(A2)-JN4 μPD70F3447F1(A2)-JN4 Figure 1-2: Pin Configuration 256-pin Plastic BGA (21 × 21) Top View Bottom View A B C D E F G H J K L M N P R T U V W Y Y W V U T R P N M L K J H G F E D C B A Index mark Index mark...
Page 39: Table 1-1: Differences In Pin Assignment Of 256-Pin Plastic Bga
Chapter 1 Introduction Table 1-1: Differences in Pin Assignment of 256-pin Plastic BGA (1/4) Pin No Pin Function (Name) Pin No Pin Function (Name) μPD70F3187 μPD70F3447 μPD70F3187 μPD70F3447 PCT4/RD PCT4 PCD5/BEN3 PCD5 PCT5/WR PCT5 PCD2/BEN0 PCD2 PDH15/D31 PDH15 PCM6 PCM6 PDH13/D29 PDH13 PCM1...
Page 40 Chapter 1 Introduction Table 1-1: Differences in Pin Assignment of 256-pin Plastic BGA (2/4) Pin No Pin Function (Name) Pin No Pin Function (Name) μPD70F3187 μPD70F3447 μPD70F3187 μPD70F3447 PAH5/A21 PAH5 PAH3/A19 PAH3 PAL14/A14 PAL14 ANI00 ANI00 ANI03 ANI03 ANI02 ANI02 ANI06 ANI06 ANI01...
Page 41 Chapter 1 Introduction Table 1-1: Differences in Pin Assignment of 256-pin Plastic BGA (3/4) Pin No Pin Function (Name) Pin No Pin Function (Name) μPD70F3187 μPD70F3447 μPD70F3187 μPD70F3447 DD10 DD10 DD30 DD30 DD33 DD33 DD33 DD33 SS33 SS33 SS33 SS33 P41/SOB0 P41/SOB0 P96/SCS313/SSB1 P96...
Page 42 Chapter 1 Introduction Table 1-1: Differences in Pin Assignment of 256-pin Plastic BGA (4/4) Pin No Pin Function (Name) Pin No Pin Function (Name) μPD70F3187 μPD70F3447 μPD70F3187 μPD70F3447 P92/SCK31 P45/SCKB1 P27/TIP71/ P27/TIP71/ P72/TECRT0/ P72/INTP12 TEVTP6/TOP71 TEVTP6/TOP71 INTP12 P73/TIT10/TTRGT0/ P73/TIT10/TTRGT0/ P100/TCLR1/ P100/TOP81 TOT10/TENCT10 TOT10/TENCT10...
Page 43 Chapter 1 Introduction Pin Identification A0 to A21: Address bus SI30, SI31, ADTRG0, ADTRG1: A/D trigger input SIB0, SIB1: Serial data input AFO: Auxiliary frequency output SO30, SO31, ANI00 to ANI09, SOB0, SOB1: Serial data output ANI10 to ANI19: Analog input SSB0, SSB1: Serial slave select input Analog power supply...
Page 44: Function Blocks
Chapter 1 Introduction 1.6 Function Blocks 1.6.1 Internal block diagrams Figure 1-3: Internal Block Diagram of μPD70F3187 INTC MEMC INTP0 to INTP12 ESO0, ESO1 Instruction SRAM Queue TTRGR1 TIR10 to TIR13 32-bit 512 KB Barrel TIP00 to TIP70 Floating Point WAIT Shifter TIP01 to TIP71...
Page 45: Figure 1-4: Internal Block Diagram Of Mpd70F3447
Chapter 1 Introduction Figure 1-4: Internal Block Diagram of μPD70F3447 INTC INTP0 to INTP12 Instruction ESO0, ESO1 Queue TTRGR1 TIR10 to TIR13 32-bit 384 KB Barrel TIP00 to TIP70 Floating Point Shifter TIP01 to TIP71 Unit TEVTP0 to TEVTP8 System TTRGP0 to TTRGP8 Multiplier Registers...
Page 46: On-Chip Units
Chapter 1 Introduction 1.6.2 On-chip units The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits 32 bits →...
Page 47 Chapter 1 Introduction Clock generator (CG) The CG provides a frequency that is 4 times the input clock (f ) (using the on-chip PLL) as the internal system clock (f ). As the input clock, connect an external crystal or resonator to pins X1 and X2 or input an external clock from the X1 pin.
Page 48 Chapter 1 Introduction (13) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port Control Function μPD70F3187 μPD70F3447 Port 0 5-bit input NMI input, external interrupt input, A/D converter external trigger input, emergency shut-off input Port 1 8-bit I/O Real-time pulse unit I/O...
Page 49: Pin Functions
Chapter 2 Pin Functions 2.1 List of Pin Functions The names and functions of the V850E/PH2 microcontroller pins are listed below. These pins can be divided into port pins and non-port pins according to their functions. Port pins Table 2-1: Port Pins (1/5)
Page 50 Chapter 2 Pin Functions Table 2-1: Port Pins (2/5) Pin Name Function Alternate Function μPD70F3187 μPD70F3447 Port 4 SIB0 6-bit I/O port SOB0 Input or output direction can be specified in 1-bit SCKB0 units SIB1 – SOB1 – SCKB1 – Port 5 TOR00 8-bit I/O port...
Page 51 Chapter 2 Pin Functions Table 2-1: Port Pins (3/5) Pin Name Function Alternate Function μPD70F3187 μPD70F3447 Port 9 SI31 – 7-bit I/O port SO31 – Input or output direction can be specified in 1-bit SCK31 – units SCS310, INTP9 INTP9 SCS311, INTP10 INTP10 SCS312, INTP11...
Page 52 Chapter 2 Pin Functions Table 2-1: Port Pins (4/5) Pin Name Function Alternate Function μPD70F3187 μPD70F3447 PDL0 Port DL – 16-bit I/O port PDL1 Input or output direction can be specified in 1-bit PDL2 units PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10...
Page 53 Chapter 2 Pin Functions Table 2-1: Port Pins (5/5) Pin Name Function Alternate Function μPD70F3187 μPD70F3447 PCM0 Port CM WAIT – 4-bit I/O port PCM1 – Input or output direction can be specified in 1-bit PCM6 – units PCM7 – PCS0 Port CS –...
Page 54: Table 2-2: Non-Port Pins
Chapter 2 Pin Functions Non-port pins Table 2-2: Non-Port Pins (1/6) Pin Name Function Alternate Function μPD70F3187 μPD70F3447 Note 22-bit external address bus PAL0 to PAL15 A0 to A15 Note PAH0 to PAH5 A16 to A21 ADTRG0 A/D conversion start trigger (ADC0) P03, INTP2 ADTRG1 A/D conversion start trigger (ADC1)
Page 55 Chapter 2 Pin Functions Table 2-2: Non-Port Pins (2/6) Pin Name Function Alternate Function μPD70F3187 μPD70F3447 FLMD0 Flash programming mode selection MODE0 FLMD1 MODE1 INTP0 External maskable interrupt request input P01, ESO0 INTP1 P02, ESO1 INTP2 P03, ADTRG0 INTP3 P04, ADTRG1 INTP4 P30, RXDC0 INTP5...
Page 56 Chapter 2 Pin Functions Table 2-2: Non-Port Pins (3/6) Pin Name Function Alternate Function μPD70F3187 μPD70F3447 Note Serial data input (CSIB1) SIB1 SO30 Serial data output (CSI30) SO31 Serial data output (CSI31) SOB0 Serial data output (CSIB0) SOB1 Serial data output (CSIB1) SSB0 Serial slave select input (CSIB0) P86, SCS303...
Page 57 Chapter 2 Pin Functions Table 2-2: Non-Port Pins (4/6) Pin Name Function Alternate Function μPD70F3187 μPD70F3447 TIP40 Capture trigger input (TMP4) P20, TEVTP5, TOP40 TIP41 P21, TTRGP5, TOP41 TIP50 Capture trigger input (TMP5) P22, TTRGP4, TOP50 TIP51 P23, TEVTP4, TOP51 TIP60 Capture trigger input (TMP6) P24, TEVTP7, TOP60...
Page 58 Chapter 2 Pin Functions Table 2-2: Non-Port Pins (5/6) Pin Name Function Alternate Function μPD70F3187 μPD70F3447 TOR00 Pulse signal output (TMR0) TOR01 TOR02 TOR03 TOR04 TOR05 TOR06 TOR07 TOR10 Pulse signal output (TMR1) P60, TTRGR1 TOR11 P61, TIR10 TOR12 P62, TIR11 TOR13 P63, TIR12 TOR14...
Page 59 Chapter 2 Pin Functions Table 2-2: Non-Port Pins (6/6) Pin Name Function Alternate Function μPD70F3187 μPD70F3447 Note External wait control signal input PCM0 WAIT Note Write strobe signal output PCT5 Crystal connection – – – Note: Not available on μPD70F3447 User’s Manual U16580EE3V1UD00...
Page 60: Pin Status
Chapter 2 Pin Functions 2.2 Pin Status Table 2-3: Pin Status in Reset and Standby Mode Operating Status During After reset release HALT Mode reset Single-chip Single-chip ROM-less Mode 0 Note Note Mode 1 Mode A0 to A15 (PAL0 to PAL15) Hi-Z Hi-Z Operating...
Page 61: Description Of Pin Functions
Chapter 2 Pin Functions 2.3 Description of Pin Functions P00 to P04 (Port 0) … Input Port 0 is an 8-bit input-only port in which all pins are fixed for input. Besides functioning as a port, in control mode, P00 to P04 operate as NMI input, external interrupt request signal, real-time pulse unit (RPU) emergency shut off signal input, and A/D converter (ADC) external trigger input.
Page 62 Chapter 2 Pin Functions P10 to P17 (Port 1) … Input/Output Port 1 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P10 to P17 operate as RPU input or output. The operation mode can be specified by the port 1 mode control register (PMC1) to port or control mode for each port pin individually.
Page 63 Chapter 2 Pin Functions P30 to P37 (Port 3) … Input/Output Port 3 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P30 to P37 operate as serial interface Note (UARTC0, UARTC1, AFCAN0, AFCAN1 ).
Page 64 Chapter 2 Pin Functions P40 to P45 (Port 10) … Input/Output Port 4 is a 6-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P40 to P45 operate as serial interface (CSIB0, Note CSIB1 The operation mode can be specified by the port 4 mode control register (PMC4) to port or control...
Page 65 Chapter 2 Pin Functions P50 to P57 (Port 5) … Input/Output Port 5 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P50 to P57 operate as RPU input or output. The operation mode can be specified by the port 5 mode control register (PMC5) to port or control mode for each port pin individually.
Page 66 Chapter 2 Pin Functions P70 to P75 (Port 7) … Input/Output Port 7 is a 6-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P70 to P75 operate as RPU input or output, and auxiliary frequency output.
Page 67 Chapter 2 Pin Functions P80 to P86 (Port 8) … Input/Output Port 8 is a 7-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P80 to P86 operate as serial interface (CSI30, CSIB0).
Page 68 Chapter 2 Pin Functions (10) P90 to P96 (Port 9) … Input/Output Port 9 is a 7-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P90 to P96 operate as serial interface Note Note (CSI31...
Page 69 Chapter 2 Pin Functions (11) P100 to P102 (Port 10) … Input/Output Port 10 is a 3-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P100 to P102 operate as RPU input or output The operation mode can be specified by the port 10 mode control register (PMC10) to port or control mode for each port pin individually.
Page 70 Chapter 2 Pin Functions (13) PAH0 to PAH5 (Port AH) … I/O Port AH is a 6-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as the address bus (A16 to A21) when memory is expanded externally.
Page 71 Chapter 2 Pin Functions (15) PDH0 to PDH15 (Port DH) … I/O Port DH is an 8-bit or a 16-bit I/O port in which input or output can be set for each port pin individually. Note Besides functioning as a port, in control mode, these pins operate as the data bus (D16 to D31) when memory is expanded externally.
Page 72 Chapter 2 Pin Functions (17) PCM0, PCM1, PCM6, PCM7 (Port CM) … I/O Port CM is a 4-bit I/O port in which input or output can be set for each port pin individually. Note Besides functioning as a port, in control mode, these pins operate as control signal input when memory is expanded externally.
Page 73 Chapter 2 Pin Functions (19) PCT4, PCT5 (Port CT) … I/O Port CT is a 2-bit I/O port in which input or output can be set for each port pin individually. Note Besides functioning as a port, in control mode, these pins operate as control signal outputs when memory is expanded externally.
Page 74 Chapter 2 Pin Functions (20) DCK (Debug clock) … Input This pin inputs a debug clock. At the rising edge of the DCK signal, the DMS and DDI signals are sampled, and data is output from the DDO pin at the falling edge of the DCK signal. Keep this pin high when the debug function is not used.
Page 75 Chapter 2 Pin Functions (32) AV (Analog ground) This is the analog ground pin for the A/D converters. (33) CV (Power supply for clock generator) This is the positive power supply pin for the clock generator. (34) CV (Ground for clock oscillator) This is the ground pin for the clock generator.
Page 76: Pin I/O Circuits And Recommended Connection Of Unused Pins
Chapter 2 Pin Functions 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-4: I/O Circuit Types (1/4) Terminal I/O circuit type Recommended termination μPD70F3187 μPD70F3447 P00/NMI Connect independently to V via a resistor P01/INTP0/ESO0 P02/INTP1/ESO1 P03INTP2/ADTRG0 P04INTP3/ADTRG1 P10/TIP00/TEVTP1/TOP00 Input: Connect independently to V or V...
Page 77 Chapter 2 Pin Functions Table 2-4: I/O Circuit Types (2/4) Terminal I/O circuit type Recommended termination μPD70F3187 μPD70F3447 P60/TOR10/TTRGR1 Input: Connect independently to V or V via a resistor P61/TOR11/TIR10 Output: leave open P62/TOR12/TIR11 P63/TOR13/TIR12 P64/TOR14/TIR13 P65/TOR15 P66/TOR16 P67/TOR17/TEVTR1 P70/TIT00/TEVTT1/TOT00/TENCT00 P71/TIT01/TTRGT1/TOT01/TENCT01 P72/TECRT0/INTP12 P73/TIT10/TTRGT0/TOT10/TENCT10...
Page 78 Chapter 2 Pin Functions Table 2-4: I/O Circuit Types (3/4) Terminal I/O circuit type Recommended termination μPD70F3187 μPD70F3447 PAH0/A16 to PAH0 to PAH5 Input: Connect independently to V or V via a PAH5/A21 resistor Output: leave open PAL0/A0 to PAL0 to PAL15 PAL15/A15 PDH0/D16 to PDH0 to PDH15...
Page 79 Chapter 2 Pin Functions Table 2-4: I/O Circuit Types (4/4) Terminal I/O circuit type Recommended termination μPD70F3187 μPD70F3447 – Pin must be used in the intended way to V DD10 DD15 to V SS10 SS15 to V DD30 DD37 to V SS30 SS37 User’s Manual U16580EE3V1UD00...
Page 80: Figure 2-1: Pin I/O Circuits
Chapter 2 Pin Functions Figure 2-1: Pin I/O Circuits Type 5 Type 1 data P-ch IN/OUT P-ch output N-ch disable N-ch input enable Type 5-K Type 2 data P-ch IN/OUT output N-ch disable Schmitt trigger input with hysteresis characteristics input enable Type 7 Type 2-I...
Page 81: Noise Suppression
Chapter 2 Pin Functions 2.5 Noise Suppression The V850E/PH2 has a digital or analog delay circuits for noise suppression on all edge sensitive inputs. The digital delay circuit suppresses input pulses shorter than the internally generated edge detection signal to assure the hold time for these signals. The noise suppression is only effective on alternate pin functions, and it is not effective when the port input function is selected.
Page 82: Figure 2-2: Noise Removal Time Control Register (1/2)
Chapter 2 Pin Functions Noise removal time control register (NRC) The NRC register specifies the noise removal clock setting for different edge sensitive inputs. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 2-2: Noise Removal Time Control Register (1/2) After reset: Address:...
Page 83 Chapter 2 Pin Functions Figure 2-2: Noise Removal Time Control Register (2/2) NCR1 Noise removal clock setting for input pins INTP2 to INTP11, ADTRG0, ADTRG1 NCR0 Noise removal clock setting for NMI input pin User’s Manual U16580EE3V1UD00...
Page 84 Chapter 2 Pin Functions [MEMO] User’s Manual U16580EE3V1UD00...
Page 85: Cpu Functions
Chapter 3 CPU Functions The CPU of the V850E/PH2 microcontroller is based on the RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline control. 3.1 Features • Number of instructions: • Minimum instruction execution time: 15.6 ns (@ 64 MHz operation)
Page 86: Cpu Register Set
Chapter 3 CPU Functions 3.2 CPU Register Set The CPU registers of the V850E/PH2 can be classified into three categories: a general-purpose pro- gram register set, a dedicated system register set and a dedicated floating point arithmetic register set. All the registers have 32-bit width.
Page 87: Program Register Set
Chapter 3 CPU Functions 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. All of these registers can be used as a data variable or address variable.
Page 88: System Register Set
Chapter 3 CPU Functions 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, STSR instructions). Table 3-2: System Register Numbers System Register Operand Specification...
Page 89: Figure 3-3: Interrupt Status Saving Registers (Eipc, Eipsw)
Chapter 3 CPU Functions Interrupt status saving registers (EIPC, EIPSW) There are two context saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the content of the program counter (PC) is saved to EIPC and the content of the program status word (PSW) is saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)).
Page 90: Figure 3-4: Nmi Status Saving Registers (Fepc, Fepsw)
Chapter 3 CPU Functions NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the content of the program counter (PC) is saved to FEPC and the content of the program status word (PSW) is saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for the DIVH instruction.
Page 91: Figure 3-6: Program Status Word (Psw)
Chapter 3 CPU Functions Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of the LDSR instruction execution.
Page 92: Figure 3-7: Callt Execution Status Saving Registers (Ctpc, Ctpsw)
Chapter 3 CPU Functions Table 3-3: Saturated Operation Results Operation result status Flag status Saturated operation result Maximum positive value exceeded 7FFFFFFFH Maximum negative value exceeded 80000000H Positive (maximum value not exceeded) Holds value Actual before operation operation result Negative (maximum value not exceeded) CALLT execution status saving registers (CTPC, CTPSW) There are two CALLT execution status saving registers, CTPC and CTPSW.
Page 93: Figure 3-8: Exception/Debug Trap Status Saving Registers (Dbpc, Dbpsw)
Chapter 3 CPU Functions Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW. The contents saved to DBPC consist of the address of the next instruction after the instruction executed when an exception trap or debug trap occurs.
Page 94: Floating Point Arithmetic Unit Register Set
Chapter 3 CPU Functions 3.2.3 Floating point arithmetic unit register set The floating point arithmetic unit is provided with one flag register and one control register. Table 3-4: Floating Point Arithmetic Unit Registers Name Usage Operation Control register Sets the operation of the EFG register Flag register Holds the status of the FPU Floating point arithmetic control register (ECT)
Page 95: Figure 3-11: Floating Point Arithmetic Status Register (Efg)
Chapter 3 CPU Functions Floating point arithmetic status register (EFG) Figure 3-11: Floating Point Arithmetic Status Register (EFG) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 After reset RO IV ZD VF UD PR 0 0 0 TR 0 OV S Z 00000000H Bit position Bit name...
Page 96: Operating Modes
Chapter 3 CPU Functions 3.3 Operating Modes The V850E/PH2 has the following operating modes. 3.3.1 Operating modes outline Normal operating mode (a) Single-chip mode 0 Access to the internal ROM is enabled. In single-chip mode 0, after the system reset is released, each pin related to the bus interface enters the port mode, program execution branches to the reset entry address of the internal ROM, and instruction processing starts.
Page 97: Operation Mode Specification
Chapter 3 CPU Functions 3.3.2 Operation mode specification The operation mode is specified according to the status of pins MODE0 to MODE2. In an application system fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins are changed during operation. MODE2 MODE1 MODE0...
Page 98: Address Space
3.4 Address Space 3.4.1 CPU address space The CPU of the V850E/PH2 uses a 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). When addressing instructions, a linear address space (program space) of up to 64 MB is supported. However, both the program and data spaces include areas whose use is prohibited.
Page 99: Images
Chapter 3 CPU Functions 3.4.2 Images When addressing an instruction address, up to 64 MB of linear address space (program space) and Internal RAM area are supported. For operand addressing (data access), up to 4 GB of linear address space (data area) is supported. On this 4 GB address space, however, 256 MB physical address spaces can be seen as an image.
Page 100: Wrap-Around Of Cpu Address Space
Chapter 3 CPU Functions 3.4.3 Wrap-around of CPU address space Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0.
Page 101: Memory Map
Chapter 3 CPU Functions 3.4.4 Memory map Areas are reserved in V850E/PH2 as shown in Figure 3-16. Each mode is specified by the MODE0 to MODE2 pins. μ Figure 3-16: Memory Map of PD70F3187 Single-chip mode 0 Single-chip mode 1...
Page 102: Figure 3-17: Memory Map Of Μpd70F3447
Chapter 3 CPU Functions μ Figure 3-17: Memory Map of PD70F3447 Single-chip mode 0 xFFFFFFFH On-chip peripheral 4 KB I/O area xFFFF000H xFFFEFFFH Access prohibited Note 1 xFFF6000H xFFF5FFFH Internal RAM area 24 KB xFFF0000H xFFEFFFFH Access prohibited x4000000H x3FFFFFFH On-chip peripheral Note 1 I/O area mirror...
Page 103: Areas
Chapter 3 CPU Functions 3.4.5 Areas Internal ROM area (a) Memory map 1MB of the internal area is reserved for the physical internal ROM (flash memory). In case of uPD70F3187 internal flash memory of 512 KB are physically provided in the following addresses as internal ROM (flash memory).
Page 104: Figure 3-19: Internal Rom / Internal Flash Memory Area Of Μpd70F3447
000000H (b) Interrupt/exception table The V850E/PH2 increases the interrupt response speed by assigning handler addresses corre- sponding to each interrupt/exception. This group of handler addresses is called an interrupt/exception table, which is located in the inter- nal ROM area. When an interrupt/exception request is acknowledged, execution jumps to the han- dler address and the program written in that memory is executed.
Page 105: Figure 3-20: Internal Ram Area Of Μpd70F3187
Chapter 3 CPU Functions Internal RAM area An area of 60 KB from FFF0000H to FFFEFFFH is reserved for the internal RAM area. In case of μPD70F3187 internal RAM of 32 KB are physically provided at addresses FFF0000H to FFF7FFFH as internal RAM. The 32 KB area of 3FF0000H to 3FF7FFFH can be seen as an image of FFF0000H to FFF7FFFH.
Page 106: Figure 3-22: On-Chip Peripheral I/O Area
Chapter 3 CPU Functions On-chip peripheral I/O area (SFR area) A 4 KB area from FFFF000H to FFFFFFFH is provided as the on-chip peripheral I/O area. An image of addresses FFFF000H to FFFFFFFH can be seen at addresses 3FFF000H to Note 3FFFFFFH Note: Addresses 3FFF000H to 3FFFFFFH are access-prohibited.
Page 107: Peripheral I/O Registers List
Chapter 3 CPU Functions 3.4.6 Peripheral I/O registers list Table 3-5: Peripheral I/O Registers (1/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFF000H Port register AL R/W 0000H FFFFF000H PALL Port register ALL R/W R/W FFFFF001H PALH Port register ALH R/W R/W FFFFF002H...
Page 108 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (2/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFF047H PMCDHH Port mode control register DHH R/W R/W Note 1 FFFFF048H PMCCS Port mode control register CS R/W R/W Note 1 FFFFF04AH PMCCT...
Page 109 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (3/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFF11AH PIC5 Interrupt control register 5 R/W R/W FFFFF11CH PIC6 Interrupt control register 6 R/W R/W FFFFF11EH PIC7 Interrupt control register 7 R/W R/W FFFFF120H PIC8...
Page 110 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (4/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFF16AH PIC45 Interrupt control register 45 R/W R/W FFFFF16CH PIC46 Interrupt control register 46 R/W R/W FFFFF16EH PIC47 Interrupt control register 47 R/W R/W FFFFF170H PIC48...
Page 111 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (5/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFF1BAH PIC85 Interrupt control register 85 R/W R/W FFFFF1BCH PIC86 Interrupt control register 86 R/W R/W FFFFF1BEH PIC87 Interrupt control register 87 R/W R/W Note 2 FFFFF1C0H PIC88...
Page 112 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (6/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFF21EH ADCR07 A/D conversion result register 07 undefined FFFFF21FH ADCR07H A/D conversion result register 07H undefined FFFFF220H ADCR08 A/D conversion result register 08 undefined FFFFF221H ADCR08H A/D conversion result register 08H...
Page 113 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (7/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFF30EH MAR7 Memory transfer start address register 7 R/W undefined FFFFF314H SAR2 SFR transfer start address register 2 R/W R/W undefined FFFFF316H SAR3...
Page 114 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (8/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFF444H PMC2 Port mode control register 2 R/W R/W FFFFF446H PMC3 Port mode control register 3 R/W R/W FFFFF448H PMC4 Port mode control register 4 R/W R/W...
Page 115 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (9/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFF5C1H TR1CTL1 TMR1 control register 1 R/W R/W FFFFF5C2H TR1IOC0 TMR1 I/O control register 0 R/W R/W FFFFF5C3H TR1IOC1 TMR1 I/O control register 1 R/W R/W FFFFF5C4H TR1IOC2...
Page 116 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (10/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFF620H TP2CTL0 TMP2 timer control register 0 R/W R/W FFFFF621H TP2CTL1 TMP2 timer control register 1 R/W R/W FFFFF622H TP2IOC0 TMP2 I/O control register 0 R/W R/W...
Page 117 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (11/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFF664H TP6IOC2 TMP6 I/O control register 2 R/W R/W FFFFF665H TP6OPT0 TMP6 option register R/W R/W FFFFF666H TP6CCR0 TMP6 capture/compare register 0 R/W 0000H FFFFF668H TP6CCR1...
Page 118 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (12/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFF6A4H TT1IOC1 TMT1 I/O control register 1 R/W R/W FFFFF6A5H TT1IOC2 TMT1 I/O control register 2 R/W R/W FFFFF6A6H TT1IOC3 TMT1 I/O control register 3 R/W R/W...
Page 119 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (13/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFFA04H UC0STR UARTC0 status register R/W R/W FFFFFA06H UC0RX UARTC0 receive data register 01FFH FFFFFA06H UC0RXL UARTC0 receive data register L FFFFFA08H UC0TX UARTC0 transmit data register...
Page 120 Chapter 3 CPU Functions Table 3-5: Peripheral I/O Registers (14/14) Address Symbol Function Register Name Bit Units for Reset Remarks Manipulation FFFFFD44H SFCS30 CSI30 chip selection CSI buffer register R/W FFFFH FFFFFD45H SFCS30H CSI30 chip selection CSI buffer register H FFFFFD46H SFDB30L CSI30 transmit data CSI buffer register L FFFFFD46H SFDB30...
Page 121: Programmable Peripheral I/O Area
3.4.7 Programmable peripheral I/O area In the V850E/PH2, the 16 KB area of x0000H to x3FFFH is provided as a programmable peripheral I/O area. In this area, the area between x0000H and x08FFH is used exclusively for the CAN controllers...
Page 122: Figure 3-24: Programmable Peripheral Area Control Register Bpc
Chapter 3 CPU Functions Peripheral area selection control register (BPC) The peripheral area selection control register (BPC) is used to select a programmable peripheral I/O register area where the registers of the CAN controller are allocated. This register can be read/written in 16-bit units. Figure 3-24: Programmable Peripheral Area Control Register BPC After reset: 0000H...
Page 123: Table 3-6: Programmable Peripheral I/O Registers
Chapter 3 CPU Functions Registers in the programmable peripheral I/O area In the following Table 3-6 the addresses shown are offsets in the programmable peripheral I/O area, which have to be added to base address set by the BPC register. Table 3-6: Programmable Peripheral I/O Registers (1/16) Address Symbol...
Page 124 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (2/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 0000064H C0TGPT CAN0 module transmit history list get pointer Undefined register × × 0000064H C0TGPTL CAN0 module transmit history list get pointer register L ×...
Page 125 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (3/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 0000140H C0MDATA0102 CAN0 message data byte 0 and 1 register 02 R/W Undefined × × 0000140H C0MDATA002 CAN0 message data byte 0 register 02...
Page 126 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (4/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 0000184H C0MDATA4504 CAN0 message data byte 4 and 5 register 04 R/W Undefined × × 0000184H C0MDATA404 CAN0 message data byte 2 register 04...
Page 127 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (5/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × × 00001C8H C0MDLC06 CAN0 message data length code register 06 Undefined × × 00001C9H C0MCONF06 CAN0 message configuration register 06 Undefined ×...
Page 128 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (6/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 0000220H C0MDATA0109 CAN0 message data byte 0 and 1 register 09 R/W Undefined × × 0000220H C0MDATA009 CAN0 message data byte 0 register 09...
Page 129 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (7/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 0000264H C0MDATA4511 CAN0 message data byte 4 and 5 register 11 R/W Undefined × × 0000264H C0MDATA411 CAN0 message data byte 2 register 11...
Page 130 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (8/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × × 00002A8H C0MDLC13 CAN0 message data length code register 13 Undefined × × 00002A9H C0MCONF13 CAN0 message configuration register 13 Undefined ×...
Page 131 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (9/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 0000600H C1GMCTRL CAN1 global macro control register 0000H × × 0000600H C1GMCTRLL CAN1 global macro control register L ×...
Page 132 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (10/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 0000666H C1TS CAN1 module time stamp register 0000H × × 0000666H C1TSL CAN1 module time stamp register L ×...
Page 133 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (11/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 0000742H C1MDATA2302 CAN1 message data byte 2 and 3 register 02 R/W Undefined × × 0000742H C1MDATA202 CAN1 message data byte 2 register 02...
Page 134 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (12/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 0000786H C1MDATA6704 CAN1 message data byte 6 and 7 register 04 R/W Undefined × × 0000786H C1MDATA604 CAN1 message data byte 6 register 04...
Page 135 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (13/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 00007CCH C1MIDH06 CAN1 message identifier H register 06 Undefined × 00007CEH C1MCTRL06 CAN1 message control register 06 Undefined ×...
Page 136 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (14/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 0000822H C1MDATA2309 CAN1 message data byte 2 and 3 register 09 R/W Undefined × × 0000822H C1MDATA209 CAN1 message data byte 2 register 09...
Page 137 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (15/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 0000866H C1MDATA6711 CAN1 message data byte 6 and 7 register 11 R/W Undefined × × 0000866H C1MDATA611 CAN1 message data byte 6 register 11...
Page 138 Chapter 3 CPU Functions Table 3-6: Programmable Peripheral I/O Registers (16/16) Address Symbol Function Register Name R/W Bit Units for Manipulation After Offset Reset × 00008ACH C1MIDH13 CAN1 message identifier H register 13 Undefined × 00008AEH C1MCTRL13 CAN1 message control register 13 Undefined ×...
Page 139: Specific Registers
Specific registers are registers that prevent invalid data from being written if an inadvertent program behaviour occurs. The V850E/PH2 has the following specific registers: • Port registers 5 and 6 (P5, P6) • Port mode registers 5 and 6 (PM5, PM6) •...
Page 140: Figure 3-25: Processor Command Register (Prcmd)
Chapter 3 CPU Functions Processor command register (PRCMD) The PRCMD register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop. Only the first write operation to a specific register following the execution of a write operation to the PRCMD register, is valid.
Page 141: Figure 3-26: System Status Register Format Phs
Chapter 3 CPU Functions System status register (PHS) The PHS register is an 8-bit register to which the PRERR flag showing the generation of protection errors is assigned. If a write operation to a specific register has not been executed in the correct sequence including the access to the command register (PRCMD), the write operation to the intended register is not executed, a protection error is generated and the PRERR flag is set to 1.
Page 142: System Wait Control Register (Vswc)
Access to on-chip peripheral I/O registers is made in 3 clocks (without wait), however, in the V850E/PH2 waits may be required depending on the operation frequency. Set the values described in the table below to the VSWC register in accordance with the operation frequency used.
Page 143: Cautions
Chapter 3 CPU Functions 3.4.11 Cautions • Initialize the following registers immediately after reset signal release in the following sequence: - System wait control register (VSWC) (refer to 3.4.9 System wait control register (VSWC)) - DMA wait control registers 0 and 1 (DMAWC0,DMAWC1) (refer to 3.4.10 DMA wait control registers 0 and 1 (DMAWC0, DMAWC1)) User’s Manual U16580EE3V1UD00...
Page 144 Chapter 3 CPU Functions [MEMO] User’s Manual U16580EE3V1UD00...
Page 145: Bus Control Function (Μpd70F3187 Only)
Chapter 4 Bus Control Function (μPD70F3187 only) The μPD70F3187 is provided with an external bus interface function by which external memories, such as ROM and RAM, and external I/O can be connected. The μPD70F3447 is not equipped external bus interface function. 4.1 Features •...
Page 146: Memory Block Function
Chapter 4 Bus Control Function (μPD70F3187 only) 4.3 Memory Block Function The 64 MB memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB units. Figure 4-1: Memory Block Function 3FFFFFFH 3FFFFFFH Block 15 (2 Mbytes) Internal peripheral I/O area (4 Kbytes) 3E00000H 3DFFFFFH...
Page 147: Chip Select Control Function
Chapter 4 Bus Control Function (μPD70F3187 only) 4.3.1 Chip select control function The 64 MB memory area can be divided into 2 MB, 4 MB and 8 MB memory blocks by the chip area selection control registers 0 and 1 (CSC0, CSC1) to control the chip select signals. The memory area can be effectively used by dividing the memory area into memory blocks using the chip select control function.
Page 148 Chapter 4 Bus Control Function (μPD70F3187 only) Figure 4-2: Chip Area Select Control Registers 0, 1 (2/2) CSnm Chip Select Operation CS00 CS0 active during block 0 access CS01 CS0 active during block 1 access. CS02 CS0 active during block 2 access. CS03 CS0 active during block 3 access.
Page 149: Bus Cycle Type Control Function
Chapter 4 Bus Control Function (μPD70F3187 only) 4.4 Bus Cycle Type Control Function In the V850E/PH2, the following external devices can be connected directly to each memory block. • SRAM, external ROM, external I/O Connected external devices are specified by the bus cycle type configuration registers 0, 1 (BCT0, BCT1).
Page 150: Bus Cycle Type Configuration
Chapter 4 Bus Control Function (μPD70F3187 only) 4.4.1 Bus cycle type configuration Bus cycle configuration registers 0, 1 (BCT0, BCT1) These registers can be read/written in 16-bit units Cautions: 1. Write to the BCT0 and BCT1 registers after reset, and then do not change the set value.
Page 151: Bus Access
Chapter 4 Bus Control Function (μPD70F3187 only) 4.5 Bus Access 4.5.1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows. Table 4-1: Number of Bus Access Clocks Resources (Bus width) Internal RAM Peripheral I/O External memory (32 bits)
Page 152: Bus Sizing Function
Chapter 4 Bus Control Function (μPD70F3187 only) 4.5.2 Bus sizing function The bus sizing function controls data bus width for each CS area. The data bus width is specified by using the bus size configuration register (BSC). Bus size configuration register (BSC) This register can be read/written in 16-bit units.
Page 153: Endian Control Function
Chapter 4 Bus Control Function (μPD70F3187 only) 4.5.3 Endian control function The Endian control function can be used to set processing of word data in memory either by the Big Endian method or the Little Endian method for each CS area selected with the chip select signal (CS0 to CS7).
Page 154: Figure 4-7: Endian Configuration Register (Bec)
Chapter 4 Bus Control Function (μPD70F3187 only) Endian configuration register (BEC) This register can be read/written in 16-bit units. Cautions: 1. Bits 15, 13, 11, 9, 7, 5, 3, and 1 of the BEC register must be cleared (0). If these bits are set to 1, the operation is not guaranteed.
Page 155: Bus Width
Chapter 4 Bus Control Function (μPD70F3187 only) 4.5.4 Bus width The V850E/PH2 accesses peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The fol- lowing shows the operation for each type of access. Access all data in order starting from the lower order side.
Page 156 Chapter 4 Bus Control Function (μPD70F3187 only) (c) When the data bus width is 8 bits (Little Endian) <1> Access to <2> Access to <3> Access to <4> Access to address (4n) address (4n+1) address (4n+2) address (4n+3) Address Address Address Address 4n + 1...
Page 157 Chapter 4 Bus Control Function (μPD70F3187 only) (e) When the data bus width is 16 bits (Big Endian) <1> Access to <2> Access to <3> Access to <4> Access to address (4n) address (4n+1) address (4n+2) address (4n+3) Address Address Address Address 4n + 2...
Page 158 Chapter 4 Bus Control Function (μPD70F3187 only) Halfword access (16 bits) (a) When the data bus width is 32 bits (Little Endian) <1> Access to address (4n) <2> Access to address (4n+1) Address Address 4n + 2 4n + 1 4n + 1 Halfword External...
Page 159 Chapter 4 Bus Control Function (μPD70F3187 only) (b) When the data bus width is 16 bits (Little Endian) <1> Access to address (4n) <2> Access to address (4n+1) 1st access 2nd access Address Address Address 4n + 1 4n + 1 4n + 2 Halfword External...
Page 160 Chapter 4 Bus Control Function (μPD70F3187 only) (c) When the data bus width is 8 bits (Little Endian) <1> Access to address (4n) <2> Access to address (4n+1) 1st access 2nd access 1st access 2nd access Address Address Address Address 4n + 1 4n + 1 4n + 2...
Page 161 Chapter 4 Bus Control Function (μPD70F3187 only) (d) When the data bus width is 32 bits (Big Endian) <1> Access to address (4n) <2> Access to address (4n+1) Address Address 4n + 1 4n + 1 4n + 2 Halfword External Halfword External...
Page 162 Chapter 4 Bus Control Function (μPD70F3187 only) (e) When the data bus width is 16 bits (Big Endian) <1> Access to address (4n) <2> Access to address (4n+1) 1st access 2nd access Address Address Address 4n + 2 4n + 1 4n + 1 Halfword Halfword...
Page 163 Chapter 4 Bus Control Function (μPD70F3187 only) (f) When the data bus width is 8 bits (Big Endian) <1> Access to address (4n) <2> Access to address (4n+1) 1st access 2nd access 1st access 2nd access Address Address Address Address 4n + 1 4n + 1 4n + 2...
Page 164 Chapter 4 Bus Control Function (μPD70F3187 only) Word access (32 bits) (a) When the bus width is 32 bits (Little Endian) <1> Access to address (4n) <2> Access to address (4n+1) 1st access 2nd access Address Address Address 4n + 3 4n + 3 4n + 2 4n + 2...
Page 165 Chapter 4 Bus Control Function (μPD70F3187 only) (b) When the bus width is 16 bits (Little Endian) <1> Access to address (4n) 1st access 2nd access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data External data bus...
Page 166 Chapter 4 Bus Control Function (μPD70F3187 only) <3> Access to address (4n+2) 1st access 2nd access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data External data bus data bus <4>...
Page 167 Chapter 4 Bus Control Function (μPD70F3187 only) (c) When the data bus width is 8 bits (Little Endian) <1> Access to address (4n) 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External...
Page 168 Chapter 4 Bus Control Function (μPD70F3187 only) <3> Access to address (4n+2) 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data External Word data External...
Page 169 Chapter 4 Bus Control Function (μPD70F3187 only) (d) When the data bus width is 32 bits (Big Endian) <1> Access to address (4n) <2> Access to address (4n+1) 1st access 2nd access Address Address Address 4n + 4 4n + 1 4n + 1 4n + 2 4n + 2...
Page 170 Chapter 4 Bus Control Function (μPD70F3187 only) (e) When the data bus width is 16 bits (Big Endian) <1> Access to address (4n) 1st access 2nd access Address Address 4n + 2 4n + 3 4n + 1 Word data External Word data External...
Page 171 Chapter 4 Bus Control Function (μPD70F3187 only) <3> Access to address (4n+2) 1st access 2nd access Address Address 4n + 2 4n + 4 4n + 3 4n + 5 Word data External Word data External data bus data bus <4>...
Page 172 Chapter 4 Bus Control Function (μPD70F3187 only) (f) When the data bus width is 8 bits (Big Endian) <1> Access to address (4n) 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 3 4n + 1 4n + 2 Word data External...
Page 173 Chapter 4 Bus Control Function (μPD70F3187 only) <3> Access to address (4n+2) 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 5 4n + 2 4n + 3 4n + 4 Word data External Word data External Word data External...
Page 174: Wait Function
Chapter 4 Bus Control Function (μPD70F3187 only) 4.6 Wait Function 4.6.1 Programmable wait function Data wait control registers 0, 1 (DWC0, DWC1) To facilitate interfacing with low-speed memory or with I/Os, it is possible to insert up to 7 data wait states with respect to the starting bus cycle for each CS area.
Page 175: Figure 4-9: Address Wait Control Register (Awc)
Chapter 4 Bus Control Function (μPD70F3187 only) Address wait control register (AWC) The V850E/PH2 allows insertion of address setup wait and address hold wait states before and after the T1 cycle. The address setup wait and address hold wait states can be set with the AWC register for each CS area.
Page 176: Idle State Insertion Function
Chapter 4 Bus Control Function (μPD70F3187 only) 4.7 Idle State Insertion Function To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted into the current bus cycle after the T2 state to meet the data output float delay time (tdf) on memory read access for each CS space.
Page 177: Figure 4-10: Bus Cycle Control Register (Bcc)
Chapter 4 Bus Control Function (μPD70F3187 only) Bus cycle control register (BCC) This register can be read/written in 16-bit units. Reset input changes the value of this register to initial setting AAAAH. Cautions: 1. Idle states cannot be inserted in internal ROM, internal RAM, on-chip peripheral I/O, or programmable peripheral I/O areas.
Page 178: Figure 4-11: Bus Clock Dividing Control Register (Dvc)
Chapter 4 Bus Control Function (μPD70F3187 only) Bus clock dividing control register (DVC) This register can be read/written in 8-bit units. Reset input changes the value of this register to initial setting 01H. Cautions: 1. Idle states cannot be inserted in internal ROM, internal RAM, on-chip peripheral I/O, or programmable peripheral I/O areas.
Page 179: Bus Priority Order
Chapter 4 Bus Control Function (μPD70F3187 only) 4.8 Bus Priority Order There are two external bus cycles: operand data access and instruction fetch. As for the priority order, the highest priority has the instruction fetch than operand data access. An instruction fetch may be inserted between read access and write access during read modify write access.
Page 180: Boundary Operation Conditions
4.9.2 Data space The V850E/PH2 is provided with an address misalign function. Through this function, regardless of the data format (word, halfword or byte), data can be allocated to all addresses. However, in the case of word data and halfword data, if the data is not subject to boundary alignment, the bus cycle will be generated at least 2 times and bus efficiency will drop.
Page 181: Chapter 5 Memory Access Control Function (Μpd70F3187 Only)
Chapter 5 Memory Access Control Function (μPD70F3187 only) 5.1 SRAM, External ROM, External I/O Interface 5.1.1 Features • SRAM is accessed in a minimum of 2 states. • Up to 7 states of programmable data waits can be inserted by setting the DWC0 and DWC1 registers.
Page 182: Sram Connection
Examples of connection to SRAM are shown below. Figure 5-1: Examples of Connection to SRAM (1/2) (a) When Data Bus Width is 32 Bits and Data Size of SRAM is 8 Bits V850E/PH2 SRAM A2 to A20 A0 to A18...
Page 183 Chapter 5 Memory Access Control Function (μPD70F3187 only) Figure 5-1: Examples of Connection to SRAM (2/2) (c) When Data Bus Width is 32 Bits and Data Size of SRAM is 16 Bits V850E/PH2 SRAM A2 to A19 A0 to A17...
Page 184: Sram, External Rom, External I/O Access
Chapter 5 Memory Access Control Function (μPD70F3187 only) 5.1.3 SRAM, external ROM, external I/O access Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/8) (a) Read Bus clock A0 to A21 Address Address (output) CSn (output) Note 1 Note 1 RD (output) WR (output) BEN0...
Page 185 Chapter 5 Memory Access Control Function (μPD70F3187 only) Figure 5-2: SRAM, External ROM, External I/O Access Timing (2/8) (b) Read (Idle State Inserted) Bus clock A0 to A21 (output) Address CSn (output) Note 1 RD (output) WR (output) BEN0 BEN3 (output) Note 2 D0 to D31 (input)
Page 186 Chapter 5 Memory Access Control Function (μPD70F3187 only) Figure 5-2: SRAM, External ROM, External I/O Access Timing (3/8) (c) Read (Data Wait, Idle State Inserted) Bus clock A0 to A21 (output) Address CSn (output) Note 1 RD (output) WR (output) BEN0 BEN3 (output)
Page 187 Chapter 5 Memory Access Control Function (μPD70F3187 only) Figure 5-2: SRAM, External ROM, External I/O Access Timing (4/8) (d) Read (Address Setup Wait and Address Hold Wait State Inserted) Bus clock A0 to A21 (output) Address CSn (output) Note 1 RD (output) WR (output) BEN0...
Page 188 Chapter 5 Memory Access Control Function (μPD70F3187 only) Figure 5-2: SRAM, External ROM, External I/O Access Timing (5/8) (e) Write Bus clock A0 to A21 Address Address (output) CSn (output) Note 1 Note 1 RD (output) WR (output) BEN0 BEN3 Note 2 Note 2 (output)
Page 189 Chapter 5 Memory Access Control Function (μPD70F3187 only) Figure 5-2: SRAM, External ROM, External I/O Access Timing (6/8) (f) Write (Idle State Inserted) Bus clock A0 to A21 (output) Address CSn (output) Note 1 RD (output) WR (output) BEN1 BEN3 (output) Note 2 D0 to D31 (input)
Page 190 Chapter 5 Memory Access Control Function (μPD70F3187 only) Figure 5-2: SRAM, External ROM, External I/O Access Timing (7/8) (g) Write (Data Wait, Idle State Inserted) Bus clock A0 to A21 (output) Address CSn (output) Note 1 RD (output) WR (output) BEN0 BEN3 (output)
Page 191 Chapter 5 Memory Access Control Function (μPD70F3187 only) Figure 5-2: SRAM, External ROM, External I/O Access Timing (8/8) (h) Read (Address Setup Wait and Address Hold Wait State Inserted) Bus clock A0 to A21 (output) Address CSn (output) Note 1 RD (output) WR (output) BEN0...
Page 192 Chapter 5 Memory Access Control Function (μPD70F3187 only) [MEMO] User’s Manual U16580EE3V1UD00...
Page 193: Chapter 6 Dma Functions (Dma Controller)
Chapter 6 DMA Functions (DMA Controller) 6.1 Features The V850E/PH2 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between internal RAM (iRAM) and peripheral I/O registers, based on DMA requests issued by the on-chip peripheral I/O (A/D converters, inverter timers, and serial interfaces), with the following features.
Page 194: Control Registers
Chapter 6 DMA Functions (DMA Controller) 6.2 Control Registers DMA transfer memory start address registers 0 to 7 (MAR0 to MAR7) The MARn register specifies the subordinated 16 bits of the DMA transfer start address within the internal RAM area for the DMA channel n (n = 0 to 7). This register can be read or written in 16-bit units.
Page 195: Figure 6-2: Dma Transfer Sfr Start Address Registers 2, 3 (Sar2, Sar3)
Chapter 6 DMA Functions (DMA Controller) DMA transfer SFR start address registers 2, 3 (SAR2, SAR3) The SARn register specifies the start address of the TMR register for which the DMA transfer is started on DMA channel n (n = 2, 3). This register can be read or written in 8-bit units.
Page 196: Figure 6-3: Dma Transfer Count Registers 0 To 7 (Dtcr0 To Dtcr7)
Chapter 6 DMA Functions (DMA Controller) DMA transfer count registers 0 to 7 (DTCR0 to DTCR7) The DTCRn register is an 8-bit register that set the transfer count for DMA channel n and stores the remaining transfer count during DMA transfer (n = 0 to 7). This register can be read or written in 8-bit units.
Page 197: Figure 6-4: Dma Mode Control Register (Dmamc)
Chapter 6 DMA Functions (DMA Controller) DMA mode control register (DMAMC) The DMAMC register is an 8-bit register that controls the operation of the DMA channels. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 6-4: DMA Mode Control Register (DMAMC) After reset: Address:...
Page 198: Figure 6-6: Dma Data Size Control Register (Dmdsc)
Chapter 6 DMA Functions (DMA Controller) DMA data size control register (DMDSC) The DMADSC register is an 8-bit register that controls the transfer data size of DMA channels 4 to 7. The data size of DMA channels 0 to 3 is fixed, and therefore not selectable. This register can be read or written in 8-bit units.
Page 199: Figure 6-7: Dma Trigger Factor Registers 4 To 7 (Dtfr4 To Dtfr7)
Chapter 6 DMA Functions (DMA Controller) DMA trigger factor registers 4 to 7 (DTFR4 to DTFR7) The DTFRn register is an 8-bit register that controls the DMA transfer start trigger of DMA channel n via interrupt requests from on-chip peripheral I/O (n = 4 to 7). The interrupt request set by this register serves as DMA transfer start factor.
Page 200: Dma Channel Priorities
Chapter 6 DMA Functions (DMA Controller) 6.3 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 >... > DMA channel 7 6.4 DMA Operation 6.4.1 DMA transfer of A/D converter result registers (ADC0, ADC1) The DMAC has two dedicated channels to support DMA transfer for both A/D converters independently, DMA channel 0 for A/D converter 0 and DMA channel 1 for A/D converter 1.
Page 201: Figure 6-8: Initialization Of Dma Transfer For A/D Conversion Result
Chapter 6 DMA Functions (DMA Controller) Figure 6-8: Initialization of DMA Transfer for A/D Conversion Result Initialization of DMA transfer for A/D conversion result of ADCn (DMA channel 0 or 1) ADCEn bit = 1? ADCSn bit = 1? Disable operation of A/D converter n: ADCEn bit = 0 Set up A/D conversion scan range in the ADMn2 register...
Page 202: Figure 6-9: Operation Of Dma Channel 0/1
Chapter 6 DMA Functions (DMA Controller) Figure 6-9: Operation of DMA Channel 0/1 Operation of DMA channel 0/1 DMA transfer will be enabled DEx bit newly by write access to the written ? corresponding DEn bit. DEx bit = 1 ? ADDMARQn occured ? Transfer content from ADDMAn register to...
Page 203: Figure 6-10: Dma Channel 0 And 1 Trigger Signal Timing
Chapter 6 DMA Functions (DMA Controller) Figure 6-10: DMA Channel 0 and 1 Trigger Signal Timing Re-setup DTCRx, DMAMC Setup MARx, DTCRx, register (write DEx bit = 1) DMAMC register ADDMARQn DMA transfer MARx 1000H 1002H 1004H 1006H 1008H 100AH 100CH 100EH 1010H...
Page 204: Dma Transfer Of Pwm Timer Reload (Tmr0, Tmr1)
Chapter 6 DMA Functions (DMA Controller) 6.4.2 DMA transfer of PWM timer reload (TMR0, TMR1) The DMAC has two dedicated channels to support DMA transfer for both PWM timers TMRn independently, DMA channel 2 for TMR0 and DMA channel 3 for TMR1. As DMA trigger factor, which requests and starts the DMA transfer, two corresponding timer interrupt signals are pre-defined (INTTRnOD or INTTRnCD).
Page 205: Figure 6-11: Initialization Of Dma Transfer For Tmrn Compare Registers
Chapter 6 DMA Functions (DMA Controller) Figure 6-11: Initialization of DMA Transfer for TMRn Compare Registers Initialization of DMA transfer for TMRn compare registers (DMA channel 2 or 3) Set up SARx register with TMRn start address offset (TRnCCR0, TRnCCR2 to TRnCCR5) Set up the MARx register with source start address in iRAM...
Page 206: Figure 6-12: Operation Of Dma Channel 2/3
Chapter 6 DMA Functions (DMA Controller) Figure 6-12: Operation of DMA Channel 2/3 Operation of DMA channel 2/3 DMA transfer will be enabled DEx bit newly by write access to the written ? corresponding DEn bit. DEx bit = 1 ? INTTRnOD occurred ? INTTRnCD...
Page 207: Figure 6-13: Dma Channel 2 And 3 Trigger Signal Timing
Chapter 6 DMA Functions (DMA Controller) Figure 6-13: DMA Channel 2 and 3 Trigger Signal Timing Setup MARx, DTCRx, SARx register INTTRnOD INTTRnCD DMA transfer MARx 1000H 1002H 1004H 1006H 1008H 100AH 100EH 1010H SARx 05 H DTCRx INTDMAx Remarks: 1. The DMA request by INTTRnOD or INTTRnCD is disregarded after INTDMAx is gener- ated, and the DMA transfer is not restarted automatically.
Page 208: Dma Transfer Of Serial Interfaces
Chapter 6 DMA Functions (DMA Controller) 6.4.3 DMA transfer of serial interfaces Serial data reception with DMA transfer The DMAC has two dedicated channels (4 and 5) to support the serial data reception. Each of Note Note both channels can be assigned to a serial interface (CSI30, CSI31 , CSIB0, CSIB1 UARTC0, UARTC1).
Page 209: Figure 6-14: Initialization Of Dma Transfer For Serial Data Reception
Chapter 6 DMA Functions (DMA Controller) The procedure of the DMA transfer in case of serial data reception is shown in Figure 6-14. Figure 6-14: Initialization of DMA Transfer for Serial Data Reception Initialization of DMA transfer for serial data reception (DMA channel 4 or 5) Set up MARx register with the destination start address in iRAM...
Page 210: Figure 6-15: Operation Of Dma Channel 4/5
Chapter 6 DMA Functions (DMA Controller) Figure 6-15: Operation of DMA Channel 4/5 Operation of DMA channel 4/5 DEx bit newly DMA transfer will be enabled by write written ? access to the corresponding DEn bit. DEx bit = 1 ? DMA trigger factor occurred ? DMA trigger factor is the interrupt...
Page 211: Figure 6-16: Dma Channel 4 And 5 Trigger Signal Timing
Chapter 6 DMA Functions (DMA Controller) Figure 6-16: DMA Channel 4 and 5 Trigger Signal Timing DTCRm, MARm, DTCRm, DMAMCm DTRFm, DMAMCm Trigger signal (by DTFRm register) DMA transfer MARm 1000H 1002H 1004H 1006H 1008H 100AH 100CH 100EH 1010H DTCRm 0003H 0002H 0001H...
Page 212: Table 6-3: Dma Configuration Of Serial Data Transmission
Chapter 6 DMA Functions (DMA Controller) Serial data transmission with DMA transfer The DMAC has two dedicated channels (6 and 7) to support the serial data transmission. Each of Note 1 Note 1 both channels can be assigned to a serial interface (CSI30, CSI31 , CSIB0, CSIB1 UARTC0, UARTC1).
Page 213: Figure 6-17: Initialization Of Dma Transfer For Serial Data Transmission
Chapter 6 DMA Functions (DMA Controller) The procedure of the DMA transfer in case of serial data transmission is shown in Figure 6-17. Figure 6-17: Initialization of DMA Transfer for Serial Data Transmission Initialization of DMA transfer for serial data transmission (DMA channel 6 or 7) Set up MARx register with the source start address in iRAM...
Page 214: Figure 6-18: Dma Channel 6 And 7 Trigger Signal Timing
Chapter 6 DMA Functions (DMA Controller) Figure 6-18: DMA Channel 6 and 7 Trigger Signal Timing MARm, DTCRm, DTCRm, DTRFm, DMAMCm DMAMCm Trigger signal (by DTFRm register) DMA transfer MARm 1000H 1002H 1004H 1006H 1008H 100AH 100CH 100EH 1010H DTCRm 0003H 0002H 0001H...
Page 215: Figure 6-19: Operation Of Dma Channel 6/7
Chapter 6 DMA Functions (DMA Controller) Figure 6-19: Operation of DMA Channel 6/7 Operation of DMA channel 6/7 DEx bit newly DMA transfer will be enabled by write written ? access to the corresponding DEn bit. DEx bit = 1 ? DMA trigger factor occurred ? DMA trigger factor is the interrupt...
Page 216: Forcible Termination Of Dma Transfer
Chapter 6 DMA Functions (DMA Controller) 6.4.4 Forcible termination of DMA transfer A once started DMA transfer can be forcible terminated when the corresponding DEn bit in the DMAMC register is cleared (0). However, if the DEn bit is cleared while DMA transferring, an once started data transfer is stopped first after it has been finished (see Figure 6-20).
Page 217: Dma Interrupt Function
Chapter 6 DMA Functions (DMA Controller) 6.5 DMA Interrupt Function The peripheral I/O interrupts of the A/D converters and the serial interfaces, which serve as DMA trigger factors, are shared with the DMA transfer completion interrupt of the corresponding channel n (INTDMAn) (n = 0, 1, 4 to 7).
Page 218: Figure 6-21: Correlation Between Serial I/O Interface Interrupts And Dma Completion Interrupts
Chapter 6 DMA Functions (DMA Controller) Figure 6-21: Correlation between Serial I/O Interface Interrupts and DMA Completion Interrupts INTUC0R' INTUC0R' INTUC1R' INTUC0R INTDMA4 INTCB0R' DMA channel 4 Note INTCB1R' INTCSI30' INTUC1R' Note INTCSI31' INTUC1R INTCB0R' INTCB0R INTDMA5 DMA channel 5 Note INTCB1R' Note...
Page 219: Chapter 7 Interrupt/Exception Processing Function
Chapter 7 Interrupt/Exception Processing Function The V850E/PH2 microcontroller is provided with a dedicated interrupt controller (INTC) for interrupt servicing, which realizes a high-performance interrupt function that can service interrupt requests from a total of up to 107 sources. An interrupt is an event that occurs asynchronously (independently of program execution), and an exception is an event that occurs synchronously (dependently on program execution).
Page 220 Chapter 7 Interrupt/Exception Processing Function Table 7-1: Interrupt/Exception Source List (2/5) Type Classification Interrupt/Exception Source Default Exception Handler Restored Priority Code Address Name Control Generating Source Gener. Register Unit Maskable Interrupt INTP5 PIC5 INTP5 valid edge input Pin 00D0H 000000D0H nextPC Interrupt INTP6 PIC6 INTP6 valid edge input Pin...
Page 221 Chapter 7 Interrupt/Exception Processing Function Table 7-1: Interrupt/Exception Source List (3/5) Type Classification Interrupt/Exception Source Default Exception Handler Restored Priority Code Address Name Control Generating Source Gener. Register Unit Maskable Interrupt INTT1EC PIC40 TMT1 encoder clear TMT1 0300H 00000300H nextPC Interrupt INTP0OV PIC41 TMP0 overflow TMP0...
Page 222 Chapter 7 Interrupt/Exception Processing Function Table 7-1: Interrupt/Exception Source List (4/5) Type Classification Interrupt/Exception Source Default Exception Handler Restored Priority Code Address Name Control Generating Source Gener. Register Unit Maskable Interrupt INTC0ERR PIC71 FCAN0 error FCAN0 04F0H 000004F0H nextPC Interrupt INTC0WUP PIC72 FCAN0 wake up FCAN0 0500H 00000500H nextPC...
Page 223 Chapter 7 Interrupt/Exception Processing Function Table 7-1: Interrupt/Exception Source List (5/5) Type Classification Interrupt/Exception Source Default Exception Handler Restored Priority Code Address Name Control Generating Source Gener. Register Unit Maskable Interrupt INTAD1 PIC96 ADC1 conversion ADC1/ 0680H 00000680H nextPC completion/ DMA DMAC transfer completion Interrupt INTCC10...
Page 224: Non-Maskable Interrupt
Chapter 7 Interrupt/Exception Processing Function 7.2 Non-maskable Interrupt A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. A NMI is not subject to priority control and takes precedence over all the other interrupts. A non-maskable interrupt request is input from the NMI pin.
Page 225: Operation
Chapter 7 Interrupt/Exception Processing Function 7.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: Saves the restored PC to FEPC. Saves the current PSW to FEPSW. Writes exception code 0010H to the higher half-word (FECC) of ECR. Sets the NP and ID bits of the PSW and clears the EP bit.
Page 226: Figure 7-2: Acknowledging Non-Maskable Interrupt Request
Chapter 7 Interrupt/Exception Processing Function Figure 7-2: Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while a NMI service program is being executed Main routine (PSW.NP = 1) NMI request held pending because NMI request NMI request PSW.NP = 1 Pending NMI request processed (b) If a new NMI request is generated twice while a NMI service program is being executed...
Page 227: Restore
Chapter 7 Interrupt/Exception Processing Function 7.2.2 Restore Execution is restored from the non-maskable interrupt (NMI) processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>...
Page 228: Non-Maskable Interrupt Status Flag (Np)
Chapter 7 Interrupt/Exception Processing Function 7.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execution. This flag is set when a NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 229: Maskable Interrupts
Chapter 7 Interrupt/Exception Processing Function 7.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The μPD70F3187 has 106 maskable interrupt sources and the μPD70F3447 has 91 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 230: Figure 7-6: Maskable Interrupt Processing
Chapter 7 Interrupt/Exception Processing Function Figure 7-6: Maskable Interrupt Processing INT input INTC accepted xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 231: Restore
Chapter 7 Interrupt/Exception Processing Function 7.3.2 Restore Recovery from maskable interrupt processing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0.
Page 232: Priorities Of Maskable Interrupts
Chapter 7 Interrupt/Exception Processing Function 7.3.3 Priorities of maskable interrupts The V850E/PH2 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (PRn) of the interrupt control register (PICn).
Page 233: Figure 7-8: Example Of Processing In Which Another Interrupt Request Is Issued While An Interrupt Is Being Processed (1/2)
Chapter 7 Interrupt/Exception Processing Function Figure 7-8: Example of Processing in which Another Interrupt Request Is Issued while an Interrupt is being Processed (1/2) Main routine Processing of a Processing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority of b is higher than that of a and interrupts are...
Page 234 Chapter 7 Interrupt/Exception Processing Function Figure 7-8: Example of Processing in which Another Interrupt Request Is Issued while an Interrupt is being Processed (2/2) Main routine Process ing of i Process ing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its...
Page 235: Figure 7-9: Example Of Processing Interrupt Requests Simultaneously Generated
Chapter 7 Interrupt/Exception Processing Function Figure 7-9: Example of Processing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request b and c are Processing of interrupt request b Interrupt request c (level 1) acknowledged first according to their priorities.
Page 236: Interrupt Control Register (Picn)
Chapter 7 Interrupt/Exception Processing Function 7.3.4 Interrupt control register (PICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read/written in 8-bit or 1-bit units. Figure 7-10: Interrupt Control Register (PICn) After reset: Address:...
Page 237: Table 7-2: Addresses And Bits Of Interrupt Control Registers
Chapter 7 Interrupt/Exception Processing Function Table 7-2: Addresses and Bits of Interrupt Control Registers (1/3) Address Register Associated Interrupt FFFFF110H PIC0 PR02 PR01 PR00 INTP0 FFFFF112H PIC1 PR12 PR11 PR10 INTP1 FFFFF114H PIC2 PR22 PR21 PR20 INTP2 FFFFF116H PIC3 PR32 PR31 PR30 INTP3...
Page 238 Chapter 7 Interrupt/Exception Processing Function Table 7-2: Addresses and Bits of Interrupt Control Registers (2/3) Address Register Associated Interrupt FFFFF160H PIC40 IF40 MK40 PR402 PR401 PR400 INTT1EC FFFFF162H PIC41 IF41 MK41 PR412 PR411 PR410 INTP0OV FFFFF164H PIC42 IF42 MK42 PR422 PR421 PR420 INTP0CC0 FFFFF166H...
Page 239 Chapter 7 Interrupt/Exception Processing Function Table 7-2: Addresses and Bits of Interrupt Control Registers (3/3) Address Register Associated Interrupt FFFFF1ACH PIC78 IF78 MK78 PR782 PR781 PR780 INTC1TRX Note Note FFFFF1AEH PIC79 IF79 MK79 PR792 PR791 PR790 INTCB0T FFFFF1B0H PIC80 IF80 MK80 PR802 PR801...
Page 240: Interrupt Mask Registers 0 To 6 (Imr0 To Imr6)
Chapter 7 Interrupt/Exception Processing Function 7.3.5 Interrupt mask registers 0 to 6 (IMR0 to IMR6) The IMR0 to IMR6 registers set the interrupt mask state for the maskable interrupts. The IMK0 to IMK104 bits are equivalent to the MKn bit in the corresponding PICn register. The IMRm register (m = 0 to 6) can be read or written in 16-bit units.
Page 241: Figure 7-12: Interrupt Mask Registers 3 To 6 (Imr3 To Imr6)
Chapter 7 Interrupt/Exception Processing Function Figure 7-12: Interrupt Mask Registers 3 to 6 (IMR3 to IMR6) After reset: FFFFH Address: IMR3 FFFFF106H IMR3L FFFFF106H, IMR3H FFFFF107H IMR3 MK63 MK62 MK61 MK60 MK59 MK58 MK57 MK56 MK55 MK54 MK53 MK52 MK51 MK50 MK49 MK48...
Page 242: In-Service Priority Register (Ispr)
Chapter 7 Interrupt/Exception Processing Function 7.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 243: Maskable Interrupt Status Flag (Id)
Chapter 7 Interrupt/Exception Processing Function 7.3.7 Maskable interrupt status flag (ID) The ID flag is bit 5 of the PSW and controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt requests. Figure 7-14: Maskable interrupt status flag (ID) 8 7 6 5 4 3 2 1 0 After reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z...
Page 244: Interrupt Trigger Mode Selection
Chapter 7 Interrupt/Exception Processing Function 7.3.8 Interrupt trigger mode selection The valid edge of the maskable external interrupt input pin (INTPn) can be selected by program (n = 0 to 12). The edge that can be selected as the valid edge is one of the following. •...
Page 245: Figure 7-15: Interrupt Mode Register 0 (Intm0)
Chapter 7 Interrupt/Exception Processing Function Interrupt mode register 0 (INTM0) The behaviour of the external interrupt input pins INTP0 to INTP2 can be specified by the interrupt mode register 0 (INTM0). The INTM0 register can be read/written in 8-bit or 1-bit units. Figure 7-15: Interrupt Mode Register 0 (INTM0) After reset: Address:...
Page 246: Figure 7-16: Interrupt Mode Register 1 (Intm1)
Chapter 7 Interrupt/Exception Processing Function Interrupt mode register 1 (INTM1) The behaviour of the external interrupt input pins INTP3 to INTP6 can be specified by the interrupt mode register 1 (INTM1). The INTM1 register can be read/written in 8-bit or 1-bit units. Figure 7-16: Interrupt Mode Register 1 (INTM1) After reset: Address:...
Page 247: Figure 7-17: Interrupt Mode Register 2 (Intm2)
Chapter 7 Interrupt/Exception Processing Function Interrupt mode register 2 (INTM2) The behaviour of the external interrupt input pins INTP7 to INTP10 can be specified by the interrupt mode register 2 (INTM2). The INTM2 register can be read/written in 8-bit or 1-bit units. Figure 7-17: Interrupt Mode Register 2 (INTM2) After reset: Address:...
Page 248: Figure 7-18: Interrupt Mode Register 3 (Intm3)
Chapter 7 Interrupt/Exception Processing Function Interrupt mode register 3 (INTM3) The behaviour of the external interrupt input pins INTP11 and INTP12 can be specified by the interrupt mode register 3 (INTM3). The INTM3 register can be read/written in 8-bit or 1-bit units. Figure 7-18: Interrupt Mode Register 3 (INTM3) After reset: Address:...
Page 249: Software Exception
Chapter 7 Interrupt/Exception Processing Function 7.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and is always accepted. For details of the instruction function, refer to the V850 Family User’s Manual Architecture. 7.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: <1>...
Page 250: Restore
Chapter 7 Interrupt/Exception Processing Function 7.4.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2>...
Page 251: Exception Status Flag (Ep)
Chapter 7 Interrupt/Exception Processing Function 7.4.3 Exception status flag (EP) The EP flag is bit 6 of the PSW, and is a status flag used to indicate that exception processing is in progress. This flag is set when an exception occurs. Figure 7-21: Exception Status Flag (EP) 8 7 6 5 4 3 2 1 0 After reset...
Page 252: Exception Trap
7.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850E/PH2, an illegal opcode trap (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 7.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 1000B to 1111B, and a sub-opcode (bit 16) of 0B.
Page 253: Figure 7-23: Exception Trap Processing
Chapter 7 Interrupt/Exception Processing Function Figure 7-23: Exception Trap Processing Exception trap (ILGOP) occurs DBPC restored PC DBPSW PSW.NP PSW.EP CPU processing PSW.ID 00000060H Exception processing Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored <1>...
Page 254: Periods In Which Cpu Does Not Acknowledge Interrupts
Chapter 7 Interrupt/Exception Processing Function 7.6 Periods in Which CPU Does Not Acknowledge Interrupts The CPU acknowledges an interrupt while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending).
Page 255: Chapter 8 Clock Generator
Chapter 8 Clock Generator The clock generator (CG) generates and controls the internal system clock (f ) that is supplied to each internal unit, such as the CPU. 8.1 Features × • Multiplier function using a phase locked loop (PLL) synthesizer (f - Crystal frequency: = 16 MHz - Internal system clock:...
Page 256: Power Save Control
8.3 Power Save Control 8.3.1 Overview The power save function of V850E/PH2 supports the HALT mode only. In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU’s operation clock stops. Since the supply of clocks to on-chip peripheral functions other than the CPU continues, operation continues.
Page 257: Halt Mode
Chapter 8 Clock Generator 8.3.2 HALT mode Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. When HALT mode is set, clock supply is stopped to the CPU only. The clock generator and PLL continue operating.
Page 258: Table 8-2: Operation After Releasing Halt Mode By Interrupt Request Signal
Chapter 8 Clock Generator Releasing HALT mode The HALT mode is released by a non-maskable interrupt request signal (NMI), an unmasked maskable interrupt request signal, or RESET pin input. After the HALT mode has been released, the normal operation mode is restored. (a) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The HALT mode is released by a non-maskable interrupt request signal (INTWDT) or an...
Page 259: Chapter 9 16-Bit Timer/Event Counter P
Chapter 9 16-Bit Timer/Event Counter P 9.1 Features Timer P (TMP) is a 16-bit timer/event counter that can be used in various ways. TMP can perform the following operations. • PWM output • Interval timer • External event counter (operation not possible when clock is stopped) •...
Page 260: Configuration
Chapter 9 16-Bit Timer/Event Counter P 9.3 Configuration TMP includes the following hardware. Table 9-1: Configuration of TMP0 to TMP8 Item Configuration Timer register 16-bit counter Registers TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1) TMPn counter register (TPnCNT) CCR0 buffer register, CCR1 buffer register Timer input Note 2 ×...
Page 261: Figure 9-2: Tmpn Capture/Compare Register 0 (Tpnccr0)
Chapter 9 16-Bit Timer/Event Counter P TMPn capture/compare register 0 (TPnCCR0) The TPnCCR0 register is a 16-bit register that functions both as a capture register and as a compare register. Whether this register functions as a capture register or as a compare register can be controlled with the TPnCCS0 bit of the TPnOPT0 register, but only in the free-running mode.
Page 262: Figure 9-3: Tmpn Capture/Compare Register 1 (Tpnccr1)
Chapter 9 16-Bit Timer/Event Counter P TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register is a 16-bit register that functions both as a capture register and as a compare register. Whether this register functions as a capture register or as a compare register can be controlled with the TPnCCS1 bit of the TPnOPT0 register, but only in the free-running mode.
Page 263: Figure 9-4: Tmpn Counter Register (Tpncnt)
Chapter 9 16-Bit Timer/Event Counter P TMPn counter register (TPnCNT) The TPnCNT register is a read buffer register that can read 16-bit counter values. This register is read-only, in 16-bit units. Reset input clears this register to 0000H, as the TPnCE bit is cleared to 0. Figure 9-4: TMPn Counter Register (TPnCNT) After reset: 0000H...
Page 264: Control Registers
Chapter 9 16-Bit Timer/Event Counter P 9.4 Control Registers TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of timer P. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 265: Figure 9-6: Tmpn Control Register 1 (Tpnctl1) (1/2)
Chapter 9 16-Bit Timer/Event Counter P TMPn control register 1 (TPnCTL1) The TPnCTL1 register is an 8-bit register that controls the operation of timer P. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 9-6: TMPn Control Register 1 (TPnCTL1) (1/2) After reset: Address:...
Page 266 Chapter 9 16-Bit Timer/Event Counter P Figure 9-6: TMPn Control Register 1 (TPnCTL1) (2/2) TPnEEE Count Clock Selection Use the internal clock (selected by bits TPnCKS2 to TPnCKS0) Note Use external clock input (TEVTPn input edge) • When TPnEEE = 1 (external clock input TEVTPn), the valid edge is specified by bits TPnEES1 and TPnEES0.
Page 267: Figure 9-7: Tmpn I/O Control Register 0 (Tpnioc0)
Chapter 9 16-Bit Timer/Event Counter P TMPn I/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 9-7: TMPn I/O Control Register 0 (TPnIOC0) After reset: Address:...
Page 268: Figure 9-8: Tmpn I/O Control Register 1 (Tpnioc1)
Chapter 9 16-Bit Timer/Event Counter P TMPn I/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge for the external input signals (TIPn0, TIPn1). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 269: Figure 9-9: Tmpn I/O Control Register 2 (Tpnioc2)
Chapter 9 16-Bit Timer/Event Counter P TMPn I/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TEVTPn) and external trigger input signal (TTRGPn). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 270: Figure 9-10: Tmpn Option Register 0 (Tpnopt0)
Chapter 9 16-Bit Timer/Event Counter P TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect overflow. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 9-10: TMPn Option Register 0 (TPnOPT0) After reset: Address:...
Page 271: Figure 9-11: Tmpn Input Control Register 0 (Tpic0)
Chapter 9 16-Bit Timer/Event Counter P TMP input control register 0 (TPIC0) The TPIC0 register is an 8-bit register that controls the external input pin source of the capture register 1 of TMP0 to TMP3. This register can be read or written in 8-bit units. Reset input clears this register to 00H.
Page 272: Figure 9-12: Tmp Input Control Register 1 (Tpic1)
Chapter 9 16-Bit Timer/Event Counter P TMP input control register 1 (TPIC1) The TPIC1 register is an 8-bit register that controls the external input pin source of the capture register 1 of TMP4 to TMP7, as well as the internal time trigger source from the AFCAN controllers of both capture registers 0 and 1 of TMP7.
Page 273 Chapter 9 16-Bit Timer/Event Counter P TMP input control register 2 (TPIC2) The TPIC2 register is an 8-bit register that controls the external input pin source of the capture register 1 of TMT0 and TMT1, as well as the internal source of both capture registers 0 and 1 of TMP8.
Page 274: Operation
Chapter 9 16-Bit Timer/Event Counter P 9.5 Operation Timer P can perform the following operations. Operation TPnEST TTRGPn0 Capture/Compare Compare Register (Software (External Mode Rewriting Method Trigger Bit) Trigger Input) Interval timer mode Invalid Invalid Compare only Anytime rewrite Note 1 Invalid Invalid Compare only...
Page 275: Figure 9-14: Basic Operation Flow For Anytime Write
Chapter 9 16-Bit Timer/Event Counter P Figure 9-14: Basic Operation Flow for Anytime Write START Initial settings Timer operation enable (TPnCE = 1) Transfer of TPnCCR0, TPnCCR1 values to CCR0 buffer register and CCR1 buffer register TPnCCR0 rewrite → Transfer to CCR0 buffer register TPnCCR1 rewrite →...
Page 276: Figure 9-15: Timing Diagram For Anytime Write
Chapter 9 16-Bit Timer/Event Counter P Figure 9-15: Timing Diagram for Anytime Write TPnCE = 1 16-bit counter TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register INTTPnCC0 INTTPnCC1 Remarks: 1. D : Setting values of TPnCCR0 register (0000H to FFFFH) : Setting values of TPnCCR1 register (0000H to FFFFH) 2.
Page 277: Figure 9-16: Basic Operation Flow For Reload (Batch Rewrite)
Chapter 9 16-Bit Timer/Event Counter P Reload method (Batch Rewrite) When the TPnCCR0 and TPnCCR1 registers are written during timer operation via the CCRm buffer register, the write data is used as the 16-bit counter comparison value. The TPnCCR0 register and the TPnCCR1 register can be rewritten when TPnCE = 1. In order for the setting value when the TPnCCR0 register and the TPnCCR1 register are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to the CCRm buffer register), it is necessary to rewrite TPnCCR0 and then write to the...
Page 278: Figure 9-17: Timing Chart For Reload
Chapter 9 16-Bit Timer/Event Counter P Figure 9-17: Timing Chart for Reload TPnCE = 1 16-bit counter TPnCCR0 CCR0 buffer 0000H register Note Same value write TPnCCR1 CCR1 buffer 0000H register Note INTTPnCC0 INTTPnCC1 Note: Reload is not performed because the TPnCCR1 register was not rewritten. Remarks: 1.
Page 279: Interval Timer Mode (Tpnmd2 To Tpnmd0 = 000B)
Chapter 9 16-Bit Timer/Event Counter P 9.5.2 Interval timer mode (TPnMD2 to TPnMD0 = 000B) In the interval timer mode, an interrupt request signal (INTTPnCC0) is output upon a match between the setting value of the TPnCCR0 register and the value of the 16-bit counter, and the 16-bit counter is cleared.
Page 280: Figure 9-19: Basic Operation Timing In Interval Timer Mode (1/2)
Chapter 9 16-Bit Timer/Event Counter P Figure 9-19: Basic Operation Timing in Interval Timer Mode (1/2) (a) D > D > D ; rewrite of TPnCCR0 register only; TOPn0, TOPn1 are not output (TPnOE0/TPnOE1 = 0, TPnOL0 = 0, TPnOL = 1) TPnCE = 1 FFFFH 16-bit...
Page 281 Chapter 9 16-Bit Timer/Event Counter P Figure 9-19: Basic Operation Timing in Interval Timer Mode (2/2) (b) D ; no TPnCCR0, TPnCCR1 rewrite; TOPn0 and TOPn1 are output (TPnOE0/TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 1) TPnCE = 1 FFFFH 16-bit counter...
Page 282: External Event Count Mode (Tpnmd2 To Tpnmd0 = 001B)
Chapter 9 16-Bit Timer/Event Counter P 9.5.3 External event count mode (TPnMD2 to TPnMD0 = 001B) In the external event count mode, external event count input (TEVTPn pin input) is used as a count-up signal. When the external event count mode is set, count-up is performed using external event count input (TEVTPn pin input), regardless of the setting of the TPnEEE bit of the TPnCTL0 register.
Page 283: Figure 9-20: Flowchart Of Basic Operation In External Event Count Mode
Chapter 9 16-Bit Timer/Event Counter P Figure 9-20: Flowchart of Basic Operation in External Event Count Mode START Initial settings • External event count mode setting (TPnCTL0. TPnMD2 to TPnMD0 = Note 1 001) • Valid edge setting (TPnIOC2. TPnEES1, TPnEES0) •...
Page 284: Figure 9-21: Basic Operation Timing In External Event Count Mode (1/2)
Chapter 9 16-Bit Timer/Event Counter P Figure 9-21: Basic Operation Timing in External Event Count Mode (1/2) (a) D1 > D2 > D3; rewrite of TPnCCR0 only; no TOPn1 output TPnCE = 1 FFFFH 16-bit counter TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer...
Page 285 Chapter 9 16-Bit Timer/Event Counter P Figure 9-21: Basic Operation Timing in External Event Count Mode (1/2) (b) D1 = D2; no TPnCCR0, TPnCCR1 rewrite; TOPn1 output TPnCE = 1 FFFFH 16-bit counter TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register INTTPnCC0...
Page 286: External Trigger Pulse Output Mode (Tpnmd2 To Tpnmd0 = 010B)
Chapter 9 16-Bit Timer/Event Counter P 9.5.4 External trigger pulse output mode (TPnMD2 to TPnMD0 = 010B) In the external trigger pulse output mode, setting TPnCE = 1 causes external trigger input (TTRGPn pin input) wait with the 16-bit counter stopped at FFFFH. The count-up operation starts upon detection of the external trigger input (TTRGPn pin input) edge.
Page 287: Figure 9-22: Flowchart Of Basic Operation In External Trigger Pulse Output Mode
Chapter 9 16-Bit Timer/Event Counter P Figure 9-22: Flowchart of Basic Operation in External Trigger Pulse Output Mode START Initial settings • Clock selection (TPnCTL1. TPnEEE = 0) (TPnCTL0. TPnCKS2 to TPnCKS0) External trigger • External trigger pulse output mode (TIPn0 pin) input setting (TPnCTL1.
Page 288: Figure 9-23: Basic Operation Timing In External Trigger Pulse Output Mode
Chapter 9 16-Bit Timer/Event Counter P Figure 9-23: Basic Operation Timing in External Trigger Pulse Output Mode TPnCE = 1 FFFFH 16-bit counter External trigger (TIPn0 pin) TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register TOPn0 TOPn1 Remarks: 1. D01, D02: Setting value of TPnCCR0 register (0000H to FFFFH) D11, D12: Setting value of TPnCCR1 register (0000H to FFFFH) 2.
Page 289: One-Shot Pulse Mode (Tpnmd2 To Tpnmd0 = 011B)
Chapter 9 16-Bit Timer/Event Counter P 9.5.5 One-shot pulse mode (TPnMD2 to TPnMD0 = 011B) In the one-shot pulse mode, setting TPnCE = 1 causes waiting on TPnEST bit setting (1) or TTRGPn Note 1 pin edge detection trigger with the 16-bit counter held at FFFFH. The 16-bit counter starts counting up upon trigger input, and upon a match between the value of the 16-bit counter and the value of the CCR1 buffer register transferred from the TPnCR1 register, TOPn1 becomes high level;...
Page 290: Figure 9-24: Flowchart Of Basic Operation In One-Shot Pulse Mode
Chapter 9 16-Bit Timer/Event Counter P Figure 9-24: Flowchart of Basic Operation in One-Shot Pulse Mode START Initial settings • Clock selection (TPnCTL1: TPnEEE = 0) (TPnCTL0: TPnCKS2 to TPnCKS0) • One-shot pulse mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 011B) •...
Page 291: Figure 9-25: Timing Of Basic Operation In One-Shot Pulse Mode
Chapter 9 16-Bit Timer/Event Counter P Figure 9-25: Timing of Basic Operation in One-Shot Pulse Mode TPnCE = 1 TPnEST = 1 FFFFH Note 1 16-bit counter External trigger Note 2 (TTRGPn) TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register INTTPnCC0...
Page 292: Pwm Mode (Tpnmd2 To Tpnmd0 = 100B)
Chapter 9 16-Bit Timer/Event Counter P 9.5.6 PWM mode (TPnMD2 to TPnMD0 = 100B) In the PWM mode, TMPn capture/compare register 1 (TPnCCR1) is used as the duty setting register and TMPn capture/compare register 0 (TPnCCR0) is used as the cycle setting register. Variable duty PWM is output by setting these two registers and operating the timer.
Page 293: Figure 9-26: Flowchart Of Basic Operation In Pwm Mode (1/2)
Chapter 9 16-Bit Timer/Event Counter P Figure 9-26: Flowchart of Basic Operation in PWM Mode (1/2) (a) Values of TPnCCR0, TPnCCR1 registers not rewritten during timer operation START Initial settings • Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) • PWM mode settings (TPnCTL1: TPnMD2 to TPnMD0 = 100B) •...
Page 294 Chapter 9 16-Bit Timer/Event Counter P Figure 9-26: Flowchart of Basic Operation in PWM Mode (2/2) (b) Values of TPnCCR0, TPnCCR1 registers rewritten during timer operation START Initial settings • Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) • PWM mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 100B) •...
Page 295: Figure 9-27: Basic Operation Timing In Pwm Mode (1/2)
Chapter 9 16-Bit Timer/Event Counter P Figure 9-27: Basic Operation Timing in PWM Mode (1/2) (a) TPnCCR1 value rewritten TPnCE = 1 FFFFH 16-bit counter TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register TOPn1 Note TOPn0 Note: TOPn0 output pin is not available for TMP8 (n = 8). Remarks: 1.
Page 296 Chapter 9 16-Bit Timer/Event Counter P Figure 9-27: Basic Operation Timing in PWM Mode (2/2) (b) TPnCCR0, TPnCCR1 values rewritten TPnCE = 1 FFFFH 16-bit counter TPnCCR0 Note CCR0 buffer 0000H register Same value write TPnCCR1 Note CCR1 buffer 0000H register TOPn1 Note 2...
Page 297: Free-Running Mode (Tpnmd2 To Tpnmd0 = 101B)
Chapter 9 16-Bit Timer/Event Counter P 9.5.7 Free-running mode (TPnMD2 to TPnMD0 = 101B) In the free-running mode, both the interval function and the compare function can be realized by operating the 16-bit counter as a free-running counter and selecting capture/compare operation with the TPnCCS1 and TPnCCS0 bits.
Page 298 Chapter 9 16-Bit Timer/Event Counter P (b) Using TPnCCR1 register as capture register Note 1 The value of the 16-bit counter is saved to the TPnCCR1 register upon TIPn1 pin edge detection. (c) Using TPnCCR0 register as compare register An interrupt is output upon a match between the 16-bit counter and the CCR0 buffer register in the free-running mode (interval function).
Page 299: Figure 9-28: Flowchart Of Basic Operation In Free-Running Mode
Chapter 9 16-Bit Timer/Event Counter P Figure 9-28: Flowchart of Basic Operation in Free-Running Mode START Initial settings • Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) • Free-running mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 101B) TPnCCS1, TPnCCS0 setting TPnCCS1 = 0 TPnCCS1 = 1 TPnCCS1 = 0 TPnCCS1 = 1...
Page 300: Figure 9-29: Basic Operation Timing In Free-Running Mode (Tpnccs1 = 0, Tpnccs0 = 0)
Chapter 9 16-Bit Timer/Event Counter P TPnCCS1 = 0, TPnCCS0 = 0 settings (interval function description) When TPnCE = 1 is set, the 16-bit counter counts from 0000H to FFFFH and the free-running count-up operation continues until TPnCE = 0 is set. In this mode, when a value is written to the TPnCCR0 and TPnCCR1 registers, they are transferred to the CCR0 buffer register and the CCR1 buffer register (anytime write).
Page 301: Figure 9-30: Basic Operation Timing In Free-Running Mode (Tpnccs1 = 1, Tpnccs0 = 1)
Chapter 9 16-Bit Timer/Event Counter P TPnCCS1 = 1, TPnCCS0 = 1 settings (capture function description) When TPnCE = 1, the 16-bit counter counts from 0000H to FFFFH and free-running count-up operation continues until TPnCE = 0 is set. During this time, values are captured by capture trigger operation and are written to the TPnCCR0 and TPnCCR1 registers.
Page 302: Figure 9-31: Basic Operation Timing In Free-Running Mode (Tpnccs1 = 1, Tpnccs0 = 0)
Chapter 9 16-Bit Timer/Event Counter P TPnCCS1 = 1, TPnCCS0 = 0 settings When TPnCE = 1 is set, the counter counts from 0000H to FFFFH and free-running count-up operation continues until TPnCE = 0 is set. The TPnCCR0 register is used as a compare register. An interrupt signal is output upon a match between the value of the 16-bit counter and the setting value transferred to the CCR0 buffer register from the TPnCCR0 register as an interval function.
Page 303: Figure 9-32: Basic Operation Timing In Free-Running Mode (Tpnccs1 = 0, Tpnccs0 = 1)
Chapter 9 16-Bit Timer/Event Counter P TPnCCS1 = 0, TPnCCS0 = 1 settings When TPnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH and free-running count-up operation continues until TPnCE = 0 is set. The TPnCCR1 register is used as a compare register.
Page 304: Pulse Width Measurement Mode (Tpnmd2 To Tpnmd0 = 110B)
Chapter 9 16-Bit Timer/Event Counter P 9.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110B) In the pulse width measurement mode, free-running count is performed. The value of the 16-bit counter is saved to capture register 0 (TPnCCR0), or capture register 1 (TPnCCR1) respectively, and the 16-bit counter is cleared upon edge detection of the TIPn0 pin, or TIPn1 respectively.
Page 305: Figure 9-33: Flowchart Of Pulse Period Measurement
Chapter 9 16-Bit Timer/Event Counter P Pulse period measurement The pulse period of a signal can be measured in the pulse width measurement mode, when the edge detection of one of the inputs TIPn0 and TIPn1 is set either to “rising edge” or “falling edge”. The detection of the other input should be set to “no edge detection”.
Page 306: Figure 9-34: Basic Operation Timing Of Pulse Period Measurement
Chapter 9 16-Bit Timer/Event Counter P Figure 9-34: Basic Operation Timing of Pulse Period Measurement TPnCE = 1 FFFFH FFFFH 16-bit counter TIPn0 TPnCCR0 0000H INTTPnCCR0 cleared by writing 0 TPnOVF from CPU INTTPnOV Remarks: 1. D : Values captured to TPnCCR0 register (0000H to FFFFH) 2.
Page 307: Figure 9-35: Flowchart Of Alternating Pulse Width And Pulse Space Measurement
Chapter 9 16-Bit Timer/Event Counter P Alternating pulse width and pulse space measurement The pulse period of a signal can be measured in the pulse width measurement mode alternating in one capture register, when the edge detection of one of the inputs TIPn0 and TIPn1 is set to “both rising and falling edges”.
Page 308: Figure 9-36: Basic Operation Timing Of Alternating Pulse Width And Pulse Space Measurement
Chapter 9 16-Bit Timer/Event Counter P Figure 9-36: Basic Operation Timing of Alternating Pulse Width and Pulse Space Measurement TPnCE = 1 FFFFH FFFFH 16-bit counter TIPn0 TPnCCR0 0000H INTTPnCCR0 cleared by writing 0 TPnOVF from CPU INTTPnOV Remarks: 1. D : Values captured to TPnCCR0 register (0000H to FFFFH) 2.
Page 309: Figure 9-37: Flowchart Of Simultaneous Pulse Width And Pulse Space Measurement
Chapter 9 16-Bit Timer/Event Counter P Simultaneous pulse width and pulse space measurement Pulse width and pulse space can be measure simultaneously in the pulse width measurement mode, when the signal is input to both inputs TIPn0 and TIPn1, where both inputs detect opposite edges.
Page 310: Figure 9-38: Basic Operation Timing Of Simultaneous Pulse Width And Pulse Space Measurement
Chapter 9 16-Bit Timer/Event Counter P Figure 9-38: Basic Operation Timing of Simultaneous Pulse Width and Pulse Space Measurement TPnCE = 1 FFFFH FFFFH 16-bit counter Note TIPn0, TIPn1 TPnCCR0 0000H TPnCCR1 0000H INTTPnCCR0 INTTPnCCR1 cleared by writing 0 TPnOVF from CPU INTTPnOV Note: The signal to measure has to be assigned to both inputs, TIPn0 and TIPn1.
Page 311: Counter Synchronous Operation Function
Chapter 9 16-Bit Timer/Event Counter P 9.5.9 Counter synchronous operation function Timer P supports a function to start several timers P simultaneously. For this purpose two timer groups are defined, TMP0 to TMP3, as well as TMP4 to TMP7. For each timer group the counting of one to three slave counters (TMP1 to TMP3, or TMP5 to TMP7) can be synchronized with the corresponding master counter (TMP0 or TMP4).
Page 312 Chapter 9 16-Bit Timer/Event Counter P [MEMO] User’s Manual U16580EE3V1UD00...
Page 313: Chapter 10 16-Bit Inverter Timer/Counter R
Chapter 10 16-bit Inverter Timer/Counter R 10.1 Features Timer R is a 16-bit timer/counter that provides various motor control functions. • Count clock resolution: 31.25 ns min. (when using 32 MHz count clock) • General-purpose timer and operation mode supporting various motor control methods •...
Page 314: Configuration
Chapter 10 16-bit Inverter Timer/Counter R 10.2 Configuration Timer R is configured of the following hardware. Table 10-1: Timer R Configuration Item Configuration 16-bit counter × 1 Counters 16-bit sub-counter × 1 10-bit dead time counter × 3 Registers Timer Rn counter read register (TRnCNT) Timer Rn sub-counter read register (TRnSBC) Timer Rn dead time setting registers 0, 1 (TRnDTC0, TRnDTC1) Timer Rn capture/compare registers 0 to 3 (TRnCCR0-TRnCCR3)
Page 315: Figure 10-1: Timer Rn Block Diagram
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-1: Timer Rn Block Diagram Internal bus TRnSBC TRnCNT TRnSUF load Counter TRnCUF 16-bit TMRn sub-counter control TORn0 TORn1 CCR0 buffer TRnSUF TORn2 CCR1 buffer TRnDTC1 TORn3 CCR2 buffer TRnDTC0 TORn4 Output TORn5 CCR3 buffer control TORn6...
Page 316: Figure 10-2: Tmrn Capture/Compare Register 0 (Trnccr0)
Chapter 10 16-bit Inverter Timer/Counter R TMRn capture/compare register 0 (TRnCCR0) The TRnCCR0 register is a 16-bit register provided with a capture function and a compare function. In the case of the free-running mode only, bit TRnCCS0 of the TRnOPT0 register is used to select use of the register as a capture register or as a compare register.
Page 317: Figure 10-3: Tmrn Capture/Compare Register 1 (Trnccr1)
Chapter 10 16-bit Inverter Timer/Counter R TMRn capture/compare register 1 (TRnCCR1) The TRnCCR1 register is a 16-bit register that functions both as a capture register and a compare register. When a compare register is rewritten in the reload mode, the reload request flag (TRnRSF) becomes 1 when write access is performed to the TRnCCR1 register, and all the registers are rewritten at the same time at the next reload timing.
Page 318: Figure 10-4: Tmrn Capture/Compare Register 2 (Trnccr2)
Chapter 10 16-bit Inverter Timer/Counter R TMRn capture/compare register 2 (TRnCCR2) The TRnCCR2 register is a 16-bit register that functions both as a capture register and compare register. In the free-running mode only, bit TRnCCS2 of the TRnOPT0 register is used to select whether to use the TRnCCR2 register as a capture register or a compare register.
Page 319: Figure 10-5: Tmrn Capture/Compare Register 3 (Trnccr3)
Chapter 10 16-bit Inverter Timer/Counter R TMRn capture/compare register 3 (TRnCCR3) the TRnCCR3 register is a 16-bit register that functions both as a capture register and a compare register. In the free-running mode only, bit TRnCCS3 of the TRnOPT0 register is used to select whether to use the TRnCCR3 register as a capture register or a compare register.
Page 320: Figure 10-6: Tmrn Compare Register 4 (Trnccr4)
Chapter 10 16-bit Inverter Timer/Counter R TMRn compare register 4 (TRnCCR4) The TRnCCR4 register is a 16-bit register that functions as a compare function. In the high-accuracy T-PWM mode and the PWM mode with dead time, the interrupt for matches between the counter and the TRnCCR4 register can be selected as the timing for A/D conversion trigger input.
Page 321: Figure 10-7: Tmrn Compare Register 5 (Trnccr5)
Chapter 10 16-bit Inverter Timer/Counter R TMRn compare register 5 (TRnCCR5) The TRnCCR5 register is a 16-bit compare register. In the high-accuracy T-PWM mode and the PWM mode with dead time, the interrupt for matches between the counter and the TRnCCR5 register can be selected as the timing for A/D conversion trigger input.
Page 322: Figure 10-8: Tmrn Counter Read Register (Trncnt)
Chapter 10 16-bit Inverter Timer/Counter R TMRn counter read register (TRnCNT) The TRnCNT register is a timer read register that can read the values of the 16-bit counter. This register can only be read in 16-bit units. RESET input or setting TRnCE = 0 clears this register to 0000H. During the interval from when CE = 1 until count up, the value of the TRnCNT register is FFFFH.
Page 323: Figure 10-10: Tmrn Dead Time Setting Register 0 (Trndtc0)
Chapter 10 16-bit Inverter Timer/Counter R TMRn dead time setting register 0 (TRnDTC0) The TRnDTC0 register is a 10-bit register that specifies the dead time value. This register can be read and written in 16-bit units. RESET input clears this register to 0000H. The dead time counter operates in the high-accuracy T-PWM mode and the PWM mode with dead time.
Page 324: Control Registers
Chapter 10 16-bit Inverter Timer/Counter R 10.3 Control Registers TMRn control register 0 (TRnCTL0) The TRnCTL0 register is an 8-bit register that controls the operation of timer Rn. This register can be read and written in 8-bit or 1-bit units. RESET input changes the value of this register to initial setting 00H.
Page 325: Table 10-2: Tmrn Count Clock And Count Delay
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-12: TMRn Control Register 0 (TRnCTL0) (2/2) TRnCKS2 TRnCKS1 TRnCKS0 Internal Count Clock Selection of Timer Rn /256 /1024 Caution: Set bits TRnCKS2 to TRnCKS0 when TRnCE = 0. When bit TRnCE is set from 0 to 1, bits TRnCKS2 to TRnCKS0 can be simultaneously set.
Page 326: Figure 10-13: Tmrn Control Register 1 (Trnctl1) (1/2)
Chapter 10 16-bit Inverter Timer/Counter R TMRn control register 1 (TRnCTL1) The TRnCTL1 register is an 8-bit register that controls the operation of timer Rn. This register can be read and written in 8-bit or 1-bit units. RESET input changes the value of this register to initial setting 00H. Cautions: 1.
Page 327 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-13: TMRn Control Register 1 (TRnCTL1) (2/2) TRnMD3 TRnMD2 TRnMD1 TRnMD0 Timer Mode Selection Interval timer mode Note 1 External event count mode Note 2 External trigger pulse output mode One-shot pulse mode PWM mode Free-running mode Note 1...
Page 328: Figure 10-14: Tmrn I/O Control Register 0 (Trnioc0)
Chapter 10 16-bit Inverter Timer/Counter R TMRn I/O control register 0 (TRnIOC0) The TRnIOC0 register is an 8-bit register that controls the timer output (pins TORn0 to TORn3). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 329: Figure 10-15: Tmr1 I/O Control Register 1 (Tr1Ioc1)
Chapter 10 16-bit Inverter Timer/Counter R TMR1 I/O control register 1 (TR1IOC1) The TR1IOC1 register is an 8-bit register that controls the valid edge of external signal inputs (pins TIR10 to TIR13). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 330: Figure 10-16: Tmr1 I/O Control Register 2 (Tr1Ioc2)
Chapter 10 16-bit Inverter Timer/Counter R TMR1 I/O control register 2 (TR1IOC2) The TR1IOC2 register is an 8-bit register that controls the valid edge of external event count input (pin TEVTR1) and external trigger input (pin TTRGR1). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 331: Figure 10-17: Tmrn I/O Control Register 3 (Trnioc3)
Chapter 10 16-bit Inverter Timer/Counter R TMRn I/O control register 3 (TRnIOC3) The TRnIOC3 register is an 8-bit register that controls timer output (pins TORn4 to TORn7). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution: If the dead time cannot be secured or if spikes (noise) may occur on the output pin, set the TRnIOC3 register when TRnCE = 0.
Page 332: Figure 10-18: Tmrn I/O Control Register 4 (Trnioc4)
Chapter 10 16-bit Inverter Timer/Counter R TMRn I/O control register 4 (TRnIOC4) The TRnIOC4 register is an 8-bit register that controls timer output error detection. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution: Set the TRnIOC4 register when TRnCE = 0.
Page 333: Figure 10-19: Tmrn Option Register 0 (Trnopt0) (1/2)
Chapter 10 16-bit Inverter Timer/Counter R TMRn option register 0 (TRnOPT0) The TRnOPT0 register is an 8-bit register that sets the capture/compare operation and detects overflow. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution: When TR1CE = 1, do not rewrite bits TR1CCS3 to TR1CCS0.
Page 334 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-19: TMRn Option Register 0 (TRnOPT0) (2/2) TRnCMS Compare Register Transfer Timing Mode Selection Reload mode (batch rewrite): When the TRnCCR1 register is written to, all the registers are updated at the next reload timing (reload). Even if registers other than the TRnCCR1 register are written, reload is not executed.
Page 335: Figure 10-20: Tmrn Option Register 1 (Trnopt1) (1/2)
Chapter 10 16-bit Inverter Timer/Counter R TMRn option register 1 (TRnOPT1) The TRnOPT1 register is an 8-bit register used to enable/disable peak/valley interrupts and set interrupt thinning out. This register can be read and written in 16-bit or 8-bit units. RESET input clears this register to 00H.
Page 336 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-20: TMRn Option Register 1 (TRnOPT1) (2/2) TRnRDE Reload Timing Thinning Out control Don’t perform reload thinning out Reload timing occurs at each peak/valley. Perform reload thinning out Reload timing occurs at the same interval as interrupt thinning out. Remark: Bit TRnRDE is valid only in the PWM mode, high-accuracy T-PWM mode, triangular wave PWM output mode, and PWM mode with dead time.
Page 337: Figure 10-21: Tmrn Option Register 2 (Trnopt2) (1/2)
Chapter 10 16-bit Inverter Timer/Counter R (10) TMRn option register 2 (TRnOPT2) The TRnOPT2 register is an 8-bit register that controls A/D conversion trigger output (TRnADTRG0 signal). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution: The settings of the TRnCCR5 and TRnCCR4 registers have an influence on the PWM output of pins TORn5 and TORn4 at the same time as the TRnADTRG0 signal output.
Page 338 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-21: TMRn Option Register 2 (TRnOPT2) (2/2) TRnAT03 TRnAT02 A/D Converter Trigger Signal (TRnADTRG0) Generation with Occurrence of Compare Match Interrupt (INTTRnCCR4) No trigger signal is generated when INTTRnCCR4 occurs. Trigger signal is generated, when INTTRnCCR4 occurs and TMRn is counting up.
Page 339: Figure 10-22: Tmrn Option Register 3 (Trnopt3) (1/2)
Chapter 10 16-bit Inverter Timer/Counter R (11) TMRn option register 3 (TRnOPT3) The TRnOPT3 register is an 8-bit register that controls A/D conversion trigger output (signal TRnADTRG1). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution: The settings of the TRnCCR5 and TRnCCR4 registers have an influence on the PWM outputs of pins TORn5, TORn4 at the same time as the TRnADTRG0 signal output.
Page 340 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-22: TMRn Option Register 3 (TRnOPT3) Format (2/2) TRnAT13 TRnAT12 A/D Converter Trigger Signal (TRnADTRG1) Generation with Occurrence of Compare Match Interrupt (INTTRnCCR4) No trigger signal is generated when INTTRnCCR4 occurs. Trigger signal is generated, when INTTRnCCR4 occurs and TMRn is counting up.
Page 341: Figure 10-23: Tmrn Option Register 6 (Trnopt6)
Chapter 10 16-bit Inverter Timer/Counter R (12) TMRn option register 6 (TRnOPT6) The TRnOPT6 register is an 8-bit register that controls the various flags of timer Rn. This register can be read and written in 8-bit or 1-bit units. RESET input or setting TRnCE = 0 clears this register to 00H. Remark: For the functions of the various flags, refer to 10.6 Flags.
Page 342: Figure 10-24: Tmrn Option Register 7 (Trnopt7)
Chapter 10 16-bit Inverter Timer/Counter R (13) TMRn option register 7 (TRnOPT7) The TRnOPT7 register is an 8-bit register that controls time output switching. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Figure 10-24: TMRn Option Register 7 (TRnOPT7) After reset: Address:...
Page 343: Basic Operation
Chapter 10 16-bit Inverter Timer/Counter R 10.4 Basic Operation 10.4.1 Basic counter operation This section describes the basic operation of the 16-bit counter. For details, refer to the description of the operation of each mode. Count start operation The 16-bit counter of timer R starts counting from initial value FFFFH in all the modes except the high-accuracy T-PWM mode.
Page 344 Chapter 10 16-bit Inverter Timer/Counter R Interrupt operation In the case of timer R, the following interrupts are output. • INTTRnCC0: Functions as TRnCCRn0 buffer register match interrupt. • INTTRnCC1: Functions as TRnCCRn1 buffer register match interrupt. • INTTRnCC2: Functions as TRnCCRn2 buffer register match interrupt. •...
Page 345: Compare Register Rewrite Operation
Chapter 10 16-bit Inverter Timer/Counter R 10.4.2 Compare register rewrite operation In the PWM mode, high-accuracy T-PWM mode, PWM mode with dead time, external trigger pulse output mode, and triangular wave PWM mode, the reload function is valid. (In all other modes, reload-related settings are invalid.) The compare/control registers with the reload function are listed below.
Page 346 Chapter 10 16-bit Inverter Timer/Counter R For details about the interrupt thinning out function specified by setting the TRnOPT1 register, refer to 10.7 Interrupt Thinning Out Function. Mode Rewrite Timing Interval mode Anytime rewrite External event count mode Anytime rewrite External trigger pulse output mode Reload One-shot pulse mode...
Page 347: Figure 10-25: Anytime Rewrite Timing
Chapter 10 16-bit Inverter Timer/Counter R Anytime rewrite Anytime rewrite is set by setting TRnOPT0 register bit TRnCMS = 1. The TRnOPT1 register bit TRnRDE setting is ignored. In this mode, the value written to each compare register is immediately transferred to the internal buffer register and compared to the counter value.
Page 348 Chapter 10 16-bit Inverter Timer/Counter R (a) Cautions related to rewriting TRnCCR0 register in high-accuracy T-PWM mode When the TRnCCR0 register is rewritten during operation using the anytime rewrite function, anytime transfer of the value to the TRnCCR0 buffer register is not performed. The timing is shown below.
Page 349 Chapter 10 16-bit Inverter Timer/Counter R If a value smaller than the counter value is written before match occurrence, no match occurs, so the following output wave results. Counter “i” “i” “r” “r” TRnCCR1 “i” “r” TRnCCR1 “r” “i” buffer TORn1 TORn2 Forced rise...
Page 350 Chapter 10 16-bit Inverter Timer/Counter R Rewrite in <3> interval (rewrite before match occurrence) In the case of rewrite before a match between the TRnCCR1 to TRnCCR3 registers and the counter occurs, a match with the counter occurs following rewrite and the rewrite value is instantly reflected.
Page 351 Chapter 10 16-bit Inverter Timer/Counter R Rewrite in <4> interval (rewrite after match occurrence) In the case of rewrite after a match between the TRnCCR1 to TRnCCR3 registers and the counter occurs, further match occurrences are ignored, so the rewrite value is not reflected. Counter “i”...
Page 352: Figure 10-26: Basic Operation Flow During Batch Rewrite
Chapter 10 16-bit Inverter Timer/Counter R Batch rewrite (reload mode) Batch rewrite is set by setting TRnOPT0 register bit TRnCMS = 0, TRnOPT1 register bit TRnRDE = 0, TRnICE = 1 (reload enabled at peaks), and TRnIOE = 1 (reload enabled at valleys). In this mode, the values written to the various compare registers are all transferred at the same time to the respective buffer registers at the reload timing.
Page 353: Figure 10-27: Batch Rewrite Timing (1/2)
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-27: Batch Rewrite Timing (1/2) Counter Reload upon Reload rewrite TRnCCR1 write timing TRnCCR0 TRnCCR0 buffer TRnCCR1 TRnCCR1 buffer TRnCCR2 TRnCCR2 buffer TRnCCR3 TRnCCR3 buffer TRnCCR4 TRnCCR4 buffer TRnCCR5 TRnCCR5 buffer TRnOPT1 TRnOPT1 buffer Batch update at reload timing INTTRnCD0...
Page 354 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-27: Batch Rewrite Timing (2/2) Counter Reload upon TRnCCR1 write TRnCCR0 TSnCCR0 buffer TRnCCR1 TSnCCR1 buffer TRnCCR2 TSnCCR2 buffer TRnCCR3 TSnCCR3 buffer TRnCCR4 TSnCCR4 buffer TRnCCR5 TSnCCR5 buffer TRnOPT1 TSnOPT1 buffer Batch update at reload timing INTTRnCD0 Setting of reload...
Page 355 Chapter 10 16-bit Inverter Timer/Counter R (a) TRnCCR0 register rewrite operation in high-accuracy T-PWM mode When rewriting the TRnCCR0 register in the batch rewrite mode, the output waveform changes according to whether reload occurs at a peak or at a valley (TRnICE = 1, TRnIOE = 1 settings). Counter <1>...
Page 356 Chapter 10 16-bit Inverter Timer/Counter R “r d1” value loaded to counter “r d1” “m” Counter “i” “k” “k” Reloadable timing TRnCCR0 “m” “r” TRnCCR0 “m” “r” buffer TRnCCR1 “i” “k” TRnCCR1 “k” “i” buffer TORn1 TORn2 INTTRnCD INTTRnOD Remark: d1: TRnDTC1 setting value The counter loads the TRnCCR0 value minus “d1”...
Page 357 Chapter 10 16-bit Inverter Timer/Counter R (b) TRnCCR1 to TRnCCR3 register rewrite operation in high-accuracy T-PWM mode “r” “r” Counter “i” “k” Reloadable timing TRnCCR1 “i” “k” “r” TRnCCR1 “r” “i” “k” buffer TORn1 TORn2 INTTRnCC1 <1> <2> <1> <2> Remark: When TRnDTC0 = 0, TRnDTC1 = 0 Rewrite in <1>...
Page 358: List Of Outputs In Each Mode
Chapter 10 16-bit Inverter Timer/Counter R 10.4.3 List of outputs in each mode Timer outputs in each mode The timer outputs (pins TORn0 to TORn7) in each mode are listed below. Table 10-3: List of Timer Outputs in Each Mode (1/2) Operation Mode TORn0 TORn1...
Page 359 Chapter 10 16-bit Inverter Timer/Counter R Table 10-3: List of Timer Outputs in Each Mode (2/2) Operation Mode TORn4 TORn5 TORn6 TORn7 Interval mode Toggle output upon Toggle output upon TRnCCR4 compare TRnCCR5 compare match match External event count Toggle output upon Toggle output upon mode TRnCCR4 compare...
Page 360: Figure 10-28: Torn7 Pin Output Timing 1
Chapter 10 16-bit Inverter Timer/Counter R (a) TORn7 pin output control The A/D conversion signals can be output to pin TORn7. Pin TORn7 is set (to 1) by the TRnADTRG0 signal trigger, and it is reset (to 0) by the TRnADTRG1 signal trigger. If the TRnADTRG0 trigger occurs while pin TORn7 is set (to 1), its set (1) status is maintained.
Page 361: Table 10-4: List Of Interrupts In Each Mode (1/2)
Chapter 10 16-bit Inverter Timer/Counter R Interrupts in each mode The interrupts in each mode (INTTRnCC0 to INTTRnCC5, INTTRnOV, INTTRnER) are listed below. Table 10-4: List of Interrupts in Each Mode (1/2) Operation Mode INTTRnCC0 INTTRnCC1 INTTRnCC2 INTTRnCC3 Interval mode TRnCCR0 compare TRnCCR1 compare TRnCCR2 compare...
Page 362 Chapter 10 16-bit Inverter Timer/Counter R Table 10-4: List of Interrupts in Each Mode (2/2) Operation Mode INTTRnCC4 INTTRnCC5 INTTRnOV INTTRnER Interval mode TRnCCR4 compare TRnCCR5 compare match interrupt match interrupt External event count mode TRnCCR4 compare TRnCCR5 compare match interrupt match interrupt External trigger pulse TRnCCR4 compare...
Page 363: Table 10-5: List Of A/D Conversion Triggers, Peak Interrupts And Valley Interrupts In Each Mode
Chapter 10 16-bit Inverter Timer/Counter R A/D conversion triggers, peak interrupts, and valley interrupts in each mode The A/D conversion triggers, peak interrupts, and valley interrupts in each mode are listed below. Table 10-5: List of A/D Conversion Triggers, Peak Interrupts and Valley Interrupts in Each Mode Operation Mode TRnADTRG0 TRnADTRG1...
Page 364: Match Interrupts
Chapter 10 16-bit Inverter Timer/Counter R 10.5 Match Interrupts Match interrupts consist of compare match interrupts (INTTRnCC0 to INTTRnCC5), peak interrupts (INTTRnCD), and valley interrupts (INTTRnOD). For details about error interrupts, refer to 10.9 Error Interrupts. Compare match interrupts (INTTRnCC0 to INTTRnCC5) are interrupts that occur following a match between the TRnCCR0 to TRnCCR5 registers and the counter, and are output in all modes (no operation mode restrictions).
Page 365 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-29: Interrupt Signal Output Example (2/2) FFFFH Counter TRnCCR0 TRnCCR1 TRnCCR2 TRnCCR3 TRnCCR3 INTTRnCC0 INTTRnCC1 INTTRnCC2 INTTRnCC3 INTTRnCC4 INTTRnCD0 (peak interrupt) INTTRnOD (valley interrupt) User’s Manual U16580EE3V1UD00...
Page 366: Compare Match Interrupt Related Cautions
Chapter 10 16-bit Inverter Timer/Counter R 10.5.1 Compare match interrupt related cautions Cautions in high-accuracy T-PWM mode Compare match interrupts occur upon a match between the counter and a compare register (TRnCCR0 to TRnCCR5). However, in the high-accuracy T-PWM mode, the compare register can be set exceeding the counter’s count operation range.
Page 367 Chapter 10 16-bit Inverter Timer/Counter R Cautions in PWM mode with dead time Compare match interrupts are output upon a match between the counter and compare registers (TRnCCR0 to TRnCCR5). However, in the high-accuracy T-PWM mode, the compare register can be set exceeding the counter’s count operation range.
Page 368: Flags
Chapter 10 16-bit Inverter Timer/Counter R 10.6 Flags 10.6.1 Up count flags Timer Rn has two counters, a counter and a sub-counter. TRnCUF is the counter’s up/down status flag. It operates in the triangular wave PWM mode and high- accuracy T-PWM mode, and is fixed to 0 in all other modes. TRnSUF is the sub-counter’s up/down status flag.
Page 369: Normal Phase/Inverted Phase Simultaneous Active Detection Flag
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-30: Up Count Flags Timings (2/2) TRnCCR0- TSnCCR0 TRnDTC1 TRnDTC0 0000H Sub-counter Counter TRnCUF TRnSUF TORn0 TORn0 TRnTOS = 0 sub-counter up/down TRnTOS = 1 sub-counter up/down status output to TORn0 status output to TORn0 10.6.2 Normal phase/inverted phase simultaneous active detection flag Timer Rn has a flag (TRnTBF) that detects normal phase/inverted phase simultaneous active states.
Page 370: Reload Hold Flag
Chapter 10 16-bit Inverter Timer/Counter R 10.6.3 Reload hold flag In the case of timer Rn, the reload hold flag (TRnRSF) is set to “1” upon occurrence of a reload request (when the TRnCCR1 register is written to). When reload occurs and the values are transferred to all the buffer registers, the reload hold flag is cleared to “0”.
Page 371: Interrupt Thinning Out Function
Chapter 10 16-bit Inverter Timer/Counter R 10.7 Interrupt Thinning Out Function The operations related to the interrupt thinning out function are indicated below. • The interrupts subject to thinning out are INTTRnCD (peak interrupt) and INTTRnOD (valley interrupt). • TRnOPT1 register bit TRnICE is used to enable INTTRnCD interrupt output and to specify thinning out count targets.
Page 372: Operation Of Interrupt Thinning Out Function
Chapter 10 16-bit Inverter Timer/Counter R 10.7.1 Operation of interrupt thinning out function Figure 10-33: Interrupt Thinning Out Operations (1/2) (a) when TRnICE = 1, TRnIOE = 1 (peak/valley interrupt output) Counter TRnID4-0 = 00H (no th inning out ) INTTRnCD INTTRnOD TRnID4-0 = 01H (mask 1 )
Page 373 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-33: Interrupt Thinning Out Operations (2/2) (b) when TRnICE = 1, TRnIOE = 0 (peak interrupt only output) Counter TRnID4-0 = 00H (no th inning out ) INTTRnCD INTTRnOD TRnID4-0 = 01H (mask 1) INTTRnCD INTTRnOD TRnID4-0 = 02H (mask 2)
Page 374: Operation Examples When Peak Interrupts And Valley Interrupts Occur Alternately
Chapter 10 16-bit Inverter Timer/Counter R 10.7.2 Operation examples when peak interrupts and valley interrupts occur alternately Register settings Set both TRnOPT1 register bit TRnICE and TRnOPT1 register bit TRnIOE to 1. Operation example Figure 10-34: Examples when Peak Interrupts and Valley Interrupts Occur Alternately (1/2) (a) when TRnCMS = 0, TRnRDE = 1 (Reload Thinning Out Control) (Recommended Settings) Counter INTTRnCD...
Page 375: Interrupt Thinning Out Function During Counter Saw Tooth Wave Operation
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-34: Examples when Peak Interrupts and Valley Interrupts Occur Alternately (2/2) (c) when TRnCMS = 1, TRnRDE = x (anytime rewrite) Counter INTTRnCD INTTRnOD TRnIDS4 to 0 Instantly reflected TRnID4 to 0 Clear Interrupt thinning out counter * Instantly reflected after rewrite.
Page 376: A/D Conversion Trigger Function
Chapter 10 16-bit Inverter Timer/Counter R 10.8 A/D Conversion Trigger Function This section describes the operation of the A/D conversion triggers output in the PWM mode, triangular wave PWM mode, high-accuracy T-PWM mode, and PWM mode with dead time. In these modes, the TRnCCR4 and TRnCCR5 registers are used as match interrupts and for the A/D conversion trigger function, with no influence on timer outputs in terms of the compare operation.
Page 377: A/D Conversion Trigger Operation
Chapter 10 16-bit Inverter Timer/Counter R 10.8.1 A/D conversion trigger operation Timer R has a function for generating A/D conversion start triggers (TRnADTRG0, TRnADTRG1 signals), freely selecting 4 trigger sources. The following 4 triggers sources are provided, which can be specified with TRnOPT2 register bits TRnAT05 to TRnAT00 and TRnOPT3 register bits TRnAT15 to TRnAT10.
Page 378: Figure 10-36: A/D Conversion Trigger Timings (1/2)
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-36: A/D Conversion Trigger Timings (1/2) (a) when TRnICE = 1, TRnIOE = 1, TRnID4-TRnID0 = 00H (No Interrupt Thinning Out) Counter INTTRnCD INTTRnOD INTTRnCC4 INTTRnCC5 TRnCUF [When TRnAT05 to 00 = 000001] Output INTTRnOD TRnADTRG0 [When TRnAT05 to 00 = 000010] Output INTTRnCD TRnADTRG0...
Page 379 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-36: A/D Conversion Trigger Timings (2/2) (b) when TRnICE = 0, TRnIOE = 1, TRnID4 to TRnID0 = 02H (Interrupt Thinning Out) Counter INTTRnCD INTTRnOD [When TRnAT05-00 = 000011] Both INTTRnCD and INTTRnOD are selected, but peak not output due to interrupt thinning out specification. TRnADTRG0 (c) 0when TRnICE = 0, TRnIOE = 1, TRnID4 to TRnID0 = 02H (Interrupt Thinning Out) Counter...
Page 380: Error Interrupts
Chapter 10 16-bit Inverter Timer/Counter R 10.9 Error Interrupts 10.9.1 Error interrupt and error signal output functions Timer R has an error interrupt (INTTRnER) and an error signal output (TRnER). As the errors detected with timer R, normal phase/inverted phase simultaneous active (fault of dead time controller) are detected as errors in the high-accuracy T-PWM mode, PWM mode with dead time, and PWM mode.
Page 381: Figure 10-38: Error Interrupt And Error Signal Output Controller In Pwm Mode
Chapter 10 16-bit Inverter Timer/Counter R In PWM mode The case of normal phase/inverted phase simultaneous active in the PWM mode is described below. As shown in the figure below, an error interrupt (INTTRnER) is output when the TRnCCR1 and TRnCCR2 registers are set so that pins TORn1 and TORn2 simultaneously output “H”.
Page 382: Figure 10-39: Error Interrupt And Error Signal Output Controller In Triangular Wave Pwm Mode
Chapter 10 16-bit Inverter Timer/Counter R In triangular wave PWM mode The case of normal phase/inverted phase simultaneous active in the triangular wave PWM mode is described below. As shown in the figure below, an error output (INTTRnER) is output when the TRnCCR0 and TRnCCR1 registers are set so that pins TORn1 and TORn2 simultaneously output “H”.
Page 383: Figure 10-40: Error Interrupt And Error Signal Output Controller
Chapter 10 16-bit Inverter Timer/Counter R In high-accuracy T-PWM mode/PWM mode with dead time In the high-accuracy T-PWM mode and PWM mode with dead time, no error occurs except when the dead time setting is “0”. If an error occurs, this is likely due to an internal circuit fault. Figure 10-40: Error Interrupt and Error Signal Output Controller in High-Accuracy T-PWM Mode / PWM Mode with Dead Time Counter...
Page 384: Operation In Each Mode
Chapter 10 16-bit Inverter Timer/Counter R 10.10 Operation in Each Mode 10.10.1 Interval timer mode Outline of interval timer mode In the interval timer mode, a compare match interrupt (INTTRnCC0) occurs and the counter is cleared upon a match between the setting value of the TRnCCR0 register and the counter value. The occurrence interval for this counter and TRnCCR0 register match interrupt becomes the interval time.
Page 385: Chapter 10 16-Bit Inverter Timer/Counter R
Chapter 10 16-bit Inverter Timer/Counter R Chapter 10 16-bit Inverter Timer/Counter R Interval timer mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Reload Possible Compare value TRnCCR1 to TRnCCR3 Reload Possible Compare value TRnCCR4, TRnCCR5 Reload Possible Compare value...
Page 386: Figure 10-42: Basic Timing In Interval Timer Mode (1/2)
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-42: Basic Timing in Interval Timer Mode (1/2) (a) When D1>D2>D3, only value of TRnCCR0 register is rewritten, TORn0 and TORn1 are not output (TRnOE0, 1 = 0, TRnOL0 = 0, TRnOL1 = 1) FFFFH Counter TRnCE...
Page 387 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-42: Basic Timing in Interval Timer Mode (2/2) (b) When D1 = D2, values of TRnCCR0 and TRnCCR1 registers not rewritten, TORn1 output performed (TRnOE0, 1 = 1, TRnOL0 = 0, TRnOL1 = 1) FFFFH D1 = D2 D1 = D2...
Page 388: External Event Count Mode
Chapter 10 16-bit Inverter Timer/Counter R 10.10.2 External event count mode Outline of external event count mode In the external event count mode, count up starts upon external event input (TEVTRn pin). (The external event input (TEVTRn) is used as the count clock, regardless of bit TRnEEE of the TRnCTL1 register.) In the external event count mode, the counter is cleared only upon a match between the counter and the value of the TRnCCR0 register.
Page 389 Chapter 10 16-bit Inverter Timer/Counter R External event count mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Anytime rewrite Possible Compare value TRnCCR1 to TRnCCR3 Anytime rewrite Possible Compare value TRnCCR4, TRnCCR5 Anytime rewrite Possible Compare value (b) Input pins...
Page 390: Figure 10-43: Basic Operation Timing In External Event Count Mode (1/4)
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-43: Basic Operation Timing in External Event Count Mode (1/4) (a) When D1>D2>D3, only value of TRnCCR0 register is rewritten, TORn0 and TORn1 are not output. The signal input from TEVTRn and internally synchronized is counted as the count clock (TRnOE0, 1 = 0, TRnOL0 = 0, TRnOL1 = 1) FFFFH Counter...
Page 391 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-43: Basic Operation Timing in External Event Count Mode (2/4) (b) When D1 = D2, TRnCCR0 and TRnCCR1 register values are not rewritten, TORn0 and TORn1 are output (TRnOE0, 1 = 1, TRnOL0 = 0, TRnOL1 = 1) FFFFH D1 = D2 D1 = D2...
Page 392 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-43: Basic Operation Timing in External Event Count Mode (3/4) (c) When D1 = D2, TRnCCR0 and TRnCCR1 register values are not rewritten, TORn0 and TORn1 are output (TRnOE0, 1 = 1, TRnOL0 = 0, TRnOL1 = 1) FFFFH Counter 0000H...
Page 393 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-43: Basic Operation Timing in External Event Count Mode (4/4) (d) When D1 = D2, TRnCCR0, TRnCCR1 register values are not rewritten, TORn0 and TORn1 are output (TRnOE0, 1 = 1, TRnOL0 = 0, TRnOL1 = 1) FFFFH Counter 0001H...
Page 394: External Trigger Pulse Output Mode (Tmr1 Only)
Chapter 10 16-bit Inverter Timer/Counter R 10.10.3 External trigger pulse output mode (TMR1 only) Outline of external trigger pulse output mode When, in the external trigger pulse mode, the duty is set to the TR1CCR1 to TR1CCR5 registers, the cycle is set to the TR1CCR0 register, and TR1CE = 1 is set, external trigger input (TTRGR1 pin) wait results, with the counter remaining stopped at FFFFH.
Page 395 Chapter 10 16-bit Inverter Timer/Counter R External trigger pulse output mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TR1CCR0 Reload Possible Cycle TR1CCR1 to TR1CCR3 Reload Possible Duty TR1CCR4, TR1CCR5 Reload Possible Duty (b) Input pins Function TIR1m (m = 0 to 3)
Page 396: Figure 10-44: Basic Operation Flow In External Trigger Pulse Output Mode
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-44: Basic Operation Flow in External Trigger Pulse Output Mode START Initial settings •Clock selection (TR1CTL1. TR1EEE = 0) (TR1CTL0. TR1CKS2 to TR1CKS0) •External trigger pulse output mode External trigger setting (TTRGR1 pin) input (TR1CTL1.
Page 397: Figure 10-45: Basic Operation Timing In External Trigger Pulse Output Mode
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-45: Basic Operation Timing in External Trigger Pulse Output Mode (a) When values of TR1CCR0 and TR1CCR1 registers are rewritten, TOR10 and TOR11 are output (TR1OE0, 1 = 1, TR1OL0, 1 = 0) FFFFH Counter TR1CE...
Page 398: One-Shot Pulse Mode
Chapter 10 16-bit Inverter Timer/Counter R 10.10.4 One-shot pulse mode Outline of one-shot pulse mode When, in the one-shot pulse mode, the duty is set to the TRnCCR0 register, the output duty delay value is set to the TRnCCR1 to TRnCCR5 registers, and bit TRnCE of the TRnCTL0 register is set to 1, external trigger input (TTRGR1 pin of TMR1) wait results, with the counter remaining stopped at FFFFH.
Page 399 Chapter 10 16-bit Inverter Timer/Counter R One-shot pulse mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Anytime rewrite Possible Cycle TRnCCR1 to TRnCCR3 Anytime rewrite Possible Output delay value TRnCCR4, TRnCCR5 Anytime rewrite Possible Output delay value (b) Input pins Function...
Page 400: Figure 10-46: Basic Operation Flow In One-Shot Pulse Mode
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-46: Basic Operation Flow in One-Shot Pulse Mode START Initial settings • Clock selection (TRnCTL1: TRnEEE = 0) (TRnCTL0: TRnCKS2 to TRnCKS0) • One-shot pulse mode setting (TRnCTL1: TRnMD2 to TRnMD0 = 011) •...
Page 401: Figure 10-47: Basic Operation Timing In One-Shot Pulse Mode
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-47: Basic Operation Timing in One-Shot Pulse Mode (a) (TRnOE0, 1 = 1, TRnOL0, 1 = 0) FFFFH Note1 Counter TRnCE TRnEST External trigger Note2 (TTRGR1 pin TRnCCR0 TRnCCR0 0000H buffer TRnCCR1 TRnCCR1 0000H buffer INTTRnCC0...
Page 402: Pwm Mode
Chapter 10 16-bit Inverter Timer/Counter R 10.10.5 PWM mode Outline of PWM mode When, in the PWM mode, the duty is set to the TRnCCR1 to TRnCCR5 registers, the cycle is set to the TRnCCR0 register, and TRnCE = 1 is set, variable duty PWM output is performed from pins TORn1 to TORn5.
Page 403 Chapter 10 16-bit Inverter Timer/Counter R PWM mode operation list (a) Compare register Register Rewrite Method Rewrite during Operation Function TRnCCR0 Reload Possible Cycle TRnCCR1 to TRnCCR3 Reload Possible Duty TRnCCR4, TRnCCR5 Reload Possible Duty (b) Input pins Function TIR1m - (m = 0 to 3) TTRGR1 TEVTR1...
Page 404: Figure 10-48: Basic Operation Mode In Pwm Mode (1/2)
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-48: Basic Operation Mode in PWM Mode (1/2) (a) When values of TRnCCR0 to TRnCCR5 registers are rewritten during timer operation START Initial settings • Clock selection (TRnCTL0: TRnCKS2 to TRnCKS0) • PWM mode setting (TRnCTL1: TRnMD3 to TRnMD0 = 0100) •...
Page 405 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-48: Basic Operation Flow in PWM Mode (2/2) (b) When values of TRnCCR0 to TRnCCR5 registers are rewritten during timer operation START Initial settings • Clock selection (TRnCTl0: TRnCKS2 to TRnCKS0) • PWM mode setting (TRnCTl1: TRnMD3 to TRnMD0 = 0100) Compare register setting •...
Page 406: Figure 10-49: Basic Operation Timing In Pwm Mode (1/2)
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-49: Basic Operation Timing in PWM Mode (1/2) (a) When only value of TRnCCR1 is rewritten, and TORn0 and TORn1 are output (TRnOE0, 1 = 1, TRnOL0, 1 = 0) FFFFH Counter TRnCE TRnCCR0 TRnCCR0 0000H...
Page 407 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-49: Basic Operation Timing in PWM Mode (2/2) (b) When values of TRnCCR0 and TRnCCR1 register are rewritten, TORn0 and TORn1 are output (TRnOE0, 1 = 1, TRnOL0, 1 = 0) FFFFH Counter TRnCE TRnCCR0 Note...
Page 408: Free-Running Mode
Chapter 10 16-bit Inverter Timer/Counter R 10.10.6 Free-running mode Outline of free-running mode The operation timing of the free-running mode is shown below. The operation for bits TRnCCS0 to TRnCCS3 of register TRnOPT0 is specified. Figure 10-50: Basic Operation Flow in Free-Running Mode START Initial settings •...
Page 409 Chapter 10 16-bit Inverter Timer/Counter R Free-running mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Note 1 Note 1 Capture or compare value Anytime rewrite Possible TRnCCR1 to TRnCCR3 Note 1 Note 1 Capture or compare value Anytime rewrite Possible TRnCCR4, TRnCCR5...
Page 410 Chapter 10 16-bit Inverter Timer/Counter R Compare function (TRnCCS1 = 0, TRnCCS0 = 0) When TRnCTL0 register bit TRnCE is set to 1, the counter counts from 0000H to FFFFH. An overflow interrupt (INTTRnOV) is output when the counter value changes from FFFFH to 0000H, and the counter is cleared.
Page 411: Figure 10-51: Basic Operation Timing In Free-Running Mode (Compare Function)
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-51: Basic Operation Timing in Free-Running Mode (Compare Function) When values of TRnCCR0 and TRnCCR1 registers are rewritten, TORn0, TORn1 are output (TRnOE0, 1 = 1, TRnOL0, 1 = 0) FFFFH Counter TRnCE TRnCCR0 TRnCCR0 0000H...
Page 412: Figure 10-52: Basic Operation Timing In Free-Running Mode (Capture Function)
Chapter 10 16-bit Inverter Timer/Counter R Capture function (TRnCCS1 = 1, TRnCCS0 = 1) When TRnCTL0 register bit TRnCE is set to 1, the counter counts from 0000H to FFFFH. An overflow interrupt (INTTRnOV) is output when the value of the counter changes from FFFFH to 0000H, and the counter is cleared.
Page 413: Figure 10-53: Basic Operation Timing In Free-Running Mode (Compare/Capture Function)
Chapter 10 16-bit Inverter Timer/Counter R Compare/capture function (TRnCCS1 = 0, TRnCCS0 = 1) When TRnCTL0 register bit TRnCE is set to 1, the counter counts from 0000H to FFFFH, an overflow interrupt (INTTRnOV) is output when the value of the counter changes from FFFFH to 0000H, and the counter is cleared.
Page 414 Chapter 10 16-bit Inverter Timer/Counter R Overflow flag When, in the free-running mode, the counter overflows from FFFFH to 0000H, the overflow flag (TRnOVF) is set to “1”, and an overflow interrupt (INTTRnOV) is output. The overflow flag is cleared through 0 write from the CPU. (The overflow flag is not cleared by just being read.) User’s Manual U16580EE3V1UD00...
Page 415: Pulse Width Measurement Mode (Tmr1 Only)
Chapter 10 16-bit Inverter Timer/Counter R 10.10.7 Pulse width measurement mode (TMR1 only) Outline of pulse width measurement mode In the pulse width measurement mode, counting is performed in the free-running mode. The counter value is saved to the TR1CCR0 register, and the counter is cleared to 0000H. As a result, the external input pulse width can be measured.
Page 416 Chapter 10 16-bit Inverter Timer/Counter R Pulse width measurement mode operation list (a) Compare register Register Rewrite Method Rewrite during Operation Function TR1CCR0 Capture value TR1CCR1 to TR1CCR3 Capture value TR1CCR4, TR1CCR5 (b) Input pins Function TIR1m Input capture trigger, transfer counter value to TR1CCRm register (m = 0 to 3) TTRGR1 TEVTR1 (c) Output pins...
Page 417: Triangular Wave Pwm Mode
Chapter 10 16-bit Inverter Timer/Counter R 10.10.8 Triangular wave PWM mode Outline of triangular wave PWM mode In the triangular wave PWM mode, similarly to in the PWM mode, when the duty is set to the TRnCCR1 to TRnCCR5 registers, the cycle is set to the TRnCCR0 register, and TRnCE = 1 is set, variable duty and cycle type triangular wave PWM output is performed from pins TORn1 to TORn5.
Page 418 Chapter 10 16-bit Inverter Timer/Counter R Triangular wave PWM mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Reload Possible 1/2 of cycle TRnCCR1 to TRnCCR3 Reload Possible 1/2 of duty TRnCCR4, TRnCCR5 Reload Possible 1/2 of duty (b) Input pins Function...
Page 419: Figure 10-55: Basic Operation Timing In Triangular Wave Pwm Mode
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-55: Basic Operation Timing in Triangular Wave PWM Mode When TORn0, TORn1 are output (TRnOE0, 1 = 1, TRnOL0, 1 = 0) FFFFH FFFFH Counter TRnCE TRnCCR0 0000H 0000H TRnCCR1 INTTRnCC0 INTTRnCC1 INTTRnOV TORn0 TORn1 Remark:...
Page 420: High-Accuracy T-Pwm Mode
Chapter 10 16-bit Inverter Timer/Counter R 10.10.9 High-accuracy T-PWM mode Outline of high-accuracy T-PWM mode The high-accuracy T-PWM mode generates 6-phase PWM using four 16-bit counters (up/down, ±2 counts, 15 real bits) and 16-bit compare registers (LSB = additional pulse control). The carrier wave cycle calculated with “TRnCCR0-TRnDTC0-TRnDTC1”...
Page 421 Chapter 10 16-bit Inverter Timer/Counter R High-accuracy T-PWM mode operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Reload, Possible Cycle Anytime rewrite TRnCCR1 to TRnCCR3 Reload, Possible PWM duty Anytime rewrite TRnCCR4, TRnCCR5 Reload, Possible PWM duty (selectable as Anytime rewrite A/D conversion trigger)
Page 422 Chapter 10 16-bit Inverter Timer/Counter R High-accuracy T-PWM mode settings (a) Mode settings The high-accuracy T-PWM mode is selected by setting TRnCTL1 register bits TRnMD4 to 0 = 1000B. (b) Output level/output enable settings Set bits TRnOL0-TRnOL7 and TRnOE0-TRnOE7 of the TRnIOC0, TRnIOC3 registers, to enable output level/output enable.
Page 423 Chapter 10 16-bit Inverter Timer/Counter R (g) A/D conversion trigger output settings To set A/D conversion trigger 0 (TRnADTRG0 signal), set TRnOPT2 register bits TRnAT05 to TRnAT00. With bits TRnAT05 to TRnAT00, peak interrupt (INTTRnCD) and valley interrupt (INTTRnOD) ena- ble/disable is performed at the TRnCCR5 register match timing (counter up count/down count), and the TRnCCR4 register match timing (counter up count/down count).
Page 424: Figure 10-57: Counter Operation In High-Accuracy T-Pwm Mode
Chapter 10 16-bit Inverter Timer/Counter R Counter operation in high-accuracy T-PWM mode At initial value FFFEH, the TRnDTC0 value is loaded to the counter immediately after TRnCE = 1 is set, and the counter counts up in +2 steps. Then, upon a match with TRnCCR0 to TRnDTC1, the counter counts down in -2 steps.
Page 425: Figure 10-59: Timer Output Example When Trnce = 1 Is Set (Initial) (High-Accuracy T-Pwm Mode)
Chapter 10 16-bit Inverter Timer/Counter R Basic operation in high-accuracy T-PWM mode The Figure 10-59 shows the timing chart when TRnCCR0 = 0010H, TRnDTC0 = 0002H, TRnDTC1 = 0004H, and the TRnCCR1 register is set from 0000H to 0010H (one part only shown).
Page 426: Figure 10-60: Timer Output Example During Operation (High-Accuracy T-Pwm Mode)
Chapter 10 16-bit Inverter Timer/Counter R The Figure 10-60 shows the timing chart when TRnCCR0 = 0010H, TRnDTC0 = 0002H, TRnDTC1 = 0004H, and the TRnCCR1 register is set from 0000H to 0010H (one part only shown). In this example, TRnOL6 to TRnOL1 = 000000B is set. As can be seen in this figure, a normal phase (pin TORn1) that is active (high level) is output when 0000H ≤...
Page 427: Figure 10-61: Torn1 Pin Output Example When Performing Additional Pulse Control
Chapter 10 16-bit Inverter Timer/Counter R Additional pulse control in high-accuracy T-PWM mode In the high-accuracy T-PWM mode, additional pulse can be set by setting the LSB of the duty setting registers (TRnCCR1 to TRnCCR3) to “1”. With the additional pulse control function, finer duty control can be performed (higher accuracy).
Page 428: Figure 10-62: Torn1 Pin Output Example When Additional Pulse Control Is Not Performed
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-62: TORn1 Pin Output Example When Additional Pulse Control Is Not Performed Count clock TRnCCR1 = 0 TRnCCR1 = 2 TRnCCR1 = 4 TRnCCR1 = 6 TRnCCR1 = 8 TRnCCR1 = 10 TRnCCR1 = 12 Remarks: 1.
Page 429: Figure 10-63: Timings Of Timer Output In High-Accuracy T-Pwm Mode (1/3)
Chapter 10 16-bit Inverter Timer/Counter R Caution on timer output in high-accuracy T-PWM mode There are cautions for TRnCCR1 to TRnCCR3 as follows when varying 6-phase PWM duty by using reload (batch rewrite). (a) In case of TRnCCR0 + 2 ≤ TRnCCRm (Setting prohibited) Figure 10-63a shows the case when the value of “TRnCCR0 + 2 or more”...
Page 430 Chapter 10 16-bit Inverter Timer/Counter R (b) In case of rewriting from TRnCCRm = 0000H to TRnCCRm = TRnCCR0 Figure 10-63b shows the output waveform where the TRnCCR1 register setting is changed from 100% output to 0% output. The TORn1 pin output is inverted upon a match between the TRnCCR1 register and 16-bit sub-counter, and the TORn2 pin output is inverted after the dead time count.
Page 431 Chapter 10 16-bit Inverter Timer/Counter R (d) In case of rewriting from “TRnDTC0 + TRnDTC1 < TRnCCRm < TRnCCR0 − TRnDTC0 − TRnDTC1” to “TRnCCR0 − TRnDTC1 + 1 < TRnCCRm < TRnCCR0” Figure 10-63d shows the output waveform when rewriting the TRnCCR1 register from x (TRnDTC0 + TRnDTC1 <...
Page 432: Table 10-1: Positive Phase Operation Condition List
Chapter 10 16-bit Inverter Timer/Counter R Timer output change after compare register updating Timer output is affected when the compare register value is updated during reload execution. The timer output level is changed at any timing listed in Tables 10-1 and 10-2. Table 10-1: Positive Phase Operation Condition List Operation Symbol...
Page 433: Figure 10-64: Timer Output Change After Compare Register Updating Timings (1/3)
Chapter 10 16-bit Inverter Timer/Counter R Table 10-3: Compare Register Value After Trough Reload (TRnDTC0 < TRnDTC1) Compare Register Compare Register Value After Trough Reload (TRnDTC0 < TRnDTC1) Figure No. Value Immediately Before Trough Reload 0000H 0000H < TRnCCR1 to TRnCCR3 < TRnDTC0 Figureaa TRnCCR1 to TRnCCR3 = 0000H, TRnDTC0 + 1 Figureab...
Page 434 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-64: Timer Output Change after Compare Register Updating Timings (2/3) → × (c) TRnCCR1 to TRnCCR3 = 0000H TRnDTC0 < TRnCCR1 to TRnCCR3 < TRnDTC0 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3,...
Page 435 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-64: Timer Output Change after Compare Register Updating Timings (3/3) → − − (e) TRnCCR1 to TRnCCR3 = 0000H TRnCCR0 TRnDTC1 TRnDTC0 < TRnCCR1 to − TRnCCR3 < TRnCCR0 TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter...
Page 436: Figure 10-65: Compare Register Value After Trough Reload Timing (1/3)
Chapter 10 16-bit Inverter Timer/Counter R Table 10-4: Compare Register Value After Trough Reload Compare Register Compare Register Value After Trough Reload Figure No. Value Immediately Before Trough Reload TRnCCR0 TRnCCR1 to TRnCCR3 = 0000H Figure 10-65a 0000H < TRnCCR1 to TRnCCR3 < TRnDTC0 Figure 10-65b TRnCCR1 to TRnCCR3 = TRnDTC0, TRnDTC0 + 1 Figure 10-65c...
Page 437 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-65: Compare Register Value After Trough Reload Timing (2/3) → (c) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnCCR1 to TRnCCR3 = TRnDTC0, TRnDTC0 + 1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5...
Page 438: Table 10-5: Compare Register Value After Trough Reload (Trndtc1 < Trndtc0)
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-65: Compare Register Value After Trough Reload Timing (3/3) → − − (f) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnCCR0 TRnDTC1 TRnDTC0 < TRnCCR1 to − TRnCCR3 < TRnCCR0 TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H...
Page 439: Figure 10-66: Compare Register Value After Trough Reload (Trndtc1 < Trndtc0) (1/3)
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-66: Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) (1/3) → − (a) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnCCR0 TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3...
Page 440 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-66: Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) (2/3) → − < (c) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnCCR0 TRnDTC1 x 2 < TRnCCR1 to TRnCCR3 − TRnCCR0 TRnDTC1 When the values of TRnCCR1 to TRnCCR3 are changed from “TRnCCR0 − TRnDTC1 < TRnCCR1 to TRnCCR3 ≤...
Page 441 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-66: Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) (3/3) → ≤ (e) TRnCCR1 to TRnCCR3 = TRnCCR0 TRnDTC0 + 1 < TRnCCR1 to TRnCCR3 TRnDTC0 + TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H...
Page 442: Figure 10-67: Compare Register Value After Trough Reload (1/3)
Chapter 10 16-bit Inverter Timer/Counter R Table 10-6: Compare Register Value After Trough Reload Compare Register Compare Register Value After Trough Reload Figure No. Value Immediately Before Peak Reload 0000H TRnCCR1 to TRnCCR3 = TRnCCR0 Figure 10-67a TRnCCR0 − TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0 Figure 10-67b TRnCCR1 to TRnCCR3 = TRnCCR0 −...
Page 443 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-67: Compare Register Value After Trough Reload (2/3) → − (c) TRnCCR1 to TRnCCR3 = 0000H TRnCCR1 to TRnCCR3 = TRnCCR0 TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3, TORn5 TORn2, TORn4,...
Page 444 Chapter 10 16-bit Inverter Timer/Counter R Figure 10-67: Compare Register Value After Trough Reload (3/3) → (f) TRnCCR1 to TRnCCR3 = 0000H TRnDTC0 + 1 < TRnCCR1 to TRnCCR3 < TRnDTC0 + TRnDTC1 TRnCCR1 to TRnCCR3 16-bit sub-counter TRnCCR0 16-bit sub-counter 0000H TRnDTT1 to TRnDTT3 TORn1, TORn3,...
Page 445: Figure 10-68: Output Waveform Example When Dead Time Is Set
Chapter 10 16-bit Inverter Timer/Counter R Dead time control in high-accuracy T-PWM mode In the high-accuracy T-PWM mode, the TRnCCR1 to TRnCCR3 registers are used for duty setting and the TRnCCR0 register is used for cycle setting. By using these four registers, duty variable type 6-phase PWM waveform can be output.
Page 446: Figure 10-69: Dead Time Control In High-Accuracy T-Pwm Mode
Chapter 10 16-bit Inverter Timer/Counter R (10) Cautions on dead time control in high-accuracy T-PWM mode (a) Rewriting of TRnDTC0 and TRnDTC1 registers The setting of the dead time in the TRnDTC0, TRnDTC1 registers can be rewritten during opera- tion. Note the following cautions when rewriting the dead time setting during operation. Cautions: 1.
Page 447: Figure 10-70: Operation Example Setting Is Out Of Range
Chapter 10 16-bit Inverter Timer/Counter R (11) Caution on rewriting cycles in high-accuracy T-PWM mode In high-accuracy T-PWM mode, setting conditions for the TRnCCR0, TRnDTC0, and TRnDTC1 registers are as follows. • 3 × MAX (TRnDTC0, TRnDTC1) + MIN (TRnDTC0, TRnDTC1) < TRnCCR0 0002H <...
Page 448: Figure 10-71: Error Interrupt Operation Example
Chapter 10 16-bit Inverter Timer/Counter R (12) Error interrupt (INTTRnER) in high-accuracy T-PWM mode The positive/negative simultaneous active detection function can be used in the high-accuracy T-PWM mode. Error interrupts (INTTRnER) do not occur in the high-accuracy T-PWM mode. In case of occurrence, the internal circuits may be damaged.
Page 449: Pwm Mode With Dead Time
Chapter 10 16-bit Inverter Timer/Counter R 10.10.10 PWM mode with dead time Outline of PWM mode with dead time In the PWM mode with dead time, 6-phase PWM is generated using the 16-bit counter’s saw tooth wave operation and four 16-bit counters. The counter’s maximum value is set with the TRnCCR0 register.
Page 450 Chapter 10 16-bit Inverter Timer/Counter R PWM mode with dead time operation list (a) Compare registers Register Rewrite Method Rewrite during Operation Function TRnCCR0 Reload Possible Cycle TRnCCR1 to TRnCCR3 Reload Possible PWM duty TRnCCR4, TRnCCR5 Reload Possible PWM duty (b) Input pins Function TIR1m...
Page 451: Figure 10-73: Output Waveform Example In Pwm Mode With Dead Time
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-73: Output Waveform Example in PWM Mode with Dead Time FFFFH Counter m (for cycle setting) TRnCCR0 i (U phase duty) TRnCCR1 TRnCCR2 j (V phase duty) k (W phase duty) TRnCCR3 TRnDTC0 TRnDTC1 TRnDTT1 TRnDTT2...
Page 452 Chapter 10 16-bit Inverter Timer/Counter R PWM mode with dead time settings (a) Mode setting The PWM mode with dead time is set by setting TRnCTL1 register bits TRnMD4 to TRnMD0 = 1001. (b) Output level/output enable settings Output level/output enable is set by setting the TRnOL0 to TRnOL7 and TRnOE0 to TRnOE7 bits of the TRnIOC0 and TRnIOC3 registers.
Page 453 Chapter 10 16-bit Inverter Timer/Counter R (g) Dead time settings The dead time settings are performed with the TRnDTC0 and TRnDTC1 registers. The dead time can be obtained with count clock cycle × TRnDTC0,TRnDTC1. The time until TORn2, TORn4, TORn6 pin inactive change → TORn1, TORn3, TORn5 pin active change can be set with the TRnDTC0 register.
Page 454: Figure 10-74: Timer Output Example When Trnce = 1 Is Set (Initial) (Pwm Mode With Dead Time)
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-74: Timer Output Example When TRnCE = 1 Is Set (Initial) (PWM mode with Dead Time) Counter 0000 000100020003000400050006 00070000000100020003 0004 FFFF 000800090002 00030004 000500060007000800090002 00030004 Sub-counter FFFF TRnCE 0007H (for cycle setting) TRnCCR0 TRnDTC0 002H (for dead time setting)
Page 455: Figure 10-75: Output Waveform Example In Pwm Mode With Dead Time
Chapter 10 16-bit Inverter Timer/Counter R Figure 10-75: Output Waveform Example in PWM Mode with Dead Time TRnCCR0 Counter TRnDTC0 = “x” TRnDTC1 = “y” TRnDTT1, 2, 3 TORn1, 3, 5 TORn2, 4, 6 User’s Manual U16580EE3V1UD00...
Page 456: Figure 10-76: Error Interrupt (Inttrner) In Pwm Mode With Dead Time
Chapter 10 16-bit Inverter Timer/Counter R Error interrupt (INTTRnER) in PWM mode with dead time In the PWM mode with dead time, the normal phase/inverted phase simultaneous active detection function can be used. When using the PWM mode with dead time, no error interrupt (INTTRnER) is output as long as no hardware fault occurs (except when TRnDTC0, TRnDTC1 = 0000H is set).
Page 457: Chapter 11 16-Bit Timer/Event Counter T
Chapter 11 16-bit Timer/Event Counter T 11.1 Features Timer T (TMT) is a 16-bit timer/event counter that provides general-purpose functions. Timer T can perform the following operations. • Interval timer function • External event count function • One-shot pulse output function •...
Page 458: Configuration
Chapter 11 16-bit Timer/Event Counter T 11.3 Configuration Timer T is configured of the following hardware. Table 11-1: Timer T Configuration Item Configuration Counter 16-bit counter Registers TMTn capture/compare registers 0, 1 (TTnCCR0, TTnCCR1) TMTn counter read buffer register (TTnCNT) TMTn counter write buffer register (TTnTCW) TTnCCR0 buffer register, TTnCCR1 buffer register Timer input pins...
Page 459: Table 11-2: List Of Timer T Registers
Chapter 11 16-bit Timer/Event Counter T Table 11-2: List of Timer T Registers Address Register Name Symbol Manipulable Bit Units After Reset × × FFFFF690H TMT0 control register 0 TT0CTL0 × × FFFFF691H TMT0 control register 1 TT0CTL1 × × FFFFF692H TMT0 control register 2 TT0CTL2...
Page 460: Figure 11-1: Block Diagram Of Timer T
Chapter 11 16-bit Timer/Event Counter T Figure 11-1: Block Diagram of Timer T Internal bus TTnCCR0 TTnCCR1 LOAD LOAD TOTn0 Control TOTn1 TTnCCR0 buffer TTnCCR1 buffer TTnEQC1/ INTTTnCC1 TTnEQC0/ φ INTTTnCC0 φ φ Clock φ LOAD generator φ INTTTnOV Counter Counter Clear φ...
Page 461: Figure 11-2: Tmtn Capture/Compare Register 0 (Ttnccr0)
Chapter 11 16-bit Timer/Event Counter T TMTn capture/compare register 0 (TTnCCR0) The TTnCCR0 register is a 16-bit register that functions both as a capture register and as a compare register. This register can be read and written in 16-bit units only. Reset input clears this register to 0000H.
Page 462: Figure 11-3: Tmtn Capture/Compare Register 1 (Ttnccr1)
Chapter 11 16-bit Timer/Event Counter T • Use as compare register When TTnCE = 1, the TTnCCR0 register rewrite method differs according to the operation mode. Refer to Table 11-3: Capture/Compare Functions in Each Mode. (For details about the compare register rewrite operation, refer to 11.5.2 Method for writing to compare register.) •...
Page 463: Table 11-4: Capture/Compare Functions In Each Mode
Chapter 11 16-bit Timer/Event Counter T The capture/compare functions in each operation mode are as follows. Table 11-4: Capture/Compare Functions in Each Mode Operation Mode Capture/Compare Setting of Rewriting Method Counter Clear Function TTnCCR1 Register during Compare Interval mode Compare only Anytime write External event count mode Compare only...
Page 464: Figure 11-4: Tmtn Counter Write Buffer Register (Ttntcw)
Chapter 11 16-bit Timer/Event Counter T TMTn counter write buffer register (TTnTCW) The TTnTCW register is a write buffer register that can write the counter value. The setting value is valid only in the encoder compare mode, encoder capture mode. In all other modes, the setting value is invalid.
Page 465: Control Registers
Chapter 11 16-bit Timer/Event Counter T 11.4 Control Registers TMTn control register 0 (TTnCTL0) TTnCTL0 is an 8-bit register that controls the operation of TMTn. This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. Reset input clears this register to 00H. When TTnCE = 1, only the TTnCE bit of the TTnCTL0 register can be changed.
Page 466: Table 11-5: Tmtn Count Clock And Count Delay
Chapter 11 16-bit Timer/Event Counter T Figure 11-6: TMTn Control Register 0 (TTnCTL0) (2/2) TTnCKS2 TTnCKS1 TTnCKS0 Internal Count Clock Selection /256 /1024 Table 11-5: TMTn Count Clock and Count Delay Count Delay Count Clocks TTnCKS2 TTnCKS1 TTnCKS0 Minimum Maximum 3 base clocks 4 base clocks 4 base clocks...
Page 467: Figure 11-7: Tmtn Control Register 1 (Ttnctl1) (1/2)
Chapter 11 16-bit Timer/Event Counter T TMTn control register 1 (TTnCTL1) The TTnCTL1 register is an 8-bit register that controls the operation of TMTn. This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. Set the TTnCTL1 register when TTnCE = 0.
Page 468 Chapter 11 16-bit Timer/Event Counter T Figure 11-7: TMTn Control Register 1 (TTnCTL1) (2/2) TTnMD3 TTnMD2 TTnMD1 TTnMD0 Timer Mode Interval mode External event count mode External trigger pulse output mode One-shot pulse mode PWM mode Free-running mode Pulse width measurement mode Triangular wave PWM mode Encoder compare mode Offset trigger generation mode...
Page 469: Figure 11-8: Tmtn Control Register 2 (Ttnctl2) (1/2)
Chapter 11 16-bit Timer/Event Counter T TMTn control register 2 (TTnCTL2) The TTnCTL2 register is an 8-bit register that controls the operation of TMTn. This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. The settings of the TTnCTL2 register are valid only in the encoder compare mode.
Page 470 Chapter 11 16-bit Timer/Event Counter T Figure 11-8: TMTn Control Register 2 (TTnCTL2) (2/2) TTnECM0 Encoder Clear Mode on Match of Counter and TTnCCR0 Register No clear condition When the counter and TTnCCR0 register match, clear the counter if the next count is a down count (TTnESF = 0) Remark: The setting of bit TTnECM0 is valid in the encoder compare mode.
Page 471: Figure 11-9: Tmtn I/O Control Register 0 (Ttnioc0)
Chapter 11 16-bit Timer/Event Counter T TMTn I/O control register 0 (TTnIOC0) The TTnIOC0 register is an 8-bit register that controls timer output (TOTn0 and TOTn1 pins). This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. Set the TTnIOC0 register when TTnCE = 0.
Page 472: Figure 11-10: Tmtn I/O Control Register 1 (Ttnioc1)
Chapter 11 16-bit Timer/Event Counter T TMTn I/O control register 1 (TTnIOC1) The TTnIOC1 register is an 8-bit register that controls the valid edge of capture input (TITn1 and TITn0 pins). This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 473: Figure 11-11: Tmtn I/O Control Register 2 (Ttnioc2)
Chapter 11 16-bit Timer/Event Counter T TMTn I/O control register 2 (TTnIOC2) The TTnIOC2 register is an 8-bit register that controls the valid edge of external event count input (TEVTTn pin) and external trigger input (TTRGTn pin). This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 474: Figure 11-12: Tmtn I/O Control Register 3 (Ttnioc3) (1/2)
Chapter 11 16-bit Timer/Event Counter T TMTn I/O control register 3 (TTnIOC3) The TTnIOC3 register is an 8-bit register that controls the valid edge of encoder clear input (TECRTn pin) and encoder input (TENCTn1 and TENCTn0 pins). This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 475 Chapter 11 16-bit Timer/Event Counter T Figure 11-12: TMTn I/O Control Register 3 (TTnIOC3) (2/2) TTnECS1 TTnECS0 Set the valid edge of encoder clear input (TECRTn pin) No edge detection Rising edge detection Falling edge detection Both rising and falling edge detection The encoder clear interrupt (INTTTnEC) is output upon detection of the valid edge set with bits TTnECS1, TTnECS0.
Page 476: Figure 11-13: Tmtn Option Register 0 (Ttnopt0)
Chapter 11 16-bit Timer/Event Counter T TMTn option register 0 (TTnOPT0) The TTnOPT0 register is an 8-bit register that sets the capture/compare operation and detects overflow. This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. Set the bits of the TTnOPT0 register other than TTnOVF when TTnCE = 0.
Page 477: Figure 11-14: Tmtn Option Register 1 (Ttnopt1) (1/2)
Chapter 11 16-bit Timer/Event Counter T TMTn option register 1 (TTnOPT1) The TTnOPT1 register is an 8-bit register that detects encoder-dedicated underflow, overflow, and counter up/down operation. This register can be read and written in 8-bit or 1-bit units. Reset input clears this register to 00H. The setting of the TTnOPT1 register is valid only in the encoder compare mode.
Page 478 Chapter 11 16-bit Timer/Event Counter T Figure 11-14: TMTn Option Register 1 (TTnOPT1) (2/2) TTnEOF Indication of Encoder Overflow No overflow indicated Indicates counter overflow in the encoder compare mode If the counter value is counted up from FFFFH, overflow occurs, the OVF flag is set (1), and the counter is cleared to 0000H.
Page 479: Figure 11-15: Tmtn Option Register 2 (Ttnopt2)
Chapter 11 16-bit Timer/Event Counter T (10) TMTn option register 2 (TTnOPT2) The TTnOPT2 register is an 8-bit register that indicates the reload request status when performing write access to compare registers using the reload method. This register can only be read in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 480: Basic Operation
Chapter 11 16-bit Timer/Event Counter T 11.5 Basic Operation 11.5.1 Basic counter operation This section describes the basic operation of the counter. For details, refer to chapter 11.6 Operation in Each Mode. Counter start operation (a) Encoder compare mode The count operation is controlled by the phases of pins TENCTn0 and TENCTn1. When TTnCE = 0 and TTnECC = 0, the counter is initialized by the TTnTCW register and the count operation is started.
Page 481: Table 11-6: Counter Clear Operation
Chapter 11 16-bit Timer/Event Counter T Table 11-6: Counter Clear Operation Operation Mode Clear Cause TTnCCR0 TTnCCR1 Other Interval mode Compare match External event count mode Compare match External trigger pulse output mode Compare match External trigger (TTRGTn pin) One-shot pulse mode Compare match PWM mode Compare match...
Page 482 Chapter 11 16-bit Timer/Event Counter T Overflow operation Counter overflow occurs in the free-running mode, pulse width measurement mode, encoder compare mode and offset trigger generation mode. Overflow occurs when the counter value changes from FFFFH to 0000H. In the free-running mode, pulse width measurement mode, offset trigger generation mode, the overflow flag (TTnOVF) is set to 1 and an overflow interrupt (INTTTnOV) is output.
Page 483: Method For Writing To Compare Register
Chapter 11 16-bit Timer/Event Counter T 11.5.2 Method for writing to compare register The TTnCCR0 and TTnCCR1 registers can be rewritten during timer operation (TTnCE = 1). There are two write modes (anytime write, reload), depending on the mode. Anytime rewrite method When the TTnCCR0 and TTnCCR1 registers are written during timer operation, the write value is immediately transferred to the TTnCCR0 buffer register and TTnCCR1 buffer register and is used as the value to be compared with the counter.
Page 484: Figure 11-17: Basic Anytime Rewrite Operation Timing
Chapter 11 16-bit Timer/Event Counter T Figure 11-17: Basic Anytime Rewrite Operation Timing Counter TTnCE TTnCCR0 TTnCCR0 0000H buffer TTnCCR1 TTnCCR1 0000H buffer INTTTnCC0 INTTTnCC1 Remarks: 1. D : Setting values of TTnCCR0 register (0000H to FFFFH) : Setting values of TTnCCR1 register (0000H to FFFFH) 2.
Page 485: Figure 11-18: Basic Operation Flow For Reload (Batch Rewrite)
Chapter 11 16-bit Timer/Event Counter T Reload method (Batch rewrite) When TTnCCR0, TTnCCR1 register write is performed during timer operation, the written value is used as the comparison value for the counter via the TTnCCR0 and TTnCCR1 buffer registers. Under the reload method, rewrite the TTnCCR0 register before the TTnCCR0 register value is matched, and next, write to the TTnCCR1 register.
Page 486: Figure 11-19: Basic Reload Operation Timing
Chapter 11 16-bit Timer/Event Counter T Figure 11-19: Basic Reload Operation Timing Counter TTnCE TTnCCR0 TTnCCR0 0000H buffer Note value Write same TTnCCR1 TTnCCR1 0000H Note buffer INTTTnCC0 INTTTnCC1 Note: Since the TTnCCR1 register is not written to, reloading is not performed even if TTnCCR0 is rewritten.
Page 487: Operation In Each Mode
Chapter 11 16-bit Timer/Event Counter T 11.6 Operation in Each Mode 11.6.1 Interval timer mode In the interval timer mode, a compare match interrupt (INTTTnCC0) occurs and the counter is cleared upon a match between the setting value of the TTnCCR0 register and the counter value. The occurrence interval for this counter and TTnCCR0 register match interrupt becomes the interval time.
Page 488: Figure 11-21: Basic Timing In Interval Timer Mode (1/2)
Chapter 11 16-bit Timer/Event Counter T Figure 11-21: Basic Timing in Interval Timer Mode (1/2) (a) When D1>D2>D3, only value of TTnCCR0 register is rewritten, TOTn0 and TOTn1 are not output (TTnOE0, 1 = 0, TTnOL0 = 0, TTnOL1 = 1) FFFFH Counter TTnCE...
Page 489 Chapter 11 16-bit Timer/Event Counter T Figure 11-21: Basic Timing in Interval Timer Mode (2/2) (b) When D1 = D2, values of TTnCCR0 and TTnCCR1 registers not rewritten, TOTn1 output performed (TTnOE0, 1 = 1, TTnOL0 = 0, TTnOL1 = 1) FFFFH D1 = D2 D1 = D2...
Page 490: External Event Count Mode
Chapter 11 16-bit Timer/Event Counter T 11.6.2 External event count mode In the external event count mode, count up starts upon external event input (TEVTTn pin). (The external event input (TEVTTn) is used as the count clock, regardless of bit TTnEEE of the TTnCTL1 register.) In the external event count mode, the counter is cleared only upon a match between the counter and the value of the TTnCCR0 register.
Page 491: Figure 11-22: Basic Operation Timing In External Event Count Mode (1/4)
Chapter 11 16-bit Timer/Event Counter T Figure 11-22: Basic Operation Timing in External Event Count Mode (1/4) (a) When D1>D2>D3, only value of TTnCCR0 register is rewritten, TOTn0 and TOTn1 are not output. The signal input from TEVTTn and internally synchronized is counted as the count clock (TTnOE1 = 0, TTnOL0 = 0, TTnOL1 = 1) FFFFH Counter...
Page 492 Chapter 11 16-bit Timer/Event Counter T Figure 11-22: Operation Timing in External Event Count Mode (2/4) (b) When D1 = D2, TTnCCR0 and TTnCCR1 register values are not rewritten, TOTn0 and TOTn1 are output (TTnOE1 = 1, TTnOL0 = 0, TTnOL1 = 1) F F F F H D 1 = D 2 D 1 = D 2...
Page 493 Chapter 11 16-bit Timer/Event Counter T Figure 11-22: Operation Timing in External Event Count Mode (3/4) (c) When D1 = D2, TTnCCR0 and TTnCCR1 register values are not rewritten, TOTn0 and TOTn1 are output (TTnOE1 = 1, TTnOL0 = 0, TTnOL1 = 1) F F F F H C o u n te r 0 0 0 0 H...
Page 494 Chapter 11 16-bit Timer/Event Counter T Figure 11-22: Basic Operation Timing in External Event Count Mode (4/4) (d) When D1 = D2, TTnCCR0, TTnCCR1 register values are not rewritten, TOTn0 and TOTn1 are output (TTnOE1 = 1, TTnOL0 = 0, TTnOL1 = 1) F F F F H C o u n te r 0 0 0 1 H...
Page 495: External Trigger Pulse Output Mode
Chapter 11 16-bit Timer/Event Counter T 11.6.3 External trigger pulse output mode When, in the external trigger pulse mode, the duty is set to the TTnCCR1 register, the cycle is set to the TTnCCR0 register, and TTnCE = 1 is set, external trigger input (TTRGTn pin) wait results, with the counter remaining stopped at FFFFH.
Page 496: Figure 11-23: Basic Operation Flow In External Trigger Pulse Output Mode
Chapter 11 16-bit Timer/Event Counter T Figure 11-23: Basic Operation Flow in External Trigger Pulse Output Mode START Initial settings • Clock selection (TTnCTL1: TTnEEE = 0) (TTnCTL0: TTnCKS2 to TTnCKS0) • External trigger pulse output mode External trigger setting (TTRGTn pin) input (TTnCTL1: TTnMD3 to TTnMD0 = 0010) •...
Page 497: Figure 11-24: Basic Operation Timing In External Trigger Pulse Output Mode
Chapter 11 16-bit Timer/Event Counter T Figure 11-24: Basic Operation Timing in External Trigger Pulse Output Mode (a) When values of TTnCCR0 and TTnCCR1 registers are rewritten, TOTn0 and TOTn1 are output (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH Counter TTnCE...
Page 498: One-Shot Pulse Mode
Chapter 11 16-bit Timer/Event Counter T 11.6.4 One-shot pulse mode When, in the one-shot pulse mode, the duty is set to the TTnCCR0 register, the output duty delay value is set to the TTnCCR1 register, and bit TTnCE of the TTnCTL0 register is set to 1, external trigger input (TTRGTn pin) wait results, with the counter remaining stopped at FFFFH.
Page 499: Figure 11-25: Basic Operation Flow In One-Shot Pulse Mode
Chapter 11 16-bit Timer/Event Counter T Figure 11-25: Basic Operation Flow in One-Shot Pulse Mode START Initial settings • Clock selection (TTnCTL1: TTnEEE = 0) (TTnCTL0: TTnCKS2 to TTnCKS0) • One-shot pulse mode setting (TTnCTL1: TTnMD2 to TTnMD0 = 011) •...
Page 500: Figure 11-26: Basic Operation Timing In One-Shot Pulse Mode
Chapter 11 16-bit Timer/Event Counter T Figure 11-26: Basic Operation Timing in One-Shot Pulse Mode (a) (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH Note Counter TTnCE TTnEST External trigger (TTRGTn pin) TTnCCR0 TTnCCR0 0000H buffer TTnCCR1 TTnCCR1 0000H buffer INTTTnCC0 INTTTnCC1...
Page 501: Pwm Mode
Chapter 11 16-bit Timer/Event Counter T 11.6.5 PWM mode When, in the PWM mode, the duty is set to the TTnCCR1 register, the cycle is set to the TTnCCR0 register, and TTnCE = 1 is set, variable duty PWM output is performed from pin TOTn1. Simultaneously with the start of count up operation, pin TOTn1 becomes high level, and upon a match between the counter and the TTnCCR1 register, becomes low level.
Page 502 Chapter 11 16-bit Timer/Event Counter T Figure 11-27: Basic Operation Flow in PWM Mode (2/2) (b) When values of TTnCCR0 and TTnCCR1 registers are rewritten during timer operation START Initial settings • Clock selection (TTnCTl0: TTnCKS2 to TTnCKS0) • PWM mode setting (TTnCTl1: TTnMD3 to TTnMD0 = 0100) •...
Page 503: Figure 11-28: Basic Operation Timing In Pwm Mode (1/2)
Chapter 11 16-bit Timer/Event Counter T Figure 11-28: Basic Operation Timing in PWM Mode (1/2) (a) When only value of TTnCCR1 is rewritten, and TOTn0 and TOTn1 are output (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH Counter TTnCE TTnCCR0 TTnCCR0 0000H...
Page 504 Chapter 11 16-bit Timer/Event Counter T Figure 11-28: Basic Operation Timing in PWM Mode (2/2) (b) When values of TTnCCR0 and TTnCCR1 register are rewritten, TOTn0 and TOTn1 are output (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH Counter TTnCE TTnCCR0 Note...
Page 505: Free-Running Mode
Chapter 11 16-bit Timer/Event Counter T 11.6.6 Free-running mode The operation timing of the free-running mode is shown below. The operation for bits TTnCCS1 and TTnCCS0 of register TTnOPT0 is specified. Figure 11-29: Basic Operation Flow in Free-Running Mode START Initial settings •...
Page 506 Chapter 11 16-bit Timer/Event Counter T Compare function (TTnCCS1 = 0, TTnCCS0 = 0) When TTnCTL0 register bit TTnCE is set to 1, the counter counts from 0000H to FFFFH. An overflow interrupt (INTTTnOV) is output when the counter value changes from FFFFH to 0000H, and the counter is cleared.
Page 507: Figure 11-30: Basic Operation Timing In Free-Running Mode (Compare Function)
Chapter 11 16-bit Timer/Event Counter T Figure 11-30: Basic Operation Timing in Free-Running Mode (Compare Function) (a) When values of TTnCCR0 and TTnCCR1 registers are rewritten, TOTn0, TOTn1 are output (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH Counter TTnCE TTnCCR0 TTnCCR0...
Page 508: Figure 11-31: Basic Operation Timing In Free-Running Mode (Capture Function)
Chapter 11 16-bit Timer/Event Counter T Capture function (TTnCCS1 = 1, TTnCCS0 = 1) When TTnCTL0 register bit TTnCE is set to 1, the counter counts from 0000H to FFFFH. An overflow interrupt (INTTTnOV) is output when the value of the counter changes from FFFFH to 0000H, and the counter is cleared.
Page 509: Figure 11-32: Basic Operation Timing In Free-Running Mode (Compare/Capture Function)
Chapter 11 16-bit Timer/Event Counter T Compare/capture function (TTnCCS1 = 0, TTnCCS0 = 1) When TTnCTL0 register bit TTnCE is set to 1, the counter counts from 0000H to FFFFH, an overflow interrupt (INTTTnOV) is output when the value of the counter changes from FFFFH to 0000H, and the counter is cleared.
Page 510 Chapter 11 16-bit Timer/Event Counter T Overflow flag When, in the free-running mode, the counter overflows from FFFFH to 0000H, the overflow flag (TTnOVF) is set to "1", and an overflow interrupt (INTTTnOV) is output. The overflow flag is cleared through 0 write from the CPU. (The overflow flag is not cleared by just being read.) User’s Manual U16580EE3V1UD00...
Page 511: Pulse Width Measurement Mode
Chapter 11 16-bit Timer/Event Counter T 11.6.7 Pulse width measurement mode In the pulse width measurement mode, counting is performed in the free-running mode. The counter value is saved to the TTnCCR0 register, and the counter is cleared to 0000H. As a result, the external input pulse width can be measured.
Page 512: Triangular Wave Pwm Mode
Chapter 11 16-bit Timer/Event Counter T 11.6.8 Triangular wave PWM mode In the triangular wave PWM mode, similarly to in the PWM mode, when the duty is set to the TTnCCR1 register, the cycle is set to the TTnCCR0 register, and TTnCE = 1 is set, variable duty and cycle type triangular wave PWM output is performed from pin TOTn1.
Page 513: Figure 11-34: Basic Operation Timing In Triangular Wave Pwm Mode
Chapter 11 16-bit Timer/Event Counter T Figure 11-34: Basic Operation Timing in Triangular Wave PWM Mode (a) When TOTn0, TOTn1 are output (TTnOE0, 1 = 1, TTnOL0, 1 = 0) FFFFH FFFFH Counter TTnCE TTnCCR0 0000H TTnCCR1 0000H INTTTnCC0 INTTTnCC1 INTTTnOV TOTn0 TOTn1...
Page 514: Encoder Count Function
Chapter 11 16-bit Timer/Event Counter T 11.6.9 Encoder count function The encoder compare mode is provided as follows. Mode TTnCCR0 register TTnCCR1 register Encoder compare mode Compare only Compare only Counter up/down control Counter up/down control is performed and the counter is operated according to the phase of signals TENCTn0 and TENCTn1 from the encoder and the set conditions of bits TTnUDS1 and TTnUDS0 of the TTnCTL2 register.
Page 515 Chapter 11 16-bit Timer/Event Counter T Control through TTnCTL2 register The settings of the TTnCTL2 register in the encoder compare mode (TTnMD3 to TTnMD0 = 1000B) are as follows. TTnMD3 to 0 TTnUDS1 to 0 TTnECM1 TTnECM0 TTnLDE Clear Load 1000B All settings possible...
Page 516: Figure 11-35: Encoder Count Function Up/Down Count Selection Specification Timings (1/6)
Chapter 11 16-bit Timer/Event Counter T (a) Up/down count selection specification (TTnCTL2 register bits TTnUDS1, TTnUDS0) Counter up/down is judged according to the settings of bits TTnUDS1 and TTnUDS0, and the phases input from pins TENCTn0 and TENCTn1. Bits TTnUDS1 and TTnUDS0 are valid only in the encoder compare mode. <1>...
Page 517 Chapter 11 16-bit Timer/Event Counter T <2> TTnCTL2: TTnUDS1, 0 = 01B (count judgment mode 2) A Phase (Pin TENCTn0) B Phase (Pin TENCTn1) Count Low level Rising edge Down Falling edge Both edges High level Rising edge Falling edge Both edges Rising edge Low level...
Page 518 Chapter 11 16-bit Timer/Event Counter T <3> TTnCTL2: TTnUDS1, 0 = 10B (count judgment mode 3) A Phase (Pin TENCTn0) B Phase (Pin TENCTn1) Count Low level Falling edge Hold Rising edge Low level Down High level Rising edge Hold Falling edge High level Rising edge...
Page 519 Chapter 11 16-bit Timer/Event Counter T <4> TTnCTL2: TTnUDS1, 0 = 11B (count judgment mode 4) A Phase (Pin TENCTn0) B Phase (Pin TENCTn1) Count Low level Falling edge Down Rising edge Low level High level Rising edge Falling edge High level Rising edge High level...
Page 520 Chapter 11 16-bit Timer/Event Counter T Operation example 2: TTnIOC2: TTnEIS3 to 0 (pins TENCTn1, TENCTn0) edge detection specification invalid. Figure 11-35: Encoder Count Function Up/Down Count Selection Specification Timings (5/6) (e) Timing 5 TENCTn0 TENCTn1 Counter Up count Hold Up count Down count Up count...
Page 521 Chapter 11 16-bit Timer/Event Counter T (b) Counter clear condition setting upon match between counter value and compare setting value (TTnCTL2 register bits TTnECM1, TTnECM0) Counter operation is performed according to the setting values of these bits upon a match between the counter value and the compare setting value.
Page 522 Chapter 11 16-bit Timer/Event Counter T (c) Counter load function for TTnCCR0 register setting value upon underflow (bit TTnLDE of register TTnCTL2)) The setting value of the TTnCCR0 register can be loaded to the counter upon counter underflow, by setting TTnLDE = 1. Bit TTnLDE is only valid in the encoder compare mode.
Page 523: Figure 11-36: Counter Clearing To 0000H Through Encoder Clear Input (Pin Tecrtn)
Chapter 11 16-bit Timer/Event Counter T Counter clearing to 0000H through encoder clear input (pin TECRTn) (TTnIOC3 register bits TTnSCE, TTnECS1, TTnECS0) There are two methods to clear the counter to 0000H through TECRTn pin input, and encoder clear input is controlled by bit TTnSCE. Bits TTnZCL, TTnBCL, TTnACL, TTnECS1, and TTnECS0 are controlled by the setting of bit TTnSCE.
Page 524 Chapter 11 16-bit Timer/Event Counter T <2> Method to clear counter to 0000H through detection of level clear condition (TTnSCE = 1) When TTnSCE = 1, the counter is cleared to 0000H according to the clear condition level of pins TECRTn, TENCTn1, and TENCTn0 set with bits TTnZCL, TTnBCL, and TTnACL.
Page 525 Chapter 11 16-bit Timer/Event Counter T Figure 11-36: Counter Clearing to 0000H through Encoder Clear Input (pin TECRTn) Timings (3/4) (c) when TECRTn Pin Input and TENCTn1 Pin Input Occur Simultaneously During Up Count Signal after edge detection TENCTn0 TENCTn1 TECRTn Base clock Counter...
Page 526 Chapter 11 16-bit Timer/Event Counter T Figure 11-36: Counter Clearing to 0000H through Encoder Clear Input (pin TECRTn) Timings (4/4) (e) when TECRTn Pin Input Occurs Later Than TENCTn1 Pin Input During Down Count Signal after edge detection TENCTn0 TENCTn1 TECRTn Base clock Counter...
Page 527: Figure 11-37: Counter Hold Through Bit Ttnecc Timings (1/5)
Chapter 11 16-bit Timer/Event Counter T Counter hold through bit TTnECC (a) Initial counter operation through bit TTnECC setting Figure 11-37: Counter Hold through Bit TTnECC Timings (1/5) (a) Count operation when TTnECC = 0 is set Base clock TTnECC TTnCE Internal count...
Page 528 Chapter 11 16-bit Timer/Event Counter T (b) Bit TTnECC rewrite timing and its influence on counter <1> When setting value of bit TTnECC is rewritten 0 → 1 → 0 when TTnCE = 1 Even if bit TTnECC rewrite is performed while TTnCE = 1, this has no influence on the counter operation.
Page 529 Chapter 11 16-bit Timer/Event Counter T (c) Rewrite timing of bit TTnECC When TTnCE = 0 and TTnECC = 0, setting TTnCE = 1 causes the setting value of the TTnTCW register to be loaded to the counter. Perform rewrite of the TTnECC bit after the operation clock has become valid (after several clocks: TBD), following setting of TTnCE = 1.
Page 530 Chapter 11 16-bit Timer/Event Counter T Figure 11-37: Counter Hold through Bit TTnECC Timings (4/5) (f) Basic Timing in Encoder Compare Mode (2) <Setting conditions> • TTnCTL0: TTnMD3 to 0 = 1000B Encoder compare mode • TTnCTL1: TTnUDS1, 0 = 11B Judgment of up/down count with count judgment mode 4 •...
Page 531 Chapter 11 16-bit Timer/Event Counter T Figure 11-37: Counter Hold through Bit TTnECC Timings (5/5) (g) Basic Timing in Encoder Compare Mode (3) <Setting conditions> • TTnCTL0: TTnMD3 to 0 = 1000B Encoder compare mode • TTnCTL1: TTnUDS1 to 0 = 11B Judgment of up/down count with count judgment mode 4 •...
Page 532: Offset Trigger Generation Mode
Chapter 11 16-bit Timer/Event Counter T 11.6.10 Offset trigger generation mode In the offset trigger generation mode, the count value is saved to the capture register (TTnCCR0) upon detection of the valid edge of the TITn0 pin, and a capture interrupt (INTTTnCC0) is output. The counter is cleared to 0000H by capture input.
Page 533: Figure 11-38: Basic Timing In Offset Trigger Generation Mode
Chapter 11 16-bit Timer/Event Counter T Figure 11-38: Basic Timing in Offset Trigger Generation Mode 0000H XXXX TTnCCR0 TTnCCR1 TTnCCB1 TITn0 INTTTnCC0 INTTTICC1 Fixed (according to setting value of TTnOL0) TOTn0 TOTn1 Compare Capture Compare Compare Capture Capture match interrupt interrupt match interrupt match interrupt...
Page 534 Chapter 11 16-bit Timer/Event Counter T User’s Manual U16580EE3V1UD00...
Page 535: Timer (Tmenc10) (Μpd70F3187 Only)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (μPD70F3187 only) 12.1 Features Timer ENC10 (TMENC10) is a 16-bit up/down counter that performs the following operations. • General-purpose timer mode: - Free-running timer - PWM output • Up/down counter mode - UDC mode A - UDC mode B TMENC10 is available on μPD70F3187 only.
Page 536 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) • PWM output function - In the general-purpose timer mode, 16-bit resolution PWM output can be output from the TO1 pin. • Timer clear - The following timer clear operations are performed according to the mode that is used. (a) General-purpose timer mode: Timer clear operation is possible upon occurrence of match with CM100 set value.
Page 537: Basic Configuration
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.3 Basic Configuration The basic configuration is shown below. Table 12-1: Timer ENC10 Configuration List Timer Count Clock Register Read/Write Generated Capture Trigger Interrupt Signal Timer TMENC10 Read/write INTOVF ENC10 INTUDF /16,...
Page 538: Figure 12-1: Block Diagram Of Timer Enc10 (Tmenc10)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Figure 12-1 shows the block diagram of timer ENC10. Figure 12-1: Block Diagram of Timer ENC10 (TMENC10) Internal bus Edge detector INTCC10 CC10 Selector CC11 Edge INTCC11 TM1UBD Selector detector TCLR1/ Edge...
Page 539: Figure 12-2: Timer Enc10 (Tmenc10)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Timer ENC10 (TMENC10) TMENC10 is a 2-phase encoder input up/down counter and general-purpose timer. It can be read/written in 16-bit units. Reset input clears TMENC10 to 0000H. Cautions: 1. Write to TMENC10 is enabled only when the TM1CE bit of the TMC10 register is “0”...
Page 540: Table 12-2: Timer Enc10 (Tmenc10) Clear Conditions
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) When the TM1CE bit of the TMC10 register is “1”, TMENC10 counts up when the operation mode is the general-purpose mode, and counts up/down when the operation mode is the UDC mode. The conditions for clearing the TMENC10 are classified as follows depending on the operation mode.
Page 541: Figure 12-3: Compare Register 100 (Cm100)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Compare register 100 (CM100) CM100 is a 16-bit register that always compares its value with the value of TMENC10. When the value of a compare register matches the value of TMENC10, an interrupt signal is generated. The interrupt generation timing in the various modes is described below.
Page 542: Figure 12-4: Compare Register 101 (Cm101)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Compare register 101 (CM101) CM101 is a 16-bit register that always compares its value with the value of TMENC10. When the value of a compare register matches the value of TMENC10, an interrupt signal is generated. The interrupt generation timing in the various modes is described below.
Page 543: Figure 12-5: Capture/Compare Register 100 (Cc100)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Capture/compare register 100 (CC100) CC100 is a 16-bit register. It can be used as a capture register or as a compare register through specification with capture/compare control register n (CCR). This register can be read/written in 16-bit units.
Page 544: Figure 12-6: Capture/Compare Register 101 (Cc101)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Capture/compare register 101 (CC101) CC101 is a 16-bit register. It can be used as a capture register or as a compare register through specification with capture/compare control register (CCR). This register can be read/written in 16-bit units.
Page 545: Control Registers
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.4 Control Registers Timer unit mode register 10 (TUM10) The TUM10 register is an 8-bit register used to specify the TMENC10 operation mode or to control the operation of the PWM output pin. This register can be read/written in 8-bit or 1-bit units.
Page 546: Figure 12-8: Timer Control Register 10 (Tmc10) (1/2)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Timer control register 10 (TMC10) The TMC10 register is used to enable/disable TMENC10 operation and to set transfer and timer clear operations. This register can be read/written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 547 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Figure 12-8: Timer Control Register 10 (TMC10) (2/2) CLR1 CLR0 Clear Operation Control in UDC Mode A Clear only by external input (TCLR1) Clear upon match of TMENC10 count value and CM100 set value Clear by TCLR1 input or upon match of TMENC10 count value and CM100 set value No clearing...
Page 548: Figure 12-9: Capture/Compare Control Register 10(Ccr10)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Capture/compare control register 10 (CCR10) The CCR10 register specifies the operation mode of the capture/compare registers (CC100, CC101). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 549: Figure 12-10: Signal Edge Selection Register 10 (Sesa10) (1/2)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Signal edge selection register 10 (SESA10) The SESA10 register specifies the valid edge of external interrupt requests from external pins (TICC10, TICC11, TCLR1). The valid edge (rising edge, falling edge, or both edges) can be specified independently for each pin.
Page 550 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Figure 12-10: Signal Edge Selection Register 10 (SESA10) (2/2) IES111 IES110 Valid Edge Specification of TICC11 Capture Trigger Input Pin Falling edge Rising edge Setting prohibited Both, rising and falling edges A valid edge on the TICC11 pin triggers the capture register CC101.
Page 551: Figure 12-11: Prescaler Mode Register 10 (Prm10)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Prescaler mode register 10 (PRM10) The PRM register is used to perform the following selections. • Selection of count clock in the general-purpose timer mode (CMD bit of TUM10 register = 0) •...
Page 552 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (b) UDC mode (CMD bit = 1) The TMENC10 count triggers in the UDC mode are as follows. Operation Mode TMENC10 Operation Mode 1 Down count when TCUD1 = high level Up count when TCUD1 = low level Mode 2 Up count upon detection of valid edge of TIUD1 input...
Page 553: Figure 12-12: Status Register 10 (Status10)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Status register 10 (STATUS10) The STATUS10 register indicates the operating status of TMENC10. This register is read-only in 8-bit or 1-bit units. Reset input clears this register to 00H. Caution: Overwriting the STATUS10 register during TMENC10 operation (TM1CE bit = 1) is pro- hibited.
Page 554: Operation
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.5 Operation 12.5.1 Basic operation The following two operation modes can be selected for TMENC10. General-purpose timer mode (CMD bit of TUM10 register = 0) In the general-purpose timer mode, the TMENC10 operates either as a 16-bit interval timer or as a PWM output timer (count operation is up count only).
Page 555: Operation In General-Purpose Timer Mode
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.5.2 Operation in general-purpose timer mode TMENC10 can perform the following operations in the general-purpose timer mode. Interval operation TMENC10 and CM100 always compare their values and the INTCM10 interrupt is generated upon occurrence of a match.
Page 556: Figure 12-13: Tmenc10 Block Diagram (During Pwm Output Operation)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Capture function TMENC10 connects two capture/compare register (CC100, CC101) channels. When CC100 and CC101 are set to the capture register mode, the value of TMENC10 is captured in synchronization with the corresponding capture trigger signal. Furthermore, an interrupt request (INTCC10, INTCC11) is generated by the TICC10, TICC11 input signals.
Page 557: Figure 12-14: Pwm Signal Output Example (When Alvt10 Bit = 0 Is Set)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) • Description of operation The PWM output cycle is specified by using the compare register CM100. When the value of this register matches the value of TMENC10, the INTCM10 interrupt is generated, and TMENC10 is cleared at the next count clock after the match.
Page 558: Operation In Udc Mode
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.5.3 Operation in UDC mode Overview of operation in UDC mode The count clock input to TMENC10 in the UDC mode (CMD bit of TUM10 register = 1) can only be externally input from the TIUD1 and TCUD1 pins.
Page 559: Figure 12-15: Mode 1 (When Rising Edge Is Specified As Valid Edge Of Tiud1 Pin)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Up/down count operation in UDC mode TMENC10 up/down count judgment in the UDC mode is determined based on the phase difference of the TIUD1 and TCUD1 pin inputs according to the PRM register setting. (a) Mode 1 (PRM12 to PRM10 bits = 100B) In mode 1, the following count operations are performed based on the level of the TCUD1 pin upon detection of the valid edge of the TIUD1 pin.
Page 560: Figure 12-17: Mode 2 (When Rising Edge Is Specified As Valid Edge Of Tiud1, Tcud1 Pins)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (b) Mode 2 (PRM102 to PRM100 bits = 101B) The count conditions in mode 2 are as follows. • TMENC10 up count upon detection of valid edge of TIUD1 pin •...
Page 561: Figure 12-18: Mode 3 (When Rising Edge Is Specified As Valid Edge Of Tiud1 Pin)
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (c) Mode 3 (PRM102 to PRM100 bits = 110B) In mode 3, when two signals 90 degrees out of phase are input to the TIUD1 and TCUD1 pins, the level of the TCUD1 pin is sampled at the timing of the valid edge of the TIUD1 pin (refer to Figure 12-18).
Page 562: Figure 12-20: Mode 4
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (d) Mode 4 (PRM102 to PRM100 bits = 111B) In mode 4, when two signals out of phase are input to the TIUD1 and TCUD1 pins, up/down operation is automatically judged and counting is performed according to the timing shown in Figure 12-20.
Page 563: Figure 12-21: Example Of Tmenc10 Operation When Interval Operation And Transfer Operation Are Combined
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) Operation in UDC mode A (a) Interval operation The operations at the count clock following a match of the TMENC10 count value and the CM100 set value are as follows. •...
Page 564: Figure 12-22: Example Of Tm1Operation In Udc Mode
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (c) Compare function TM1n connects two compare register (CM100, CM101) channels and two capture/compare register (CC100, CC101) channels. When the TMENC10 count value and the set value of one of the compare registers match, a Note Note match interrupt (INTCM10, INTCM11, INTCC10...
Page 565 Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) (b) Compare function TMENC10 connects two compare register (CM100, CM101) channels and two capture/compare register (CC100, CC101) channels. When the TMENC10 count value and the set value of one of the compare registers match, a match interrupt (INTCM10 (only during up count operation), INTCM11 (only during down count Note Note...
Page 566: Supplementary Description Of Internal Operation
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.6 Supplementary Description of Internal Operation 12.6.1 Clearing of count value in UDC mode B When TMENC10 is in UDC mode B, the count value clear operation is as follows. •...
Page 567: Clearing Of Count Value Upon Occurrence Of Compare Match
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.6.2 Clearing of count value upon occurrence of compare match The internal operation during TMENC10 clear operation upon occurrence of a compare match is as follows. Figure 12-25: Count Value Clear Operation upon Compare Match Clear TMENC1 (Not clear TMENC1) Count clock...
Page 568: Interrupt Signal Output Upon Compare Match
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10) 12.6.4 Interrupt signal output upon compare match An interrupt signal is output when the count value of TMENC10 matches the set value of the CM100, Note Note CM101, CC10 , or CC11 register.
Page 569: Chapter 13 Auxiliary Frequency Output Function (Afo)
Chapter 13 Auxiliary Frequency Output Function (AFO) 13.1 Features • Frequency up to 8 Mbps • Programmable frequency output • Interval timer function • Interrupt request signal (INTBRG2) 13.2 Configuration The AFO function includes the following hardware. Table 13-1: AFO Configuration Item Configuration Control registers...
Page 570: Control Registers
Chapter 13 Auxiliary Frequency Output Function (AFO) 13.3 Control Registers Prescaler mode register 2 (PRSM2) The PRSM2 register controls generation of a baud rate signal for the AFO function. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 571: Figure 13-3: Prescaler Compare Register 2 (Prscm2)
Chapter 13 Auxiliary Frequency Output Function (AFO) Prescaler compare registers 2 (PRSCM2) The PRSCM2 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 13-3: Prescaler Compare Register 2 (PRSCM2) After reset: Address: FFFFFDE1H...
Page 572: Operation
Chapter 13 Auxiliary Frequency Output Function (AFO) 13.4 Operation 13.4.1 Auxiliary frequency output The auxiliary frequency output (AFO) is enabled as soon as the shared port (P75) is set into control output mode by setting bit 5 of the PM7 register to 0 and bit 5 of the PMC7 register to 1. 13.4.2 Auxiliary frequency generation The auxiliary frequency output clock is generated by dividing the main clock.
Page 573: Chapter 14 A/D Converter
Chapter 14 A/D Converter 14.1 Features × • Analog input: 2 10 channels (ANI00 to ANI09, ANI10 to ANI19) • 10-bit resolution • On-chip A/D conversion result register (ADCRn0 to ADCRn9): 10 bits × 10 • A/D conversion trigger mode - A/D trigger mode - Timer trigger mode - External trigger mode...
Page 574: Configuration
Chapter 14 A/D Converter 14.2 Configuration The A/D converter of the V850E/PH2 adopts the successive approximation method, and uses A/D con- verter n mode registers 0, 1, 2 (ADMn0, ADMn1, ADMn2), and the A/D conversion result register (ADCRn0 to ADCRn9) to perform A/D conversion operations (n = 0, 1).
Page 575: Figure 14-1: Block Diagram Of A/D Converter (Adcn)
Chapter 14 A/D Converter pin (n = 0, 1) This is the ground pin of the A/D converter. Always use this pin at the same potential as that of the pin even when the A/D converter is not used. (10) AV This is the analog power supply pin of both A/D converters (ADC0, ADC1).
Page 576: Control Registers
Chapter 14 A/D Converter 14.3 Control Registers A/D converter n mode register 0 (ADMn0) The ADMn0 register is an 8-bit register that specifies the operation mode, and executes conversion operations. This register can be read or written in 8-bit or 1-bit units. However, bit 6 can only be read. Writing this bit is ignored.
Page 577: Figure 14-3: A/D Converter N Mode Register 1 (Admn1) (1/2)
Chapter 14 A/D Converter A/D converter n mode register 1 (ADMn1) The ADMn1 register is an 8-bit register that specifies the conversion operation time and trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H. Cautions: 1.
Page 578 Chapter 14 A/D Converter Figure 14-3: A/D Converter n Mode Register 1 (ADMn1) (2/2) FRn3 FRn2 FRn1 FRn0 Number of Note 1 Conversion Operation Time conversion = 64 MHz A/D Stabilization clocks Note 2 Time 2.0 µs 64/f 4.0 µs 128/f 6.0 µs 160/f...
Page 579: Figure 14-4: A/D Converter N Mode Register 2 (Admn2)
Chapter 14 A/D Converter A/D converter n mode register 2 (ADMn2) The ADMn2 register is an 8-bit register that specifies the analog input pin of the A/D converter n (n = 0, 1). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H.
Page 580: Figure 14-5: A/D Converter N Trigger Source Select Register (Adtrseln)
Chapter 14 A/D Converter A/D converter n trigger source select register (ADTRSELn) The ADTRSELn register is an 8-bit register that specifies the timer trigger signal in the timer trigger mode (TRGn1, TRGn0 bits of ADMn1 register = 01B). This register can be read or written in 8-bit units. Reset input sets this register to 00H.
Page 581: Figure 14-6: A/D Conversion Result Registers N0 To N9, N0H To N9H (Adcrn0 To Adcrn9, Adcrn0H To Adcrn9H)
Chapter 14 A/D Converter A/D conversion result registers n0 to n9, n0H to n9H (ADCRn0 to ADCRn9, ADCRn0H to ADCRn9H) The ADCRnm register is a 10-bit register holding the A/D conversion results (n = 0, 1)(m = 0 to 9). These registers are read-only in 16-bit or 8-bit units.
Page 582: Table 14-1: Assignment Of A/D Conversion Result Registers To Analog Input Pins
Chapter 14 A/D Converter The correspondence between each analog input pin and the ADCRnm register is shown in Table 14-1 below. Table 14-1: Assignment of A/D Conversion Result Registers to Analog Input Pins Analog Input Pin Assignment of A/D Conversion Result Registers Select 1 Buffer Mode/ Select 4 Buffer Mode Scan Mode...
Page 583: Figure 14-7: Relationship Between Analog Input Voltage And A/D Conversion Results
Chapter 14 A/D Converter Figure 14-7: Relationship Between Analog Input Voltage and A/D Conversion Results 1023 1022 A/D conversion 1021 results (ADCRnm) 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 Input voltage/AV Remark: n = 0, 1 m = 0 to 9...
Page 584: Figure 14-8: A/D Conversion Result Registers N0 To N9, N0H To N9H (Adcrn0 To Adcrn9, Adcrn0H To Adcrn9H)
Chapter 14 A/D Converter A/D conversion result register n for DMA (ADDMAn) The ADDMAn register is a 16-bit register holding the result of the latest A/D conversion operation, and is used for DMA transfer of ADCn results into the internal RAM. It has an overrun detection flag indicating an overrun situation of the DMA transfer mechanism (n = 0, 1).
Page 585: Operation
Chapter 14 A/D Converter 14.4 Operation 14.4.1 Basic operation A/D conversion is executed by the following procedure. <1> The selection of the analog input and specification of the operation mode, trigger mode, etc. Note 1 (n = 0, 1). should be specified using the ADMn0, ADMn1 or ADMn2 registers When the ADCEn bit of the ADMn0 register is set to 1, A/D conversion starts in the A/D trigger Note 2 mode.
Page 586: Operation Mode And Trigger Mode
Chapter 14 A/D Converter 14.4.2 Operation mode and trigger mode Various conversion operations can be specified for the A/D converter by specifying the operation mode and trigger mode. The operation mode and trigger mode are set by the ADMn0 and ADMn1registers. The following table shows the relationship between the operation mode and trigger mode.
Page 587 Chapter 14 A/D Converter (c) External trigger mode This mode specifies the conversion timing of the analog input to the ANIn0 to ANIn9 pins using the ADTRGn pin. The EGAn1 and EGAn0 bits of the ADMn1 register are used to specify the valid edge to be input to the ADTRGn pin.
Page 588: Figure 14-9: Select Mode Operation Timing: 1-Buffer Mode (Anin1)
Chapter 14 A/D Converter Figure 14-9: Select Mode Operation Timing: 1-Buffer Mode (ANIn1) ANIn1 (input) Data 1 Data 2 Data 3 Data 5 Data 6 Data 4 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 A/D conversion (ANIn1) (ANIn1) (ANIn1)
Page 589: Figure 14-10: Select Mode Operation Timing: 4-Buffer Mode (Anin2)
Chapter 14 A/D Converter • 4-buffer mode In this mode, one analog input is A/D converted and the results are stored in the ADCRnm regis- ters. The A/D conversion end interrupt (INTADn) is generated when the four A/D conversions end (m = 0 to 3 when one of the analog input channels ANIn0 to ANIn3 is specified, m = 4 to 7 when one of analog input channels ANIn4 to ANIn7 is specified, and m = 8 to 9 when one of the analog input channels ANIn8 or ANIn9 is specified).
Page 590: Figure 14-11: Scan Mode Operation Timing: 4-Channel Scan (Ani0 To Ani3)
Chapter 14 A/D Converter (b) Scan mode In this mode, the analog inputs specified by the ADMn2 register are selected sequentially from the ANIn0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRnm register corresponding to the analog input (m = 0 to 9). When the conversion of the specified analog input ends, the A/D conversion end interrupt (INTADn) is generated.
Page 591: Operation In A/D Trigger Mode
Chapter 14 A/D Converter 14.5 Operation in A/D Trigger Mode When the ADCEn bit of the ADMn0 register is set to 1, A/D conversion is started. 14.5.1 Select mode operation In this mode, the analog input specified by the ADMn2 register is A/D converted. The conversion results are stored in the ADCRnm register corresponding to the analog input.
Page 592: Table 14-4: Correspondence Between Analog Input Pins And Adcrnm Register (A/D Trigger Select: 4 Buffers)
Chapter 14 A/D Converter 4-buffer mode (A/D trigger select: 4 buffers) In this mode, one analog input is A/D converted four times (two times for analog input ANIn8 or ANIn9) and the results are stored in the ADCRnm register. When the 4th A/D conversion ends, an A/D conversion end interrupt (INTADn) is generated and the A/D conversion is stopped.
Page 593: Figure 14-13: Example Of 4-Buffer Mode Operation (A/D Trigger Select: 4 Buffers)
Chapter 14 A/D Converter Figure 14-13: Example of 4-Buffer Mode Operation (A/D Trigger Select: 4 Buffers) ADMn2 ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ADCRn2 A/D converter ANIn3 ADCRn3 (ADCn) × ANIn4 ADCRn4 ( 4) ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9...
Page 594: Scan Mode Operations
Chapter 14 A/D Converter 14.5.2 Scan mode operations In this mode, the analog inputs specified by the ADMn2 register are selected sequentially from the ANIn0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRnm register corresponding to the analog input (m = 0 to 9).
Page 595: Figure 14-14: Example Of Scan Mode Operation (A/D Trigger Scan)
Chapter 14 A/D Converter Figure 14-14: Example of Scan Mode Operation (A/D Trigger Scan) ADMn2 ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ADCRn2 A/D converter ANIn3 ADCRn3 (ADCn) ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 <1> The ADCEn bit of ADMn0 register is set to 1 (enable) <2>...
Page 596: Operation In Timer Trigger Mode
Chapter 14 A/D Converter 14.6 Operation in Timer Trigger Mode In this mode, the conversion timing of the analog input signal set by the ANIn0 to ANIn9 pins is defined by a timer event signal (A/D converter trigger signal, or top and bottom reversal interrupt) of the inverter timers R0 and R1 (TMR0, TMR1).
Page 597: Figure 14-15: Example Of 1-Buffer Mode Operation (Timer Trigger Select: 1 Buffer) (Anin1)
Chapter 14 A/D Converter Table 14-6: Correspondence Between Analog Input Pins and ADCRnm Register (1-Buffer Mode (Timer Trigger Select: 1 Buffer)) Trigger Analog Input A/D Conversion Result Register Timer event signal ANIn0 ADCRn0 (TR0ADTRG0, ANIn1 ADCRn1 TR0ADTRG1, ANIn2 ADCRn2 TR1ADTRG0, TR1ADTRG1, ANIn3 ADCRn3...
Page 598: Table 14-7: Correspondence Between Analog Input Pins And Adcrnm Register (4-Buffer Mode (Timer Trigger Select: 4 Buffers))
Chapter 14 A/D Converter 4-buffer mode operation (timer trigger select: 4 buffers) In this mode, A/D conversion of one analog input is executed four times, and the results are stored in the ADCRnm register. One analog input is A/D converted four times using the timer event signals (TR0ADTRG0, TR0ADTRG1, TR1ADTRG0, TR1ADTRG1, INTTR0CD, INTR0OD, INTTR1CD, INTTR1OD) as a trigger, and the results are stored in four ADCRnm registers.
Page 599: Figure 14-16: Example Of 4-Buffer Mode Operation (Timer Trigger Select: 4 Buffers) (Anin3)
Chapter 14 A/D Converter Figure 14-16: Example of 4-Buffer Mode Operation (Timer Trigger Select: 4 Buffers) (ANIn3) × ( 4) ANIn0 ADCRn0 TR0ADTRG0 ANIn1 ADCRn1 ANIn2 ADCRn2 × ( 4) ANIn3 ADCRn3 A/D converter ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8...
Page 600: Scan Mode Operation
Chapter 14 A/D Converter 14.6.2 Scan mode operation In this mode, the analog inputs specified by the ADMn2 register are selected sequentially from the ANIn0 pin and are A/D converted the specified number of times using the timer event signal as a trigger.
Page 601: Figure 14-17: Example Of Scan Mode Operation (Timer Trigger Scan) (Anin0 To Anin4)
Chapter 14 A/D Converter Figure 14-17: Example of Scan Mode Operation (Timer Trigger Scan) (ANIn0 to ANIn4) ANIn0 ADCRn0 ANIn1 ADCRn1 TR0ADTRG0 ANIn2 ADCRn2 A/D converter ANIn3 ADCRn3 (ADCn) ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 <1>...
Page 602: Operation In External Trigger Mode
Chapter 14 A/D Converter 14.7 Operation in External Trigger Mode In this mode, the conversion timing of the analog signals input to the ANIn0 to ANIn9 pins is specified by the ADTRGn pin. Detection of the valid edge at the ADTRGn input pin is specified by using the EGAn1 and EGAn0 bits of the ADMn1 register.
Page 603: Figure 14-18: Example Of 1-Buffer Mode Operation (External Trigger Select: 1 Buffer) (Anin1)
Chapter 14 A/D Converter Figure 14-18: Example of 1-Buffer Mode Operation (External Trigger Select: 1 Buffer) (ANIn1) ANIn0 ADCRn0 ADTRGn ANIn1 ADCRn1 ANIn2 ADCRn2 A/D converter ANIn3 ADCRn3 (ADCn) ANIn4 ADCRn4 ADCRn5 ANIn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 <1>...
Page 604: Table 14-10: Correspondence Between Analog Input Pins And Adcrnm Register (External Trigger Select: 4 Buffers))
Chapter 14 A/D Converter 4-buffer mode (external trigger select: 4 buffers) In this mode, one analog input is A/D converted four times using the ADTRGn signal as a trigger and the results are stored in the ADCRnm register. The A/D conversion end interrupt (INTADn) is generated and A/D conversion is stopped after the 4th A/D conversion.
Page 605: Figure 14-19: Example Of 4-Buffer Mode Operation (External Trigger Select: 4 Buffers) (Anin2)
Chapter 14 A/D Converter Figure 14-19: Example of 4-Buffer Mode Operation (External Trigger Select: 4 Buffers) (ANIn2) ANIn0 ADCRn0 ANIn1 ADCRn1 × × ( 4) ( 4) ADTRGn ANIn2 ADCRn2 ANIn3 ADCRn3 A/D converter (ADCn) ANIn4 ADCRn4 ADCRn5 ANIn5 ANIn6 ADCRn6 ANIn7 ADCRn7...
Page 606: Scan Mode Operation
Chapter 14 A/D Converter 14.7.2 Scan mode operation In this mode, the analog inputs specified by the ADMn2 register are selected sequentially from the ANIn0 pin using the ADTRGn signal as a trigger, and A/D converted. The A/D conversion results are stored in the ADCRnm register corresponding to the analog input ANInm (n = 0, 1)(m = 0 to 9).
Page 607: Figure 14-20: Example Of Scan Mode Operation (External Trigger Scan) (Anin0 To Anin3)
Chapter 14 A/D Converter Figure 14-20: Example of Scan Mode Operation (External Trigger Scan) (ANIn0 to ANIn3) ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ADCRn2 ADTRGn ANIn3 ADCRn3 A/D converter (ADCn) ANIn4 ADCRn4 ADCRn5 ANIn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADCRn9 <1>...
Page 608: Precautions
Chapter 14 A/D Converter 14.8 Precautions Stopping conversion operation When the ADCEn bit of the ADMn0 register is cleared to 0 during a conversion operation, the conversion operation stops and the conversion results are not stored in the ADCRnm register (n = 0, 1), (m = 0 to 9).
Page 609: Chapter 15 Asynchronous Serial Interface C (Uartc)
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.1 Features • Transfer speed: 16 bps to 2000 kbps • Full-duplex communication: Internal UARTC receive data register n (UCnRX) Internal UARTC transmit data register n (UCnTX) • 2-pin configuration: TXDCn: Transmit data output pin RXDCn: Receive data input pin •...
Page 610: Configuration
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.2 Configuration UARTCn control register 0 (UCnCTL0) The UCnCTL0 register is an 8-bit register used to specify the asynchronous serial interface operation. UARTCn control register 1 (UCnCTL1) The UCnCTL1 register is an 8-bit register used to select the input clock for the asynchronous serial interface.
Page 611: Figure 15-1: Block Diagram Of Asynchronous Serial Interface N
Chapter 15 Asynchronous Serial Interface C (UARTC) (11) UARTCn transmit data register (UCnTX) The UCnTX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the UCnTX register. When data can be written to the UCnTX register (when data of one frame is transferred from the UCnTX register to the UARTCn transmit shift register), the transmission enable interrupt (INUCnT) is generated.
Page 612: Control Registers
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.3 Control Registers UARTCn control register 0 (UCnCTL0) The UCnCTL0 register is an 8-bit register that controls the UARTCn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 10H.
Page 613 Chapter 15 Asynchronous Serial Interface C (UARTC) Figure 15-2: UARTCn Control Register 0 (UCnCTL0) (2/2) UCnDIR Transfer Direction Selection MSB-first transfer LSB-first transfer This bit can be rewritten only when UCnPWR bit = 0 or UCnTXE bit = UCnRXE bit = 0. UCnPS1 UCnPS0 Parity Selection...
Page 614: Figure 15-3: Uartcn Control Register 1 (Ucnctl1)
Chapter 15 Asynchronous Serial Interface C (UARTC) UARTCn control register 1 (UCnCTL1) The UCnCTL1 register is an 8-bit register that selects the UARTCn base clock XCLK This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 15-3: UARTCn Control Register 1 (UCnCTL1) After reset: Address:...
Page 615: Figure 15-4: Uartcn Control Register 2 (Ucnctl2)
Chapter 15 Asynchronous Serial Interface C (UARTC) UARTCn control register 2 (UCnCTL2) The UCnCTL2 register is an 8-bit register that specifies the divisor to control the baud rate (serial transfer speed) clock of UARTCn. This register can be read or written in 8-bit units. Reset input sets this register to FFH.
Page 616: Figure 15-5: Uartcn Option Control Register 0 (Ucnopt0) (1/2)
Chapter 15 Asynchronous Serial Interface C (UARTC) UARTCn option control register 0 (UCnOPT0) The UCnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTCn register. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 14H.
Page 617 Chapter 15 Asynchronous Serial Interface C (UARTC) Figure 15-5: UARTCn Option Control Register 0 (UCnOPT0) (2/2) UCnSLS2 UCnSLS1 UCnSLS0 SBF Length Selection 13-bit output (reset value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output This register can be set when the UCnPWR bit of the UCnCTL0 register is 0 or when the UCnRXE bit of the UCnCTL0 register is 0.
Page 618: Figure 15-6: Uartcn Option Control Register 1 (Ucnopt1)
Chapter 15 Asynchronous Serial Interface C (UARTC) UARTCn option control register 1 (UCnOPT1) The UCnOPT1 register is an 8-bit register that controls the extension bit operation of the UARTCn. The register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 619: Table 15-1: Relation Between Uartcn Register Settings And Data Format
Chapter 15 Asynchronous Serial Interface C (UARTC) Table 15-1: Relation between UARTCn Register Settings and Data Format Register Bit Settings Data Format UCnEBE UCnPS1 UCnPS0 UCnCL UCnSL D0 - D6 Data Stop Data Stop Stop Data Data Stop Data Data Stop Stop other than 00B...
Page 620: Figure 15-7: Uartcn Status Register (Ucnstr) (1/2)
Chapter 15 Asynchronous Serial Interface C (UARTC) UARTCn status register (UCnSTR) The UCnSTR register is an 8-bit register that displays the UARTCn transfer status and reception error contents. This register can be read or written in 8-bit or 1-bit units, but the UCnTSF bit is a read-only bit, while the UCnPE, UCnFE, and UCnOVE bits can both be read and written.
Page 621 Chapter 15 Asynchronous Serial Interface C (UARTC) Figure 15-7: UARTCn Status Register (UCnSTR) (2/2) UCnFE Framing Error Flag • When UCnPWR bit of UCnCTL0 register = 0 or UCnRXE bit of UCnCTL0 register = 0 has been set • When 0 has been written When no stop bit is detected during reception •...
Page 622: Figure 15-8: Uartcn Status Register 1 (Ucnstr1)
Chapter 15 Asynchronous Serial Interface C (UARTC) UARTCn status register 1 (UCnSTR1) The UCnSTR1 register is an 8-bit register that displays the UARTCn reception status. The register is read only, and be read in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 15-8: UARTCn Status Register 1 (UCnSTR1) After reset: Address:...
Page 623: Figure 15-9: Uartcn Receive Data Register (Ucnrx, Ucnrxl)
Chapter 15 Asynchronous Serial Interface C (UARTC) UARTCn receive data register (UCnRX, UCnRXL) The UCnRX register is a 16-bit buffer register that stores parallel data converted by receive shift register. It is overlayed by an 8-bit register UCnRXL on the lower 8 bits, which stores the lower byte of the received data.
Page 624: Figure 15-10: Uartcn Transmit Data Register (Ucntx, Ucntxl)
Chapter 15 Asynchronous Serial Interface C (UARTC) UARTCn transmit data register (UCnTX, UCnTXL) The UCnTX register is a 16-bit buffer register used to set transmit data. It is overlayed by an 8-bit register UCnTXL on the lower 8 bits. The UCnTXL register is used for setting the transmit data when 7-bit or 8-bit data character length is specified (UCnEBE bit = 0).
Page 625: Interrupt Requests
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.4 Interrupt Requests The following three interrupt requests are generated from UARTCn. • Receive error interrupt (INTUCnRE) • Reception complete interrupt (INTUCnR) • Transmission enable interrupt (INTUCnT) The default priority for these three interrupt requests is highest for the receive error interrupt, followed by the reception complete interrupt, and the transmission enable interrupt.
Page 626: Operation
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5 Operation 15.5.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 15-11, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of MSB/LSB-first transfer are performed using the UCnCTL0 register.
Page 627 Chapter 15 Asynchronous Serial Interface C (UARTC) Figure 15-11: UARTC Transmit/Receive Data Format (2/2) (d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H 1 data frame Start Parity Stop Stop (e) 8-bit data length, LSB first, no parity, 1 stop bit, transfer data: 87H 1 data frame Start Stop...
Page 628: Sbf Transmission/Reception Format
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.2 SBF transmission/reception format The UARTC has a SBF (Sync Break Field) transmission/reception control function to enable use of the LIN (Local Interconnect Network) function. Figure 15-12: LIN Transmission Manipulation Outline Wake-up Synch Check signal break...
Page 629: Figure 15-13: Lin Reception Manipulation Outline
Chapter 15 Asynchronous Serial Interface C (UARTC) Figure 15-13: LIN Reception Manipulation Outline Wake-up Synch Check signal break Synch Ident DATA DATA frame field field field field field field Sleep Note 2 Data Data Note 5 SF reception 13 bits ID reception transmission transmission...
Page 630: Sbf Transmit Operation
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.3 SBF transmit operation When the UCnPWR bit = the UCnTXE bit of the UCnCTL0 register = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UCnSTT bit of UCnOPT0 register).
Page 631: Sbf Receive Operation
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.4 SBF receive operation The reception enabled status is achieved by setting the UCnPWR bit of the UCnCTL0 register to 1 and then setting the UCnRX bit of the UCnCTL0 register to 1. The SBF reception wait status is set by setting the SBF reception trigger (UCnSRT bit of the UCnOPT0 register) to 1.
Page 632: Uart Transmit Operation
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.5 UART transmit operation The transmission enabled status is set by setting the UCnTXE bit of the UCnCTL0 register to 1, after UCnPWR bit was set to 1, and transmission is started by writing transmit data to the UCnTX register. The start bit, parity bit, and stop bit are automatically added.
Page 633: Continuous Transmit Operation
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.6 Continuous transmit operation UARTCn can write the next transmit data to the UCnTX register when the UARTCn transmit shift register starts the shift operation. The transfer timing of the UARTCn transmit shift register can be judged from the transmission enable interrupt (INTUCnT).
Page 634: Figure 15-18: Continuous Transfer Operation Timing
Chapter 15 Asynchronous Serial Interface C (UARTC) Figure 15-18: Continuous Transfer Operation Timing (a) Transmission start Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDCn UCnTX Data (1) Data (2) Data (3) Transmission Data (2) Data (1) shift register INTUCnT UCnTSF...
Page 635: Uart Receive Operation
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.7 UART receive operation The reception wait status is set by setting the UCnPWR bit of the UCnCTL0 register to 1 and then setting the UCnRX bit of the UCnCTL0 register to 1. In the reception wait status, the RXDCn pin is monitored and start bit detection is performed.
Page 636: Receive Error
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.8 Receive error Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. A data reception result error flag is set to the UCnSTR register and a reception error interrupt (INTUCnRE) is output.
Page 637: Parity Types And Operations
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.9 Parity types and operations Caution: When using the LIN function, fix the UCnPS1 and UCnPS0 bits of the UCnCTL0 register to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side.
Page 638: Receive Data Noise Filter
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.5.10 Receive data noise filter This filter performs the RXDCn pin sampling using the internal system clock (f /2). When the same sampling value is read twice, the match detector output changes and sampling as the input data is performed.
Page 639: Dedicated Baud Rate Generator
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.6 Dedicated Baud Rate Generator 15.6.1 Baud rate generator configuration The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTCn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel.
Page 640: Baud Rate
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.6.2 Baud rate The baud rate is obtained by the following equation. XCLK Baud rate = [bps] 2 × k = Frequency of base clock (Clock) selected by bits UCnCKS3 to UCnCKS0 of UCnCTL1 register XCLK k = Value set using bits UCnBRS7 to UCnBRS0 of UCnCTL2 register (k = 4, 5, 6,..., 255) 15.6.3 Baud rate error...
Page 641: Baud Rate Setting Example
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.6.4 Baud rate setting example Table 15-4: Baud Rate Generator Setting Data Baud Rate = 64 MHz [bps] UCnCTL1 UCnCTL2 Error [%] 0.16 0.16 0.16 1200 0.16 2400 0.16 4800 0.16 9600 0.16 10400 0.16 19200...
Page 642: Allowable Baud Rate Range During Reception
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.6.5 Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution: The baud rate error during reception must be set within the allowable error range using the following equation.
Page 643: Table 15-5: Maximum/Minimum Allowable Baud Rate Error
Chapter 15 Asynchronous Serial Interface C (UARTC) Therefore, the maximum baud rate that can be received by the destination is as follows. BRmax = (FLmin/11) 21k + 2 Similarly, obtaining the following maximum allowable transfer rate yields the following. k + 2 21k - 2 ×...
Page 644: Baud Rate During Continuous Transmission
Chapter 15 Asynchronous Serial Interface C (UARTC) 15.6.6 Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 clocks longer. However, timing initialization is performed through start bit detection by the receiving side, so this has no influence on the transfer result.
Page 645: Chapter 16 Clocked Serial Interface B (Csib)
Chapter 16 Clocked Serial Interface B (CSIB) 16.1 Features • Transfer rate: Maximum 8 Mbps • Master mode and slave mode selectable • Serial clock and data phase switchable • Transmission data length: 8 to 16 bits (selectable in 1-bit units) •...
Page 646: Figure 16-1: Block Diagram Of Csibn
Chapter 16 Clocked Serial Interface B (CSIB) Figure 16-1: Block Diagram of CSIBn Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR SSBn INTCBnT INTCBnR Controller INTCBnRE BRG0 BRG1 f /8 f /16 Phase control f /32 f /64 f /128 CBnTX SCKBn Phase SO latch SOBn...
Page 647: Figure 16-2: Csibn Receive Data Register (Cbnrx, Cbnrxl)
Chapter 16 Clocked Serial Interface B (CSIB) CSIBn receive data register (CBnRX, CBnRXL) The CBnRX register is a 16-bit buffer register that holds receive data. It is overlayed by an 8-bit register CBnRXL on the lower 8 bits, which is used when the transfer data length is 8 bits. The receive operation is started by reading the CBnRX or CBnRXL registers during reception enabled status.
Page 648: Figure 16-3: Csibn Transmit Data Register (Cbntx, Cbntxl)
Chapter 16 Clocked Serial Interface B (CSIB) CSIB transmit data register (CBnTX) The CBnTX register is a 16-bit buffer register used to write the CSIB transfer data. It is overlayed by an 8-bit register CBnTXL on the lower 8 bits, which is used when the transfer data length is 8 bits.
Page 649: Control Registers
Chapter 16 Clocked Serial Interface B (CSIB) 16.3 Control Registers The following registers are used to control CSIB. • CSIBn control register 0 (CBnCTL0) • CSIBn control register 1 (CBnCTL1) • CSIBn control register 2 (CBnCTL2) • CSIBn status register (CBnSTR) CSIBn control register 0 (CBnCTL0) The CBnCTL0 register is a register that controls the CSIB serial transfer operation.
Page 650 Chapter 16 Clocked Serial Interface B (CSIB) Figure 16-4: CSIBn Control Register 0 (CBnCTL0) (2/2) Note Transfer Direction Selection CBnDIR MSB-first transfer LSB-first transfer Slave Selection Operation Enable Note CBnSSE Slave selection function disabled Slave selection function enabled When the CSIBn serves as slave, it executes transmission/reception in synchronization with the clock only when a low level is input to the SSBn pin.
Page 651: Figure 16-5: Csibn Control Register 1 (Cbnctl1)
Chapter 16 Clocked Serial Interface B (CSIB) CSIBn control register 1 (CBnCTL1) The CBnCTL1 register is an 8-bit register that controls the CSIB serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Caution: The CBnCTL1 register can be rewritten when the CBnPWR bit of the CBnCTL0 register is 0 or when both the CBnTXE and CBnRXE bits are 0.
Page 652: Figure 16-6: Csibn Control Register 2 (Cbnctl2)
Chapter 16 Clocked Serial Interface B (CSIB) CSIBn control register 2 (CBnCTL2) The CBnCTL2 register is an 8-bit register that controls the number of CSIB serial transfer bits. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Caution: The CBnCTL2 register can be rewritten only when the CBnPWR bit of the CBnCTL0 register is 0 or when both the CB0TXE and CB0RXE bits are 0.
Page 653: Figure 16-7: Effect Of Transfer Data Length Setting
Chapter 16 Clocked Serial Interface B (CSIB) (a) Transfer data length function The CSIB transfer data length can be set in 1-bit units between 8 and 16 bits using bits CBnCL3 to CBnCL0 of the CBnCTL2 register. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
Page 654: Figure 16-8: Csibn Status Register (Cbnstr)
Chapter 16 Clocked Serial Interface B (CSIB) CSIBn status register (CBnSTR) The CBnSTR register is an 8-bit register that displays the CSIB status. This register can be read or written in 8-bit or 1-bit units, but the CBnSTF flag is a read-only. Reset input clears this register to 00H.
Page 655: Operation
Chapter 16 Clocked Serial Interface B (CSIB) 16.4 Operation 16.4.1 Single transfer mode (master mode, transmission/reception mode) Figure 16-9: Single Transfer Mode (Master Mode, Transmission/Reception Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 0, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) CBnTX register write (55H)
Page 656: Single Transfer Mode (Master Mode, Transmission Mode)
Chapter 16 Clocked Serial Interface B (CSIB) 16.4.2 Single transfer mode (master mode, transmission mode) Figure 16-10: Single Transfer Mode (Master Mode, Transmission Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 0, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) CBnTX register write (55H)
Page 657: Single Transfer Mode (Master Mode, Reception Mode)
Chapter 16 Clocked Serial Interface B (CSIB) 16.4.3 Single transfer mode (master mode, reception mode) Figure 16-11: Single Transfer Mode (Master Mode, Reception Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 0, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) CBnRX register read (55H)
Page 658: Continuous Mode (Master Mode, Transmission/Reception Mode)
Chapter 16 Clocked Serial Interface B (CSIB) 16.4.4 Continuous mode (master mode, transmission/reception mode) Figure 16-12: Continuous Mode (Master Mode, Transmission/Reception Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 1, CBnDAP Bit of the CBnCTL1 Register = 0, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) CBnTX register...
Page 659: Continuous Mode (Master Mode, Transmission Mode)
Chapter 16 Clocked Serial Interface B (CSIB) 16.4.5 Continuous mode (master mode, transmission mode) Figure 16-13: Continuous Mode (Master Mode, Transmission Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 0, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) SCKBn pin SOBn pin...
Page 660: Continuous Mode (Master Mode, Reception Mode)
Chapter 16 Clocked Serial Interface B (CSIB) 16.4.6 Continuous mode (master mode, reception mode) Figure 16-14: Continuous Mode (Master Mode, Reception Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 1, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) SCKBn pin CBnSCE bit...
Page 661: Continuous Reception Mode (Error)
Chapter 16 Clocked Serial Interface B (CSIB) 16.4.7 Continuous reception mode (error) Figure 16-15: Continuous Reception Mode (Error) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 1, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) SCKBn pin SIBn pin...
Page 662: Continuous Mode (Slave Mode, Transmission/Reception Mode)
Chapter 16 Clocked Serial Interface B (CSIB) 16.4.8 Continuous mode (slave mode, transmission/reception mode) Figure 16-16: Continuous Mode (Slave Mode, Transmission/Reception Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 1, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) CBnTX register...
Page 663: Continuous Mode (Slave Mode, Reception Mode)
Chapter 16 Clocked Serial Interface B (CSIB) 16.4.9 Continuous mode (slave mode, reception mode) Figure 16-17: Continuous Mode (Slave Mode, Reception Mode) MSB First (CBnDIR Bit of CBnCTL0 Register = 0), CBnCKP Bit of the CBnCTL1 Register = 0, CBnDAP Bit of the CBnCTL1 Register = 0, Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B) SCKBn pin SIBn pin...
Page 664: Clock Timing
Chapter 16 Clocked Serial Interface B (CSIB) 16.4.10 Clock timing Figure 16-18: CSIBn Clock Timing (1/2) (a) CBnCKP = 0, CBnDAP = 0 SCKBn pin SIBn capture SOBn pin Reg-R/W INTCBnT interrupt INTCBnR interrupt CBnTSF bit (b) CBnCKP = 1, CBnDAP = 0 SCKBn pin SIBn capture...
Page 665 Chapter 16 Clocked Serial Interface B (CSIB) Figure 16-18: CSIBn Clock Timing (2/2) (c) CBnCKP = 0, CBnDAP = 1 SCKBn pin SIBn capture SOBn pin Reg-R/W INTCBnT interrupt INTCBnR interrupt CBnTSF bit (d) CBnCKP = 1, CBnDAP = 1 SCKBn pin SIBn capture...
Page 666: Output Pins
Chapter 16 Clocked Serial Interface B (CSIB) 16.5 Output Pins SCKBn pin When CSIBn operation is disabled (CBnPWR bit of CBnCTL0 register = 0), the SCKBn pin output status is as follows. CBnCKP SCKBn Pin Output Fixed to high level Fixed to low level Remarks: 1.
Page 667: Operation Flow
Chapter 16 Clocked Serial Interface B (CSIB) 16.6 Operation Flow Single transmission Figure 16-19: Operation Flow of Single Transmission START Note Initial settings (CBnCTL0 CBnCTL1 registers etc.) CBnTX register write (Transfer start) INTCBnR = 1 Transfer data exists? Note: Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings. μPD70F3187: n = 0, 1 Remark: μPD70F3447: n = 0...
Page 668: Figure 16-20: Operation Flow Of Single Reception (Master)
Chapter 16 Clocked Serial Interface B (CSIB) Single reception (master) Figure 16-20: Operation Flow of Single Reception (Master) START Note Initial settings (CBnCTL0 CBnCTL1 registers etc.) Dummy read of CBnRX register INTCBnR = 1 Last data? CBnCTL0.CBnSCE bit = 0 CBnRX register read CBnRX register read CBnCTL0.CBnSCE bit = 1...
Page 669: Figure 16-21: Operation Flow Of Single Reception (Slave)
Chapter 16 Clocked Serial Interface B (CSIB) Single reception (slave) Figure 16-21: Operation Flow of Single Reception (Slave) START Note Initial settings (CBnCTL0 CBnCTL1 registers etc.) Dummy read of CBnRX register INTCBnR = 1 CBnRX register read Last data? Note: Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings. μPD70F3187: n = 0, 1 Remark: μPD70F3447: n = 0...
Page 670: Figure 16-22: Operation Flow Of Continuous Transmission
Chapter 16 Clocked Serial Interface B (CSIB) Continuous transmission Figure 16-22: Operation Flow of Continuous Transmission START Note Initial settings (CBnCTL0 CBnCTL1 registers etc.) CBnTX register write (transfer start) INTCBnT = 1 Data to be transferred next exists? Note: Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings. Remarks: 1.
Page 671: Figure 16-23: Operation Flow Of Continuous Reception (Master)
Chapter 16 Clocked Serial Interface B (CSIB) Continuous reception (master) Figure 16-23: Operation Flow of Continuous Reception (Master) START Note Initial settings (CBnCTL0 CBnCTL1 registers etc.) Dummy read of CBnRX register INTCBnR = 1 Data currently received = last data? CBnCTL0.CBnSCE bit = 0 CBnRX register read CBnRX register read...
Page 672: Figure 16-24: Operation Flow Of Continuous Reception (Slave)
Chapter 16 Clocked Serial Interface B (CSIB) Continuous reception (slave) Figure 16-24: Operation Flow of Continuous Reception (Slave) START Note Initial settings (CBnCTL0 CBnCTL1 registers etc.) Dummy read of CBnRX register INTCBnR = 1 CBnRX register read Last data? Note: Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings. Remarks: 1.
Page 673: Baud Rate Generator
Chapter 16 Clocked Serial Interface B (CSIB) 16.7 Baud Rate Generator 16.7.1 Configuration Figure 16-25: Block Diagram of Baud Rate Generators 0 and 1 (BRG0, BRG1) f /8 f /16 8-bit Counter f /32 BRGOUTm Output f /64 Control INTBRGm PRSCMm The baud rate generators 0 and 1 (BRG0, BRG1) and CSIB0 and CSIB1 are connected as shown in the following block diagram.
Page 674: Control Registers
Chapter 16 Clocked Serial Interface B (CSIB) 16.7.2 Control registers Prescaler mode registers 0 and 1 (PRSM0, PRSM1) The PRSMm register controls generation of a baud rate signal for CSIB (m = 0, 1). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 675: Figure 16-28: Prescaler Compare Registers 0 And 1 (Prscm0, Prscm1)
Chapter 16 Clocked Serial Interface B (CSIB) Prescaler compare registers 0 and 1 (PRSCM0, PRSCM1) The PRSCMm register is an 8-bit compare register (m = 0, 1). This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 16-28: Prescaler Compare Registers 0 and 1 (PRSCM0, PRSCM1) After reset: Address:...
Page 676: Baud Rate Generation
Chapter 16 Clocked Serial Interface B (CSIB) 16.7.3 Baud rate generation The transmission/reception clock is generated by dividing the main clock. The baud rate generated from the main clock is obtained by the following equation. BGCSm -------------------- ------------------------- - × BRGm ×...
Page 677: Chapter 17 Clocked Serial Interface 3 (Csi3)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.1 Features • Transfer rate: Maximum 8 Mbps • Master mode and slave mode selectable • Serial clock and data phase switchable • Transmission data length: 8 to 16 bits (selectable in 1-bit units) •...
Page 678: Configuration
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.2 Configuration CSI3n is controlled by the clocked serial interface mode register 3n (CSIM3n). Clocked serial interface mode register 3n (CSIM3n) The CSIM3n register is an 8-bit register for specifying the operation of CSI3n. Clocked serial interface clock select register 3n (CSIC30, CSIC31) The CSIC3n register is an 8-bit register for controlling the operation clock and operating mode of CSI3n.
Page 679: Figure 17-1: Block Diagram Of Clocked Serial Interface 3N (Csi3N)
Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-1: Block Diagram of Clocked Serial Interface 3n (CSI3n) CSIBUF status Chip Select CSI buffer Transmit data CSI buffer INTC3nOVF register 3n (SFA3n) register 3n (SFCS3n) register 3n (SFDB3n) Transfer data control SCS3n0 CSI data buffer register n (CSIBUFn)
Page 680: Control Registers
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.3 Control Registers Clocked serial interface mode registers 3n (CSIM3n) The CSIM3n register controls the operation of CSI3n (n = 0, 1). This registers can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H.
Page 681 Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-2: Clocked Serial Interface Mode Register 3n (CSIM3n) (2/2) TRMDn Transfer Mode Specification Single mode Consecutive mode DIRn Transfer Direction Specification MSB-first transfer LSB-first transfer Specifies the transfer direction when data is written from the SFDB3n register to the CSIBUFn register or read from the SIRB3n and CSIBUFn registers.
Page 682: Figure 17-3: Clocked Serial Interface Clock Select Register 3N (Csic3N) (1/3)
Chapter 17 Clocked Serial Interface 3 (CSI3) Clocked serial interface clock select register 3n (CSIC3n) The CSIC3n register is an 8-bit register that controls the operation clock and operating mode of CSI3n. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 07H.
Page 683 Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-3: Clocked Serial Interface Clock Select Register 3n (CSIC3n) (2/3) CKPn DAPn Specification of Data Transmission/Reception Timing in Relation to Clock Phase SCK3n (I/O) SO3n (output) SI3n capture SCK3n (I/O) SO3n (output) SI3n capture Note SCK3n (I/O)
Page 684 Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-3: Clocked Serial Interface Clock Select Register 3n (CSIC3n) (3/3) CKS3n2 CKS3n1 CKS3n0 Set Value Basic Clock (f Mode XCLK Master mode Master mode Master mode Master mode Master mode Master mode Master mode –...
Page 685: Figure 17-4: Receive Data Buffer Register 3N (Sirb3N, Sirb3Nl, Sirb3Nh)
Chapter 17 Clocked Serial Interface 3 (CSI3) Receive data buffer register 3n (SIRB3n, SIRB3nL, SIRB3nH) The SIRB3n register is a 16-bit buffer register that stores receive data. It is overlayed by an 8-bit buffer register SIRB3nL on the lower 8 bits, and an 8-bit buffer register SIRB3nH on the higher 8 bits.
Page 686: Figure 17-5: Chip Select Csi Buffer Register 3N (Sfcs3N, Sfcs3Nl)
Chapter 17 Clocked Serial Interface 3 (CSI3) Chip select CSI buffer register 3n (SFCS3n, SFCS3nL) The SFCS3n register is a 16-bit buffer register that stores transmit data. It is overlayed by an 8-bit buffer register SFCS3nL on the lower 8 bits. When chip select data is written to the SFCS3n (SFCS3nL) register, the data is stored in the CSIBUFn register following the CSIBUFn pointer for writing.
Page 687: Figure 17-6: Transmit Data Csi Buffer Register 3N (Sfdb3N, Sfdb3Nl, Sfdb3Nh)
Chapter 17 Clocked Serial Interface 3 (CSI3) Transmit data CSI buffer register 3n (SFDB3n, SFDB3nL, SFDB3nH) The SFDB3n register is a 16-bit buffer register that stores transmit data. It is overlayed by an 8-bit buffer register SFDB3nL on the lower 8 bits, and an 8-bit buffer register SFDB3nH on the higher 8 bits.
Page 688: Figure 17-7: Csibuf Status Register 3N (Sfa3N)(1/3)
Chapter 17 Clocked Serial Interface 3 (CSI3) CSIBUF status register 3n (SFA3n) The SFA3n register indicates the status of the CSIBUFn register or the transfer status. This register can be read or written in 8-bit or 1-bit units (however, bits 6 to 0 can only be read. They do not change even if they are written).
Page 689 Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-7: CSIBUF Status Register 3n (SFA3n)(2/3) SFFULn CSIBUFn Full Status Flag CSIBUFn register has a vacancy CSIBUFn is full Cautions: 1. This bit is cleared to 0 when the CSICAEn bit of the CSIM3n register is cleared to 0 and the FPCLR bit is set to 1.
Page 690 Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-7: CSIBUF Status Register 3n (SFA3n)(3/3) SFPn3 SFPn2 SFPn1 SFPn0 CSIBUFn Pointer Status 0H to FH • In the single mode (TRMDn bit of the CSIM3n (0 to 15) register = 0), the “number of transfer data remaining in CSIBUFn register (CSIBUFn pointer value for writing –...
Page 691: Figure 17-8: Transfer Data Length Select Register 3N (Csil3N)
Chapter 17 Clocked Serial Interface 3 (CSI3) Transfer data length select register 3n (CSIL3n) The CSIL3n register is used to select the transfer data length of CSI3n. This register can be read or written in 8-bit or 1-bit units. Reset input clears the register to 00H. Caution: The CSIL3n register may be transferring data when the CTXEn or CRXEn bit of the CSIM3n register is 1.
Page 692: Figure 17-9: Transfer Data Number Specification Register 3N (Sfn3N)
Chapter 17 Clocked Serial Interface 3 (CSI3) Transfer data number specification register 3n (SFN3n) The SFN3n register is used to set the number of transfer data of CSI3n in the consecutive mode (TRMDn bit of the CSIM3n register = 1). This register can be read or written in 8-bit or 1-bit units.
Page 693: Dedicated Baud Rate Generator 3N (Brg3N)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.4 Dedicated Baud Rate Generator 3n (BRG3n) The transfer clock of CSI3n can be selected from the output of a dedicated baud rate generator (BRG3n) or external clock (n = 0, 1). The serial clock source is specified by the CSIC3n register. In the master mode (CKS3n2 to CKS3n0 bits of the CSIC3n register other than 111B), BRG3n is selected as the clock source.
Page 694 Chapter 17 Clocked Serial Interface 3 (CSI3) Baud rate The baud rate is calculated by the following expression. --------------------------- - [bps] Baud rate × Remarks: 1. f : Main clock Value set by CKS3n2 to CKS3n0 bits of CSIC3n register (0 ≤ k ≤ 6) 2.
Page 695: Operation
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5 Operation 17.5.1 Operation modes Table 17-1: Operation Modes TRMDn Bit CKS3n2 to CTXEn and DIRn Bit CSITn Bit CSWEn Bit CSMDn Bit CKS3n0 Bits CRXEn Bits Single mode Master mode Transmission/ MSB/LSB INTC3n delay Transfer wait Intermediate...
Page 696: Function Of Csi Data Buffer Register (Csibufn)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.2 Function of CSI data buffer register (CSIBUFn) By consecutively writing the transmit data to the SFCS3n register and the SFDB3n register from where it is transferred, the data can be stored in the CSIBUFn register while the CSIBUFn pointer for writing is automatically incremented (the CSIBUFn register size is 20 bits ×...
Page 697: Data Transfer Direction Specification Function
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.3 Data transfer direction specification function The data transfer direction can be changed by using the DIRn bit of the CSIM3n register (n = 0, 1). MSB first (DIRn bit = 0) Figure 17-12: Data Transfer Direction Specification (MSB first) (a) Transfer direction: MSB first, Transfer data length: 8 Bits SCK3n (I/O) SI3n (input)
Page 698: Figure 17-13: Data Transfer Direction Specification (Lsb First)
Chapter 17 Clocked Serial Interface 3 (CSI3) LSB first (DIRn bit = 1) Figure 17-13: Data Transfer Direction Specification (LSB first) (a) Transfer direction: LSB first, Transfer data length: 8 Bits SCK3n (I/O) SI3n (input) SO3n (output) (b) Writing from SFDB3n register to CSIBUFn register SFDB3n CSIBUFn Data...
Page 699: Transfer Data Length Changing Function
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.4 Transfer data length changing function The transfer data length can be set from 8 to 16 bits in 1-bit units, by using the CCLn3 to CCLn0 bits of the CSIL3n register (n = 1, 0). Figure 17-14: Transfer Data Length Changing Function Transfer Data Length: 16 Bits (CCLn3 to CCLn0 Bits of CSIL3n Register = 0000B), Transfer Direction: MSB First (DIRn Bit of CSIM3n Register = 0)
Page 700: Function To Select Serial Clock And Data Phase
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.5 Function to select serial clock and data phase The serial clock and data phase can be changed by using the CKPn and DAPn bits of the CSIC3n register (n = 0, 1). Figure 17-15: Clock Timing (a) When CKPn bit = 0, DAPn bit = 0 SCK3n...
Page 701: Master Mode
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.6 Master mode The master mode is set and data is transferred with the transfer clock output to the SCK3n pin when the CKS3n2 to CKS3n0 bits of the CSIC3n register are set to a value other than 111B (SCK3n pin input is invalid) (n = 0, 1).
Page 702: Slave Mode
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.7 Slave mode The slave mode is set when the CKS3n2 to CKS3n0 bits of the CSIC3n register are set to 111B, and data is transferred with the transfer clock input to the SCK3n pin (in the slave mode, it is recommended to set the MDLn2 to MDLn0 bits of the CSIC3n register to 000B and set the BRGn stop mode) (n = 0, 1).
Page 703: Transfer Clock Selection Function
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.8 Transfer clock selection function In the master mode (CKS3n2 to CKS3n0 bits of the CSIC3n register other than 111B), the bit transfer rate can be selected by setting the CKS3n2 to CKS3n0 and MDLn2 to MDLn0 bits of the CSIC3n register (ref.
Page 704: Figure 17-18: Single Mode
Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-18: Single Mode CSI data buffer register n (CSIBUFn) Write Incremented CSIBUFn pointer CS data 4 Transfer data 4 Note SCS3n0 CS data 3 Transfer data 3 Chip SIO3n load SCS3n1 CS data 2 Transfer data 2 select Incremented...
Page 705: Consecutive Mode
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.10 Consecutive mode The consecutive mode is set when the TRMDn bit of the CSIM3n register is 1 (μPD70F3187: n = 0, 1, μPD70F3447: n = 0). In this mode, transfer is started when the CTXEn bit or CRXEn bit is 1 and when data is in the CSIBUFn register (SFEMPn bit of the SFA3n register = 0).
Page 706: Figure 17-19: Consecutive Mode
Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-19: Consecutive Mode CSI data buffer register n (CSIBUFn) Write Incremented CSIBUFn pointer Note SCS3n0 CS data 3 Transfer data 3 Chip SIO3n load/store SCS3n1 CS data 2 Transfer data 2 select Incremented CSIBUFn pointer output...
Page 707: Transmission Mode
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.11 Transmission mode The transmission mode is set when the CTXEn bit of the CSIM3n register is set to 1 and the CRXEn bit is cleared to 0. In this mode, transmission is started by a trigger that writes transmit data to the SFDB3n register or sets the CTXEn bit to 1 when transmit data is in the SFDB3n register (n = 0, 1).
Page 708: Delay Control Of Transmission/Reception Completion Interrupt (Intc3N)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.14 Delay control of transmission/reception completion interrupt (INTC3n) In the master mode (CKS3n2 to CKS3n0 bits of the CSIC3n register other than 111B), occurrence of the transmission/reception completion interrupt (INTC3n) can be delayed by half a clock (1/2 serial clock), depending on the setting of the CSITn bit of the CSIM3n register (CSITn bit = 1).
Page 709: Transfer Wait Function
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.15 Transfer wait function In the master mode (CKS3n2 to CKS3n0 bits of the CSIC3n register other than 111B), starting transfer can be delayed by one clock, depending on the setting of the CSWEn bit of the CSIM3n register (CSWEn bit = 1).
Page 710 Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-21: Transfer Wait Function (2/3) (b) Transfer Wait Enabled (CSWEn Bit = 1), INTC3n Delay Disabled (CSITn Bit = 0), CKPn and DAPn Bits = 00B, Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B), Intermediate Inactive Chip Select Level Enabled (CSMDn = 1) Wait SCK3n (output)
Page 711 Chapter 17 Clocked Serial Interface 3 (CSI3) Figure 17-21: Transfer Wait Function (3/3) (c) Transfer Wait Enabled (CSWEn Bit = 1), INTC3n Delay Enabled (CSITn Bit = 1), CKPn and DAPn Bits = 00B, Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B), Intermediate Inactive Chip Select Level Disabled (CSMDn = 0) Delay Wait...
Page 712: Output Pins
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.5.16 Output pins SCK3n pin The SCK3n pin outputs a high level when both the CTXEn and CRXEn bits of the CSIM3n register are 0 (n = 0, 1). In the master mode (CKS3n2 to CKS3n0 bits = other than 111 in the CSIC3n register), this pin outputs the default level when the FPCLRn bit of the SFA3n register is set to 1.
Page 713: Csibufn Overflow Interrupt Signal (Intc3Novf)
Chapter 17 Clocked Serial Interface 3 (CSI3) SCS3n0 to SCS3n3 pins The SCS3n0 to SCS3n3 pins output the default level when both the CTXEn and CRXEn bits of the CSIM3n register are 0, or when the CSICAEn bit of the CSIM3n register is cleared to 0 (n = 0, 1). These pins output the default level when the FPCLRn bit of the SFA3n register is set to 1.
Page 714: Operating Procedures
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6 Operating Procedures 17.6.1 Single mode (master mode, transmission mode) Figure 17-22: Single Mode (Master Mode, Transmission Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 0 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Page 715 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. <2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <4>...
Page 716: Single Mode (Master Mode, Reception Mode)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.2 Single mode (master mode, reception mode) Figure 17-23: Single Mode (Master Mode, Reception Mode) MSB First (DIR bit = 0), CKP bit = 1, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Page 717 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. <2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <4>...
Page 718: Single Mode (Master Mode, Transmission/Reception Mode)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.3 Single mode (master mode, transmission/reception mode) Figure 17-24: Single Mode (Master Mode, Transmission/Reception Mode) MSB First (DIR bit = 0), CKP bit = 1, DAP bit = 0 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Page 719 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. <2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <4>...
Page 720: Single Mode (Slave Mode, Transmission Mode)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.4 Single mode (slave mode, transmission mode) Figure 17-25: Single Mode (Slave Mode, Transmission Mode) MSB First (DIR bit = 0), CKP bit = 1, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Page 721 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. <2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <4>...
Page 722: Single Mode (Slave Mode, Reception Mode)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.5 Single mode (slave mode, reception mode) Figure 17-26: Single Mode (Slave Mode, Reception Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 0 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Page 723 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. <2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <4>...
Page 724: Single Mode (Slave Mode, Transmission/Reception Mode)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.6 Single mode (slave mode, transmission/reception mode) Figure 17-27: Single Mode (Slave Mode, Transmission/Reception Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Page 725 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. <2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <4>...
Page 726: Consecutive Mode (Master Mode, Transmission Mode)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.7 Consecutive mode (master mode, transmission mode) Figure 17-28: Consecutive Mode (Master Mode, Transmission Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 0 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Page 727 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. <2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <4>...
Page 728: Consecutive Mode (Master Mode, Reception Mode)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.8 Consecutive mode (master mode, reception mode) Figure 17-29: Consecutive Mode (Master Mode, Reception Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Page 729 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. <2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <4>...
Page 730: Consecutive Mode (Master Mode, Transmission/Reception Mode)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.9 Consecutive mode (master mode, transmission/reception mode) Figure 17-30: Consecutive Mode (Master Mode, Transmission/Reception Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Page 731 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. <2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <4>...
Page 732: Consecutive Mode (Slave Mode, Transmission Mode)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.10 Consecutive mode (slave mode, transmission mode) Figure 17-31: Consecutive Mode (Slave Mode, Transmission Mode) MSB First (DIR bit = 0), CKP bit = 1, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Page 733 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. <2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <4>...
Page 734: Consecutive Mode (Slave Mode, Reception Mode)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.11 Consecutive mode (slave mode, reception mode) Figure 17-32: Consecutive Mode (Slave Mode, Reception Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 0 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Page 735 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. <2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <4>...
Page 736: Consecutive Mode (In Slave Mode And Transmission/Reception Mode)
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.6.12 Consecutive mode (in slave mode and transmission/reception mode) Figure 17-33: Consecutive Mode (Slave Mode, Transmission/Reception Mode) MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 1 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B) INTC3n Interrupt Not Delayed (CSIT bit = 0), Transfer Wait: Disabled (CSWE bit = 0), Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Page 737 Chapter 17 Clocked Serial Interface 3 (CSI3) <1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled. <2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <4>...
Page 738: Cautions
Chapter 17 Clocked Serial Interface 3 (CSI3) 17.7 Cautions The following points must be observed when using CSI3n. Cautions: 1. The CSI3n unit is reset and CSI3n is stopped when the CSICAEn bit of the CSIM3n register is cleared to 0. To operate CSI3n, first set the CSICAEn bit to 1. Usually, before clearing the CSICAEn bit to 0, clear both the CTXEn and CRXEn bits to 0 (after the end of transfer).
Page 739: Chapter 18 Afcan Controller
Chapter 18 AFCAN Controller The V850E/PH2 microcontrollers feature an on-chip n-channel CAN (Controller Area Network) control- ler that complies with the CAN protocol as standardized in ISO 11898. The number of channels is given in the table below: µPD70F3447 uPD70F3187...
Page 740: Overview Of Functions
Chapter 18 AFCAN Controller 18.1.1 Overview of functions Table 18-1 presents an overview of the CAN Controller functions. Table 18-1: Overview of Functions Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Maximum 1 Mbps (CAN clock input ≥ 8 MHz) Baud rate Data storage Storing messages in the CAN RAM...
Page 741: Configuration
The CAN Controller is composed of the following four blocks. • NPB interface This functional block provides an NPB (NEC Peripheral I/O Bus) interface and means of transmitting and receiving signals between the CAN module and the host CPU. •...
Page 742: Can Protocol
Chapter 18 AFCAN Controller 18.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time commu- nication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer.
Page 743: Frame Types
Chapter 18 AFCAN Controller 18.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 18-2: Frame types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame...
Page 744: Figure 18-4: Remote Frame
Chapter 18 AFCAN Controller Remote frame A remote frame is composed of six fields. Figure 18-4: Remote Frame Remote frame <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Notes: 1.
Page 745: Figure 18-6: Arbitration Field (In Standard Format Mode)
Chapter 18 AFCAN Controller (b) Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Figure 18-6: Arbitration field (in standard format mode) Arbitration field (Control field) Identifier (r1) ID28 · · · · · · · · · · · · · · · · · · · · · · · · · · ID18 (11 bits) (1 bit) (1 bit)
Page 746: Figure 18-8: Control Field
Chapter 18 AFCAN Controller Table 18-4: Frame format setting (IDE bit) and number of identifier (ID) bits Frame Format SRR Bit IDE Bit Number of Bits Standard format mode None 0 (D) 11 bits Extended format mode 1 (R) 1 (R) 29 bits (c) Control field The control field sets “DLC”...
Page 747: Figure 18-9: Data Field
Chapter 18 AFCAN Controller (d) Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. Figure 18-9: Data field (Control field) Data field (CRC field) Data 0 Data 7 (8 bits)
Page 748: Figure 18-11: Ack Field
Chapter 18 AFCAN Controller (f) ACK field The ACK field is used to acknowledge normal reception. Figure 18-11: ACK field (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit) Note: D: Dominant = 0 R: Recessive = 1 •...
Page 749: Figure 18-13: Interframe Space (Error Active Node)
Chapter 18 AFCAN Controller (h) Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. • The bus state differs depending on the error status. –...
Page 750: Error Frame
Chapter 18 AFCAN Controller • Operation in error status Table 18-6: Operation in error status Error Status Operation Error active A node in this status can transmit immediately after a 3-bit intermission. Error passive A node in this status can transmit 8 bits after the intermission. 18.2.4 Error frame An error frame is output by a node that has detected an error.
Page 751: Overload Frame
Chapter 18 AFCAN Controller 18.2.5 Overload frame An overload frame is transmitted under the following conditions. • When the receiving node has not completed the reception operation • If a dominant level is detected at the first two bits during intermission •...
Page 752: Functions
Chapter 18 AFCAN Controller 18.3 Functions 18.3.1 Determining bus priority When a node starts transmission: • During bus idle, the node that output data first transmits the data. When more than one node starts transmission: • The node that consecutively outputs the dominant level for the longest from the first bit of the arbitra- tion field has the bus priority (if a dominant level and a recessive level are simultaneously transmit- ted, the dominant level is taken as the bus value).
Page 753: Multi Masters
Chapter 18 AFCAN Controller 18.3.3 Multi masters As the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus master. 18.3.4 Multi cast Although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes.
Page 754: Table 18-12: Output Timing Of Error Frame
Chapter 18 AFCAN Controller Output timing of error frame Table 18-12: Output timing of error frame Type Output Timing Bit error, stuff error, Error frame output is started at the timing of the bit following form error, ACK error the detected error. CEC error Error frame output is started at the timing of the bit following the ACK delimiter.
Page 755: Table 18-13: Types Of Error States
Chapter 18 AFCAN Controller Table 18-13: Types of error states Type Operation Value of Error Indication of Operation Specific to Error State Counter CnINFO Register Error active Transmission 0 to 95 TECS1, TECS0 = 00 Outputs an active error flag (6 consecutive dominant-level bits) on detection of the error.
Page 756: Table 18-14: Error Counter
Chapter 18 AFCAN Controller (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful trans- mission and reception. The error counter is updated immediately after error detection. Table 18-14: Error counter State Transmission error counter Reception error counter (TEC7 to TEC0 Bits)
Page 757 Chapter 18 AFCAN Controller Recovery from bus-off state When the CAN module is in the bus-off state, the CAN module permanently sets its output signals (CTXDn) to recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence. <1>...
Page 758: Figure 18-17: Recovery From Bus-Off State Through Normal Recovery Sequence
Chapter 18 AFCAN Controller Figure 18-17: Recovery from bus-off state through normal recovery sequence TEC > FFH »bus-off« »bus-off-recovery-sequence« »error-active« »error-passive« BOFF bit in CnINFO register <1> <2> OPMODE[2:0] in CnCTRL ≠ ≠ register (user writings) <3> OPMODE[2:0] in CnCTRL ≠...
Page 759: Baud Rate Control Function
Chapter 18 AFCAN Controller 18.3.7 Baud rate control function Prescaler The CAN controller has a prescaler that divides the clock (f ) supplied to CAN. This prescaler generates a CAN protocol layer basic system clock (f ) derived from the CAN module system clock (f ), and divided by 1 to 256 (“CnBRP - CANn module bit rate prescaler register”...
Page 760: Figure 18-19: Configuration Of Data Bit Time Defined By Can Specification
Chapter 18 AFCAN Controller Figure 18-19: Configuration of data bit time defined by CAN specification Data bit time(DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 Sample point (SPT) Table 18-16: Configuration of data bit time defined by CAN specification Segment name Settable range Notes on setting to conform to CAN specification...
Page 761: Figure 18-20: Adjusting Synchronization Of Data Bit
Chapter 18 AFCAN Controller Synchronizing data bit • The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. • The transmitting node transmits data in synchronization with the bit timing of the transmitting node. (a) Hardware synchronization This synchronization is established when the receiving node detects the start of frame in the inter- frame space.
Page 762: Figure 18-21: Re-Synchronization
Chapter 18 AFCAN Controller (b) Re-synchronization Synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). • The phase error of the edge is given by the relative position of the detected edge and sync segment. <Sign of phase error>...
Page 763: Connection With Target System
Chapter 18 AFCAN Controller 18.4 Connection with Target System The CAN module has to be connected to the CAN bus using an external transceiver. Figure 18-22: Connection to CAN bus CTxDn CANL CAN module Transceiver CRxDn CANH User’s Manual U16580EE3V1UD00...
Page 764: Internal Registers Of Can Controller
Chapter 18 AFCAN Controller 18.5 Internal Registers of CAN Controller 18.5.1 CAN module register and message buffer addresses In this chapter all register and message buffer addresses are defined as address offsets to different base addresses. Since all registers are accessed via the programmable peripheral area the bottom address is defined by the BPC register (refer to <Peripheral-IO-Reference>...
Page 765: Can Controller Configuration
Chapter 18 AFCAN Controller 18.5.2 CAN Controller configuration Table 18-18: List of CAN Controller registers Item Register Name CAN global registers CANn global control register (CnGMCTRL) CANn global clock selection register (CnGMCS) CANn global automatic block transmission control register (CnGMABT) CANn global automatic block transmission delay setting register (CnGMABTD) CAN module registers CANn module mask 1 register (CnMASK1L, CnMASK1H)
Page 766: Can Registers Overview
Chapter 18 AFCAN Controller 18.5.3 CAN registers overview CAN module #n registers The following table lists the address offsets to the CAN #n register base address: CnRBaseAddr Table 18-19: CAN0 global and module registers Address off- Register name Symbol Access After reset 1-bit 8-bit...
Page 767: Register Bit Configuration
Chapter 18 AFCAN Controller Table 18-20: CAN0 message buffer registers Address offset Register name Symbol Access After reset 1-bit 8-bit √ mx20 CAN #n message data byte 01 register m CnMDATA01m Undefined √ mx20 CAN #n message data byte 0 register m CnMDATA0m Undefined √...
Page 768: Table 18-22: Can Module Register Bit Configuration
Chapter 18 AFCAN Controller Table 18-22: CAN module register bit configuration (1/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 Note offset CnMASK1L CMID7 to CMID0 CMID15 to CMID8 CnMASK1H CMID23 to CMID16 CMID28 to CMID24 CnMASK2L...
Page 769 Chapter 18 AFCAN Controller Table 18-22: CAN module register bit configuration (2/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 Note offset CnRGPT (W) Clear ROVF CnRGPT (R) RHPM ROVF RGPT7 to RGPT0 F62H CnLOPT...
Page 770: Table 18-23: Message Buffer Register Bit Configuration
Chapter 18 AFCAN Controller Table 18-23: Message buffer register bit configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 Note offset CnMDATA01m Message data (byte 0) Message data (byte 1) CnMDATA0m Message data (byte 0) CnMDATA1m...
Page 771: Bit Set/Clear Function
Chapter 18 AFCAN Controller 18.6 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.
Page 772 Chapter 18 AFCAN Controller Bit Status After Bit Setting/Clearing Operations Clear Clear Clear Clear Clear Clear Clear Clear Set 7 Set 6 Set 5 Set 4 Set 3 Set 2 Set 1 Set 0 Set 0 ... 7 Clear 0 ... 7 Status of bit n after bit set/clear operation No change No change...
Page 773: Control Registers
Chapter 18 AFCAN Controller 18.7 Control Registers CnGMCTRL - CANn global control register The CnGMCTRL register is used to control the operation of the CAN module. After reset: 0000H Address: <CnRBaseAddr> + 000 (a) Read CnGMCTRL MBON EFSD MBON Bit enabling access to message buffer register, transmit/receive history registers Write access and read access to the message buffer register and the transmit/receive history list registers is disabled.
Page 774 Chapter 18 AFCAN Controller (b) Write CnGMCTRL EFSD Clear Set EFSD EFSD bit setting No change in EFSD bit. EFSD bit set to 1. Clear GOM bit setting GOM bit cleared to 0. GOM bit set to 1. Other than above No change in GOM bit.
Page 775 Chapter 18 AFCAN Controller CnGMCS - CANn global clock selection register The CnGMCS register is used to select the CAN module system clock. After reset: 0FH Address: <CnRBaseAddr> + 002 CnGMCS CCP3 CCP2 CCP1 CCP0 CCP3 CCP2 CCP1 CCP1 CAN module system clock (fCANMOD) /16 (Default value) Remark: = Clock supplied to CAN...
Page 776 Chapter 18 AFCAN Controller CnGMABT - CANn global automatic block transmission control register The CnGMABT register is used to control the automatic block transmission (ABT) operation. After reset: 0000H Address: <CnRBaseAddr> + 006 (a) Read CnGMABT ABTCLR ABTTRG ABTCLR Automatic block transmission engine clear status bit Clearing the automatic transmission engine is completed.
Page 777 Chapter 18 AFCAN Controller (b) Write CnGMABT ABTCLR ABTTRG Clear ABTTRG Caution: Before changing the normal operation mode with ABT to the initialization mode, be sure to set the CnGMABT register to the default value (0000H) and confirm the CnGMABT register is surely initialized to the default value (0000H). Set ABTCLR Automatic block transmission engine clear request bit The automatic block transmission engine is in idle status or under...
Page 778 Chapter 18 AFCAN Controller CnGMABTD - CANn global automatic block transmission delay register The CnGMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT. After reset: 00H Address: <CnRBaseAddr>...
Page 779 Chapter 18 AFCAN Controller CnMASKaL, CnMASKaH - CANn module mask control register (a = 1 to 4) The CnMASKaL and CnMASKaH registers are used to extend the number of receivable mes- sages into the same message buffer by masking part of the identifier (ID) comparison of a mes- sage and invalidating the ID of the masked part.
Page 780 Chapter 18 AFCAN Controller (d) CANn module mask 4 register (CnMASK4L, CnMASK4H) After reset: Undefined Address: CnMASK4L <CnRBaseAddr> + 04C CnMASK4H <CnRBaseAddr> + 04E CnMASK4L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 CnMASK4H CMID28...
Page 781 Chapter 18 AFCAN Controller CnCTRL - CANn module control register The CnCTRL register is used to control the operation mode of the CAN module. After reset: 0000H Address: CnCTRL <CnRBaseAddr> + 050 (a) Read CnCTRL RSTAT TSTAT PSMODE PSMODE OPMODE OPMODE OPMODE CCERC...
Page 782 Chapter 18 AFCAN Controller CCERC Error counter clear bit The CnERC and CnINFO registers are not cleared in the initialization mode. The CnERC and CnINFO registers are cleared in the initialization mode. Notes: 1. The CCERC bit is used to clear the CnERC and CnINFO registers for re-initialization or forced recovery from the bus-off state.
Page 783 Chapter 18 AFCAN Controller OPMODE2 OPMODE1 OPMODE0 Operation mode No operation mode is selected (CAN module is in the initialization mode). Normal operation mode Normal operation mode with automatic block transmission function (normal operation mode with ABT) Receive-only mode Single-shot mode Self-test mode Other than above Setting prohibited...
Page 784 Chapter 18 AFCAN Controller Clear Setting of PSMODE1 bit PSMODE1 PSMODE1 PSMODE1 bit is cleared to 0. PSMODE1 bit is set to 1. Other than above PSMODE1 bit is not changed. Clear Setting of OPMODE0 bit OPMODE0 OPMODE0 OPMODE0 bit is cleared to 0. OPMODE0 bit is set to 1.
Page 785 Chapter 18 AFCAN Controller CnLEC - CANn module last error information register The CnLEC register provides the error information of the CAN protocol. After reset: 00H Address: CnLEC <CnRBaseAddr> + 052 CnLEC LEC2 LEC1 LEC0 Notes: 1. The contents of the CnLEC register are not cleared when the CAN module changes from an operation mode to the initialization mode.
Page 786 Chapter 18 AFCAN Controller CnINFO - CANn module information register The CnINFO register indicates the status of the CAN module. After reset: 00H Address: CnINFO <CnRBaseAddr> + 053 CnINFO BOFF TECS1 TECS0 RECS1 RECS0 BOFF Bus-off state bit Not bus-off state (transmit error counter ≤ 255). (The value of the transmit counter is less than 256.) Bus-off state (transmit error counter >...
Page 787 Chapter 18 AFCAN Controller CnERC - CANn module error counter register The CnERC register indicates the count value of the transmission/reception error counter. After reset: 0000H Address: CnERC <CnRBaseAddr> + 054H CnERC REPS REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5...
Page 788 Chapter 18 AFCAN Controller (10) CnIE - CANn module interrupt enable register The CnIE register is used to enable or disable the interrupts of the CAN module. After reset: 0000H Address: CnIE <CnRBaseAddr> + 056 (a) Read CnIE CIE5 CIE4 CIE3 CIE2 CIE1...
Page 789 Chapter 18 AFCAN Controller Set CIE1 Clear CIE1 Setting of CIE1 bit CIE1 bit is cleared to 0. CIE1 bit is set to 1. Other than above CIE1 bit is not changed. Set CIE0 Clear CIE0 Setting of CIE0 bit CIE0 bit is cleared to 0.
Page 790 Chapter 18 AFCAN Controller (11) CnINTS - CANn module interrupt status register The CnINTS register indicates the interrupt status of the CAN module. After reset: 0000H Address: CnINTS <CnRBaseAddr> + 058 (a) Read CnINTS CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 CINTS5 to CINTS0 CAN interrupt status bit No related interrupt source event is pending.
Page 791: Figure 18-24: Can Module Clock
Chapter 18 AFCAN Controller (12) CnBRP - CANn module bit rate prescaler register The CnBRP register is used to select the CAN protocol layer basic system clock (f ). The commu- nication baud rate is set to the CnBTR register. After reset: FFH Address: CnBRP <CnRBaseAddr>...
Page 792: Figure 18-25: Data Bit Time
Chapter 18 AFCAN Controller (13) CnBTR - CANn module bit rate register The CnBTR register is used to control the data bit time of the communication baud rate. After reset: 370FH Address: CnBTR <CnRBaseAddr> + 05C CnBTR SJW1 SJW0 TSEG22 TSEG21 TSEG20 TSEG13...
Page 793 Chapter 18 AFCAN Controller TSEG13 TSEG12 TSEG11 TSEG10 Length of time segment 1 Setting prohibited Note Note 10TQ 11TQ 12TQ 13TQ 14TQ 15TQ 16TQ (default value) Note: This setting must not be made when the CnBRP register = 00H. Remark: TQ = 1/f : CAN protocol layer basic system clock) (14) CnLIPT - CANn module last in-pointer register...
Page 794 Chapter 18 AFCAN Controller (15) CnRGPT - CANn module receive history list register The CnRGPT register is used to read the receive history list. After reset: xx02H Address: CnRGPT <CnRBaseAddr> + 060 (a) Read CnRGPT RGPT7 RGPT6 RGPT5 RGPT4 RGPT3 RGPT2 RGPT1 RGPT0...
Page 795 Chapter 18 AFCAN Controller (16) CnLOPT - CANn module last out-pointer register The CnLOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last. After reset: Undefined Address: CnLOPT <CnRBaseAddr> + 062 CnLOPT LOPT7 LOPT6...
Page 796 Chapter 18 AFCAN Controller (17) CnTGPT - CANn module transmit history list register The CnTGPT register is used to read the transmit history list. After reset: xx02H Address: CnTGPT <CnRBaseAddr> + 064 (a) Read CnTGPT TGPT7 TGPT6 TGPT5 TGPT4 TGPT3 TGPT2 TGPT1 TGPT0...
Page 797 Chapter 18 AFCAN Controller Clear TOVF Setting of TOVF bit TOVF bit is not changed. TOVF bit is cleared to 0. (18) CnTS - CANn module time stamp register The CnTS register is used to control the time stamp function. After reset: 0000H Address: CnTS <CnRBaseAddr>...
Page 798 Chapter 18 AFCAN Controller (b) Write CnTS TSLOCK TSSEL TSEN Clear Clear Clear TSLOCK TSSEL TSEN Clear Setting of TSLOCK bit TSLOCK TSLOCK TSLOCK bit is cleared to 0. TSLOCK bit is set to 1. Other than above TSLOCK bit is not changed. Clear Setting of TSSEL bit TSSEL...
Page 799 Chapter 18 AFCAN Controller MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 CnMDATA01m MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA0 MDATA0 MDATA0 MDATA0 MDATA0 MDATA0 MDATA0 MDATA0 CnMDATA0m MDATA1 MDATA1 MDATA1 MDATA1 MDATA1 MDATA1 MDATA1 MDATA1 CnMDATA1m MDATA23 MDATA23 MDATA23 MDATA23...
Page 800 Chapter 18 AFCAN Controller MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 CnMDATA45m MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 CnMDATA4m MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 CnMDATA5m MDATA67 MDATA67 MDATA67 MDATA67...
Page 801 Chapter 18 AFCAN Controller (20) CnMDLCm - CANn message data length register m The CnMDLCm register is used to set the number of bytes of the data field of a message buffer. After reset: 0000xxxxB Address: refer to “CAN registers overview” on page 766 CnMDLCm MDLC3 MDLC2...
Page 802 Chapter 18 AFCAN Controller (21) CnMCONFm - CANn message configuration register m The CnMCONFm register is used to specify the type of the message buffer and to set a mask. After reset: Undefined Address: refer to “CAN registers overview” on page 766 CnMCONFm Overwrite control bit Note...
Page 803 Chapter 18 AFCAN Controller Message buffer assignment bit Message buffer not used. Message buffer used. Caution Be sure to write 0 to bits 2 and 1. (22) CnMIDLm, CnMIDHm - CANn message ID register m The CnMIDLm and CnMIDHm registers are used to set an identifier (ID). After reset: Undefined Address: refer to “CAN registers overview”...
Page 804 Chapter 18 AFCAN Controller (23) CnMCTRLm - CANn message control register m The CnMCTRLm register is used to control the operation of the message buffer. After reset: 00x000000 Address: refer to “CAN registers overview” on page 766 00000000B (a) Read CnMCTRLm Note Bit indicating that message buffer data is being updated...
Page 805 Chapter 18 AFCAN Controller Message buffer transmission request bit No message frame transmitting request that is pending or being transmitted is in the message buffer. The message buffer is holding transmission of a message frame pending or is transmitting a message frame. Message buffer ready bit The message buffer can be written by software.
Page 806 Chapter 18 AFCAN Controller Set TRQ Clear TRQ Setting of TRQ bit TRQ bit is cleared to 0. TRQ bit is set to 1. Other than above TRQ bit is not changed. Set RDY Clear RDY Setting of RDY bit RDY bit is cleared to 0.
Page 807: Can Controller Initialization
Chapter 18 AFCAN Controller 18.8 CAN Controller Initialization 18.8.1 Initialization of CAN module Before CAN module operation is enabled, the CAN module system clock needs to be determined by setting the CCP[3:0] bits of the CnGMCS register by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled.
Page 808: Transition From Initialization Mode To Operation Mode
Chapter 18 AFCAN Controller Figure 18-26: Setting transmission request (TRQ) to transmit message buffer after redefinition Redefinition completed Execute transmission? Wait for 1 bit of CAN data. Set TRQ bit Set TRQ bit = 1 Clear TRQ bit = 0 Cautions: 1.
Page 809: Resetting Error Counter Cnerc Of Can Module
Chapter 18 AFCAN Controller Figure 18-27: Transition to operation modes OPMODE[2:0] = 00H and CAN bus is busy. [Receive-only mode] OPMODE[2:0]=03H OPMODE[2:0] = 00H OPMODE[2:0] = 00H and CAN bus is busy. and CAN bus is busy. [Normal operation OPMODE[2:0] = 03H mode with ABT] [Single-shot mode] OPMODE[2:0]=02H...
Page 810: Message Reception
Chapter 18 AFCAN Controller 18.9 Message Reception 18.9.1 Message reception In all the operation modes, the complete message buffer area is analyzed to find a suitable buffer to store a newly received message. All message buffers satisfying the following conditions are included in that evaluation (RX-search process).
Page 811: Receive History List Function
Chapter 18 AFCAN Controller cidental data WR by CPU. Note the storage process may be disturbed (delayed) when the CPU accesses the message buffer. Figure 18-28: DN and MUC Bit Setting Period (for Standard ID Format) Recessive DATA0-DATA7 ACK EOF CAN std ID format Dominant (11)
Page 812: Figure 18-29: Receive History List
Chapter 18 AFCAN Controller If the LIPT pointer is incremented and matches the value of the RGPT pointer minus 1, the ROVF bit (receive history list overflow) of the CnRGPT register is set to 1. This indicates that the RHL is full of numbers of message buffers that have not been read.
Page 813: Mask Function
Chapter 18 AFCAN Controller 18.9.4 Mask function For any message buffer, which is used for reception, the assignment to one of four global reception masks (or no mask) can be selected. By using the mask function, the message ID comparison can be reduced by masked bits, herewith allowing the reception of several different IDs into one buffer.
Page 814: Multi Buffer Receive Block Function
Chapter 18 AFCAN Controller <3> Mask setting for CAN module 1 (mask 1) (Example) (Using CAN1 address mask 1 registers L and H (C1MASKL1 and C1MASKH1)) CMID2 CMID2 CMID2 CMID2 CMID2 CMID2 CMID2 CMID2 CMID2 CMID1 CMID1 CMID1 CMID1 CMID1 CMID1 CMID1 CMID1...
Page 815: Remote Frame Reception
Chapter 18 AFCAN Controller buffer is not the same, if the ID that is masked by the mask register matches, it is considered a matching ID and the buffer that has this ID is treated as the storage destination of a message. 5.
Page 816: Message Transmission
Chapter 18 AFCAN Controller 18.10 Message Transmission 18.10.1 Message transmission A message buffer with its TRQ bit set to 1 participates in the search for the most high-prioritized mes- sage when the following conditions are fulfilled. This behavior is valid for all operational modes. •...
Page 817: Transmit History List Function
Chapter 18 AFCAN Controller Priority Conditions Description 1 (high) Value of first 11 bits of ID The message frame with the lowest value represented by the first 11 [ID28 to ID18]: bits of the ID is transmitted first. If the value of an 11-bit standard ID is equal to or smaller than the first 11 bits of a 29-bit extended ID, the 11- bit standard ID has a higher priority than a message frame with a 29-bit extended ID.
Page 818 Chapter 18 AFCAN Controller a data frame or remote frame first can be checked. The LOPT pointer is utilized as a write pointer that indicates to what part of the THL a message buffer number is recorded. Any time a data frame or remote frame is transmitted, the corresponding message buffer number is recorded to the THL element indicated by the LOPT pointer.
Page 819: Automatic Block Transmission (Abt)
Chapter 18 AFCAN Controller Figure 18-31: Transmit history list Transmit history list(THL) Transmit history list(THL) Event: - CPU confirms TX completion of message buffer 6, 9 and 2 Message buffer 4 - TX completion of message Message buffer 3 Last out- buffer 3 and 4 message Message buffer 7...
Page 820: Transmission Abort Process
Chapter 18 AFCAN Controller the message buffer where ABT stopped, by setting the RDY and ABTTRG bits to 1 by software. To not resume transmission from the message buffer where ABT stopped, the internal ABT engine can be reset by setting the ABTCLR bit to 1 while ABT mode is stopped and the ABTTRG bit is cleared to 0. In this case, transmission is started from message buffer 0 if the ABTCLR bit is cleared to 0 and then the ABTTRG bit is set to 1.
Page 821: Remote Frame Transmission
Chapter 18 AFCAN Controller Transmission abort process except for ABT transmission in normal operation mode with automatic block transmission (ABT) The user can clear the ABTTRG bit of the CnGMABT register to 0 to abort a transmission request. After checking the ABTTRG bit of the CnGMABT register = 0, clear the TRQ bit of the CnMCTRLm register to 0.
Page 822: Power Saving Modes
Chapter 18 AFCAN Controller 18.11 Power Saving Modes 18.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN Controller to stand-by mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes. Release of the CAN sleep mode returns the CAN module to exactly the same operation mode from which the CAN sleep mode was entered.
Page 823 Chapter 18 AFCAN Controller predetermined timing. At this time, the CAN sleep mode request is not held pending and is ignored. • Even when initialization mode and sleep mode are not requested simultaneously (i.e the first request has not been granted while the second request is made), the request for initialization has priority over the sleep mode request.
Page 824: Can Stop Mode
Chapter 18 AFCAN Controller Releasing CAN sleep mode The CAN sleep mode is released by the following events: • When the CPU writes 00B to the PSMODE[1:0] bits of the CnCTRL register • A falling edge at the CAN reception pin (CRXDn) (i.e. the CAN bus level shifts from recessive to dominant) Caution Even if the falling edge belongs to the SOF of a receive message, this...
Page 825: Example Of Using Power Saving Modes
Chapter 18 AFCAN Controller Status in CAN stop mode The CAN module is in the following state after it enters the CAN stop mode. • The internal operating clock is stopped and the power consumption is minimized. • To wake up the CAN module from the CPU, data can be written to the PSMODE[1:0] bits of the CAN module control register (CnCTRL), but nothing can be written to other CAN module registers or bits.
Page 826 Chapter 18 AFCAN Controller – releases its power saving mode, – resumes supply of the internal clocks—including the clock to the CAN module—after the oscillation stabilization time has elapsed, and – starts instruction execution. • The CAN module is immediately released from the CAN sleep mode when clock supply is resumed, and returns to the normal operation mode (PSMODE = 00B).
Page 827: Interrupt Function
Chapter 18 AFCAN Controller 18.12 Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that cor- responds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register.
Page 828: Diagnosis Functions And Special Operational Modes
Chapter 18 AFCAN Controller 18.13 Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis functions or the operation of special CAN communication methods. 18.13.1 Receive-only mode The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and can be used for CAN bus analysis nodes.
Page 829: Single-Shot Mode
Chapter 18 AFCAN Controller operating in the receive-only mode, there is no ACK on the CAN bus. Due to the missing ACK, the transmitting node will transmit an active error flag, and repeat transmitting a message frame. The transmitting node becomes error passive after transmitting the message frame 16 times (assuming that the error counter was 0 in the beginning and no other errors have occurred).
Page 830: Receive/Transmit Operation In Each Operation Mode
Chapter 18 AFCAN Controller Figure 18-33: CAN module terminal connection in self-test mode CAN macro Fixed to the recessive level CTXDn CRXDn 18.13.4 Receive/Transmit Operation in Each Operation Mode The following table shows outline of the receive/transmit operation in each operation mode. Transmiss Transmissi Automatic...
Page 831: Time Stamp Function
Chapter 18 AFCAN Controller 18.14 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autono- mous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchro- nous and may have different frequencies).
Page 832: Baud Rate Settings
Chapter 18 AFCAN Controller 18.15 Baud Rate Settings 18.15.1 Baud rate setting conditions Make sure that the settings are within the range of limit values for ensuring correct operation of the CAN Controller, as follows. 5TQ ≤ SPT (sampling point) ≤ 17 TQ •...
Page 833: Table 18-3: Settable Bit Rate Combinations
Chapter 18 AFCAN Controller <~Reference>Table 18-3 shows the combinations of bit rates that satisfy the above conditions. Table 18-3: Settable bit rate combinations (1/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG1 TSEG2 unit (%) DBT length SEGMENT...
Page 834 Chapter 18 AFCAN Controller Table 18-3: Settable bit rate combinations (2/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG1 TSEG2 unit (%) DBT length SEGMENT SEGMENT SEGMENT1 SEGMENT2 [3:0] [2:0] 1010 70.6 1011 76.5 1100 82.4...
Page 835 Chapter 18 AFCAN Controller Table 18-3: Settable bit rate combinations (3/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG1 TSEG2 unit (%) DBT length SEGMENT SEGMENT SEGMENT1 SEGMENT2 [3:0] [2:0] 1000 83.3 1001 91.7 0101 63.6...
Page 836: Representative Examples Of Baud Rate Settings
Chapter 18 AFCAN Controller 18.15.2 Representative examples of baud rate settings <~Reference>Table 18-4 and <~Reference>Table 18-5 show representative examples of baud rate set- tings. Table 18-4: Representative examples of baud rate settings = 8 MHz) (1/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud...
Page 837 Chapter 18 AFCAN Controller Table 18-4: Representative examples of baud rate settings = 8 MHz) (2/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC PROP...
Page 838: Table 18-5: Representative Examples Of Baud Rate Settings (Fcanmod = 16 Mhz)
Chapter 18 AFCAN Controller Table 18-5: Representative examples of baud rate settings = 16 MHz) (1/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC PROP...
Page 839 Chapter 18 AFCAN Controller Table 18-5: Representative examples of baud rate settings = 16 MHz) (2/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC PROP...
Page 840: Operation Of Can Controller
Chapter 18 AFCAN Controller 18.16 Operation of CAN Controller The processing procedure for showing in this chapter is recommended processing procedure to oper- ate CAN controller. Develop the program referring to recommended processing procedure in this chapter. Figure 18-35: Initialization START CnGMCS register.
Page 841: Figure 18-36: Re-Initialization
Chapter 18 AFCAN Controller Figure 18-36: Re-initialization START START Clear Clear OPMODE OPMODE INIT mode? INIT mode? CnBRP register, CnBRP register, CnBTR register CnBTR register CnIE register CnIE register CnMASK register CnMASK register Initialize message buffers Initialize message buffers CnERC and CnINFO CnERC and CnINFO register clear? register clear?
Page 842: Figure 18-37: Message Buffer Initialization
Chapter 18 AFCAN Controller Figure 18-37: Message buffer initialization START START RDY = 1? RDY = 1? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? CnMCONFm register CnMCONFm register CnMIDHm register, CnMIDHm register, CnMIDLm register CnMIDLm register Transmit message buffer? Transmit message buffer? CnMDLCm register...
Page 843: Figure 18-38: Message Buffer Redefinition
Chapter 18 AFCAN Controller Figure 18-38: Message buffer redefinition START START Clear VALID bit Clear VALID bit RDY = 1? RDY = 1? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? RSTAT = 0 or RSTAT = 0 or VALID = 1? VALID = 1? Note1...
Page 844: Figure 18-39: Message Buffer Redefinition During Transmission
Chapter 18 AFCAN Controller Figure 18-39: Message Buffer Redefinition during Transmission <~Reference>Figure 18-39 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000B). START START Transmit abort process Transmit abort process Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Data frame...
Page 845: Figure 18-40: Message Transmit Processing
Chapter 18 AFCAN Controller Figure 18-40: Message transmit processing <~Reference>Figure 18-40 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000B) START START TRQ = 0? TRQ = 0? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Data frame...
Page 846: Figure 18-41: Abt Message Transmit Processing
Chapter 18 AFCAN Controller Figure 18-41: ABT Message transmit processing <~Reference>Figure 18-41 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000B) START START ABTTRG = 0? ABTTRG = 0? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Set CnMDATAxm register...
Page 847: Figure 18-42: Transmission Via Interrupt (Using Cnlopt Register)
Chapter 18 AFCAN Controller Figure 18-42: Transmission via interrupt (using CnLOPT register) START START Transmit completion Transmit completion Transmit completion interrupt processing interrupt processing interrupt processing Read CnLOPT register Read CnLOPT register Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Data frame Data frame...
Page 848: Figure 18-43: Transmission Via Interrupt (Using Cntgpt Register)
Chapter 18 AFCAN Controller Figure 18-43: Transmission via interrupt (using CnTGPT register) START START Transmit completion Transmit completion Transmit completion interrupt processing interrupt processing interrupt processing Read CnTGPT register Read CnTGPT register TOVF = 1? TOVF = 1? Clear TOVF bit Clear TOVF bit Clear RDY bit Clear RDY bit...
Page 849: Figure 18-44: Transmission Via Software Polling
Chapter 18 AFCAN Controller Figure 18-44: Transmission via software polling START START CINTS0 = 1? CINTS0 = 1? Clear CINTS0 bit Clear CINTS0 bit Read CnTGPT register Read CnTGPT register TOVF = 1? TOVF = 1? Clear TOVF bit Clear TOVF bit Clear RDY bit Clear RDY bit RDY = 0?
Page 850: Figure 18-45: Transmission Abort Processing (Except Normal Operation Mode With Abt)
Chapter 18 AFCAN Controller Figure 18-45: Transmission abort processing (Except Normal Operation Mode with ABT) START START Clear TRQ bit Clear TRQ bit Wait for 11 CAN data bits Wait for 11 CAN data bits Note Note TSTAT = 0? TSTAT = 0? Read CnLOPT register Read CnLOPT register...
Page 851 Chapter 18 AFCAN Controller START START Clear ABTTRG bit Clear ABTTRG bit ABTTRG = 0? ABTTRG = 0? Clear TRQ bit Clear TRQ bit Wait for 11 CAN data bits Wait for 11 CAN data bits TSTAT = 0? TSTAT = 0? Read CnLOPT register Read CnLOPT register Message buffer to...
Page 852: Figure 18-47: Transmission Abort Processing (Normal Operation Mode With Abt)
Chapter 18 AFCAN Controller <~Reference>Figure 18-47 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. Figure 18-47: Transmission abort processing (normal operation mode with ABT) START START TSTAT = 0? TSTAT = 0? Clear ABTTRG bit...
Page 853: Figure 18-48: Transmission Request Abort Processing (Normal Operation Mode With Abt)
Chapter 18 AFCAN Controller <~Reference>Figure 18-48 shows the processing to not skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. Figure 18-48: Transmission request abort processing (normal operation mode with ABT) START START Clear TRQ bit of message buffer...
Page 854: Figure 18-49: Reception Via Interrupt (Using Cnlipt Register)
Chapter 18 AFCAN Controller Figure 18-49: Reception via interrupt (using CnLIPT register) START START Generation of receive Generation of receive completion interrupt completion interrupt Read CnLIPT register Read CnLIPT register Clear DN bit Clear DN bit Read CnMDATAxm, CnMDLCm, Read CnMDATAxm, CnMDLCm, CnMIDLm, and CnMIDHm CnMIDLm, and CnMIDHm registers...
Page 855: Figure 18-50: Reception Via Interrupt (Using Cnrgpt Register)
Chapter 18 AFCAN Controller Figure 18-50: Reception via interrupt (using CnRGPT register) START START Generation of receive Generation of receive completion interrupt completion interrupt Read CnRGPT register Read CnRGPT register ROVF = 1? ROVF = 1? Clear ROVF bit Clear ROVF bit RHPM = 1? RHPM = 1? Clear DN bit...
Page 856: Figure 18-51: Reception Via Software Polling
Chapter 18 AFCAN Controller Figure 18-51: Reception via software polling START START CINTS1 = 1? CINTS1 = 1? Clear CINTS1 bit Clear CINTS1 bit Read CnRGPT register Read CnRGPT register ROVF = 1? ROVF = 1? Clear ROVF bit Clear ROVF bit RHPM = 1? RHPM = 1? Clear DN bit...
Page 857: Figure 18-52: Setting Can Sleep Mode/Stop Mode
Chapter 18 AFCAN Controller Figure 18-52: Setting CAN sleep mode/stop mode START (when PSMODE[1:0] = 00B) START (when PSMODE[1:0] = 00B) Set PSMODE0 bit Set PSMODE0 bit PSMODE0 = 1? PSMODE0 = 1? CAN sleep mode CAN sleep mode CAN sleep mode Set PSMODE1 bit Set PSMODE1 bit PSMODE1 = 1?
Page 858: Figure 18-53: Clear Can Sleep/Stop Mode
Chapter 18 AFCAN Controller Figure 18-53: Clear CAN sleep/stop mode START START CAN stop mode CAN stop mode Clear PSMODE1 bit Clear PSMODE1 bit CAN sleep mode CAN sleep mode Releasing CAN sleep mode Releasing CAN sleep mode by CAN bus activity by CAN bus activity Releasing CAN sleep mode Releasing CAN sleep mode...
Page 859: Figure 18-54: Bus-Off Recovery (Except Normal Operation Mode With Abt)
Chapter 18 AFCAN Controller Figure 18-54: Bus-Off recovery (Except Normal Operation Mode with ABT) START START BOFF = 1? BOFF = 1? Clear all TRQ bits Clear all TRQ bits Note Note Set CnCTRL register Set CnCTRL register (Clear OPMODE) (Clear OPMODE) Access to registers other than Access to registers other than...
Page 860: Figure 18-55: Bus-Off Recovery (Normal Operation Mode With Abt)
Chapter 18 AFCAN Controller Figure 18-55: Bus-Off recovery (Normal Operation Mode with ABT) START START BOFF = 1? BOFF = 1? Clear ABTTRG bit Clear ABTTRG bit Clear all TRQ bits Clear all TRQ bits Note Note Set CnCTRL register Set CnCTRL register (Clear OPMODE) (Clear OPMODE)
Page 861: Figure 18-56: Normal Shutdown Process
Chapter 18 AFCAN Controller Figure 18-56: Normal shutdown process START START INIT mode INIT mode Clear GOM bit Clear GOM bit GOM = 0? GOM = 0? Shutdown successful Shutdown successful Shutdown successful GOM = 0, EFSD = 0 GOM = 0, EFSD = 0 GOM = 0, EFSD = 0 Figure 18-57: Forced shutdown process START...
Page 862: Figure 18-58: Error Handling
Chapter 18 AFCAN Controller Figure 18-58: Error handling START START Error interrupt Error interrupt CINTS2 = 1? CINTS2 = 1? Check CAN module state Check CAN module state (read CnINFO register) (read CnINFO register) Clear CINTS2 bit Clear CINTS2 bit CINTS3 = 1? CINTS3 = 1? Check CAN protocol error state...
Page 863: Figure 18-59: Setting Cpu Stand-By (From Can Sleep Mode)
Chapter 18 AFCAN Controller Figure 18-59: Setting CPU stand-by (from CAN sleep mode) STAR T Set PS MODE0 bit. PSMODE0 bit = 1? Clear CINT S 5 bit. CAN sl e ep mode CINTS5 bit = 1? MBON bit = 0? Set CP U standb y mode.
Page 864: Figure 18-60: Setting Cpu Stand-By (From Can Stop Mode)
Chapter 18 AFCAN Controller Figure 18-60: Setting CPU stand-by (from CAN stop mode) STAR T Set PS MODE0 bit. PSMODE0 bit = 1? Clear CINT S 5 bit. (Note) CAN sl e ep mode Set PS MODE1 bit. PSMODE1 bit = 1? CAN stop mode MBON bit = 0? Set CP U standb y mode.
Page 865: Chapter 19 Random Number Generator (Μpd70F3187 Only)
Chapter 19 Random Number Generator (μPD70F3187 only) μPD70F3187 incorporates a hardware random number generator (RNG). The random number genera- tor is not supported on μPD70F3447. 19.1 Features • Random number sequence passing FIPS and Maurer test • Random number format: 16 bits •...
Page 866: Operation
Chapter 19 Random Number Generator (μPD70F3187 only) 19.3 Operation 19.3.1 Access timing After read access to the RNG register it needs a certain time to generate the next random number. Moreover, when a consecutive read access takes place before the new random number has been generated, the read access will be delayed.
Page 867: Chapter 20 Port Functions
Chapter 20 Port Functions 20.1 Features • Input-only ports: I/O ports: • Input/Output direction can be specified in 1.bit units • Noise removal circuit provided for external interrupts and timer inputs • Edge detect function for external interrupts (rising-, falling-, both edges) •...
Page 868: Port Configuration
20.2 Port Configuration The V850E/PH2 incorporates a total of 141 input/output ports (including 5 input-only ports) labelled port 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, AL, AH, DH, DL, CS, CM, CT, and CD. The port configuration is shown in Figure 20-1 below.
Page 869: Function Of Each Port
Chapter 20 Port Functions 20.2.1 Function of each port The port functions of V850E/PH2 are shown in the table below. The port type can vary for each individual bit of a port. In addition to their port functions, these pins are also shared with on-chip peripheral I/O pins in control mode.
Page 870: Port Types
Chapter 20 Port Functions 20.2.2 Port types Port type 1 Port type 1 provides a general purpose I/O port with peripheral output function. Figure 20-2: Port Type 1 PMCmn PMmn Peripheral output function PORT Address Remark: m: port number n: port bit number User’s Manual U16580EE3V1UD00...
Page 871: Figure 20-3: Port Type 1S
Chapter 20 Port Functions Port type 1S Port type 1S provides a general purpose I/O port with peripheral output function. This type is similar to port type 1, but features a Schmitt trigger input buffer characteristic. Figure 20-3: Port Type 1S PMCnm PMnm Peripheral...
Page 872: Figure 20-4: Port Type 1E
Chapter 20 Port Functions Port type 1E Port type 1E provides a general purpose I/O port with peripheral output function. In peripheral function mode a control signal is provided to enable or disable the output. Figure 20-4: Port Type 1E Peripheral output function enable 1 = enabled...
Page 873: Figure 20-5: Port Type 2
Chapter 20 Port Functions Port type 2 Port type 2 provides a general purpose I/O port with peripheral input function. Figure 20-5: Port Type 2 PMCmn PMmn PORT Address Peripheral input function Remark: m: port number n: port bit number User’s Manual U16580EE3V1UD00...
Page 874: Figure 20-6: Port Type 2A
Chapter 20 Port Functions Port type 2A Port type 2A provides a general purpose I/O port with peripheral input function. This type is similar as port type 2, but in port mode the peripheral input function is forced to high level. Figure 20-6: Port Type 2A PMCmn PMmn...
Page 875: Figure 20-7: Port Type 2C
Chapter 20 Port Functions Port type 2C Port type 2C provides a general purpose I/O port with peripheral input function. This type is similar to type 2, but features CMOS input buffer characteristic. Figure 20-7: Port Type 2C PMCmn PMmn PORT Address Peripheral...
Page 876: Figure 20-8: Port Type 3
Chapter 20 Port Functions Port type 3 Port type 3 provides a general purpose input port with NMI interrupt input function. Figure 20-8: Port Type 3 Edge Filter detection INTM ESN0 ESN1 INTM Address User’s Manual U16580EE3V1UD00...
Page 877: Figure 20-9: Port Type 4
Chapter 20 Port Functions Port type 4 Port type 4 provides a general purpose I/O port with peripheral I/O function. Peripheral output enable is controlled by the corresponding peripheral function. Figure 20-9: Port Type 4 Peripheral function output control PMCmn PMmn Peripheral output function...
Page 878: Figure 20-10: Port Type 4C
Chapter 20 Port Functions Port type 4C Port type 4 provides a general purpose I/O port with peripheral I/O function. Peripheral output enable is controlled by the corresponding peripheral function. Figure 20-10: Port Type 4C Peripheral function output control PMCmn PMmn Peripheral output function...
Page 879: Figure 20-11: Port Type 5
Chapter 20 Port Functions (10) Port type 5 Port type 5 provides a general purpose I/O port with peripheral I/O function. If the peripheral input function is disabled, the value of the peripheral input signal is fixed to low level. Figure 20-11: Port Type 5 PMCmn PMmn...
Page 880: Figure 20-12: Port Type 6
Chapter 20 Port Functions (11) Port type 6 Port type 6 provides a general purpose I/O port with peripheral output function and digitally filtered peripheral input function. Figure 20-12: Port Type 6 PMCmn PMmn Peripheral output function PORT Address Peripheral input function Filter Remark:...
Page 881: Figure 20-13: Port Type 7
Chapter 20 Port Functions (12) Port type 7 Port type 7 provides a general purpose I/O port with peripheral output function and external interrupt input capability. Figure 20-13: Port Type 7 PMCmn PMmn Peripheral output function PORT Address Edge Filter INTx detection INTM...
Page 882: Figure 20-14: Port Type 8
Chapter 20 Port Functions (13) Port type 8 Port type 8 provides a general purpose I/O port with digitally filtered peripheral input function and external interrupt input capability. Figure 20-14: Port Type 8 PMCmn PMmn PORT Address Peripheral input function Filter Edge INTx...
Page 883: Figure 20-15: Port Type 9
Chapter 20 Port Functions (14) Port type 9 Port type 9 provides a general purpose I/O port with peripheral input function and external interrupt input capability. This type is similar to the port type 8, but input noise filter is bypassed for peripheral input function.
Page 884: Figure 20-16: Port Type 10
Chapter 20 Port Functions (15) Port type 10 Port type10 provides a general purpose I/O port with digitally filtered peripheral input function. Figure 20-16: Port Type 10 PMCmn PMmn PORT Address Peripheral input function Filter Remark: m: port number n: port bit number User’s Manual U16580EE3V1UD00...
Page 885: Figure 20-17: Port Type 11
Chapter 20 Port Functions (16) Port type 11 Port type 11 provides a general purpose I/O port with peripheral output function. This type is similar to the port type 6, but all port registers are write protected against unintended change due to system or software malfunction.
Page 886: Figure 20-18: Port Type 12
Chapter 20 Port Functions (17) Port type 12 Port type 12 provides a general purpose I/O port with digitally filtered peripheral input function and peripheral output function. This type is similar to the port logic type 1S, but all port registers are write protected against unintended change due to system or software malfunction.
Page 887 Chapter 20 Port Functions (18) Port type 13 Port type 13 provides a general purpose I/O port with peripheral output function. This type is similar to the port logic type 11, but the output driver can be shut down immediately by the ESOx input signal (x = 0, 1).
Page 888: Figure 20-19: Port Type 13
Chapter 20 Port Functions Figure 20-19: Port Type 13 Analog ESOx filter "1"set request by active edge (pulse width 10ns) "1"set request by active level analog delay 10 ns PRCMD PESCn ESOxED0 ESOxED1 ESOxEN ESOSTn ESOxST PMCmn PMmn Peripheral output function PORT Address...
Page 889 Chapter 20 Port Functions (19) Port type 14 Port type 14 provides a general purpose I/O port with digitally filtered peripheral input function and peripheral output function. This type is similar to the port type 12, but the output driver can be shut down immediately by the ESOx input signal (x = 0, 1).
Page 890: Figure 20-20: Port Type 14
Chapter 20 Port Functions Figure 20-20: Port Type 14 Analog ESOx filter "1"set request by active edge (pulse width 10ns) "1"set request by active level analog delay 10 ns PRCMD PESCn ESOxED0 ESOxED1 ESOxEN ESOSTn ESOxST PRCMD PMCmn PMmn Peripheral output function PORT Address...
Page 891: Figure 20-21: Port Type 15
Chapter 20 Port Functions (20) Port type 15 Port type 15 provides a general purpose input port with external interrupt input function. This type is similar as port type 3. Difference is the additional filtered peripheral input function support. Figure 20-21: Port Type 15 Peripheral input function Edge...
Page 892: Figure 20-22: Port Type 15A
Chapter 20 Port Functions (21) Port type 15A Port type 15A provides a general purpose input port with external interrupt input function. This type is similar as port type 15. Difference is the analog filter instead of digital filter. Figure 20-22: Port Type 15A Peripheral input function Edge...
Page 893: Peripheral Registers Of I/O Ports
Chapter 20 Port Functions 20.2.3 Peripheral registers of I/O ports The following table lists the peripheral registers related to I/O ports. Table 20-2: Peripheral Registers of I/O Ports (1/3) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits...
Page 894 Chapter 20 Port Functions Table 20-2: Peripheral Registers of I/O Ports (2/3) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 0xFFFFF044 Port mode control register Port mode PMCDL 0x0000 control DL 0xFFFFF045 Port mode control register Port mode PMCDLH...
Page 895 Chapter 20 Port Functions Table 20-2: Peripheral Registers of I/O Ports (3/3) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 0xFFFFF44A Port mode control register port 5 PMC5 0x00 0xFFFFF44C Port mode control register port 6 PMC6 0x00 0xFFFFF44E...
Page 896: Peripheral Registers Of Valid Edge Control
Chapter 20 Port Functions 20.2.4 Peripheral registers of valid edge control The following table lists the peripheral registers related to valid edge control. Table 20-3: Peripheral Registers of Valid Edge Control Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit...
Page 897: Port Pin Functions
Chapter 20 Port Functions 20.3 Port Pin Functions 20.3.1 Port 0 Port 0 is a 5-bit input only port. Functions • Input data can be read in 1-bit units by using the port register 0 (P0). • The alternate functions shared with the input port functionality of port 0 are always enabled. Table 20-4: Alternate Function Pins and Port Types of Port 0 Port Alternate Function...
Page 898: Port 1
Chapter 20 Port Functions 20.3.2 Port 1 Port 1 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register 1 (P1). •...
Page 899: Figure 20-24: Port Register 1 (P1)
Chapter 20 Port Functions Control registers (a) Port register 1 (P1) The P1 register 1 is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P10 to P17. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content.
Page 900: Figure 20-26: Port Mode Control Register 1 (Pmc1) (1/2)
Chapter 20 Port Functions (c) Port mode control register 1 (PMC1) The PMC1 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H.
Page 901 Chapter 20 Port Functions Figure 20-26: Port Mode Control Register 1 (PMC1) (2/2) PMC13 Port/Control Mode Specification of Pin P13 I/O port mode Control mode (alternate function) PM13 Function TOP11 output mode TIP11, TEVTP0 input mode PMC12 Port/Control Mode Specification of Pin P12 I/O port mode Control mode (alternate function) PM12...
Page 902: Port 2
Chapter 20 Port Functions 20.3.3 Port 2 Port 2 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register 2 (P2). •...
Page 903: Figure 20-27: Port Register 2 (P2)
Chapter 20 Port Functions Control registers (a) Port register 2 (P2) The P2 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P20 to P27. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content.
Page 904: Figure 20-29: Port Mode Control Register 2 (Pmc2) (1/2)
Chapter 20 Port Functions (c) Port mode control register 2 (PMC2) The PMC2 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H.
Page 905 Chapter 20 Port Functions Figure 20-29: Port Mode Control Register 1 (PMC2) (2/2) PMC23 Port/Control Mode Specification of Pin P23 I/O port mode Control mode (alternate function) PM23 Function TOP51 output mode TIP51, TEVTP4 input mode PMC22 Port/Control Mode Specification of Pin P22 I/O port mode Control mode (alternate function) PM22...
Page 906: Port 3
Chapter 20 Port Functions 20.3.4 Port 3 Port 3 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register 3 (P3). •...
Page 907: Figure 20-30: Port Register 3 (P3)
Chapter 20 Port Functions Control registers (a) Port register 3 (P3) The P3 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P30 to P37. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content.
Page 908: Figure 20-32: Port Mode Control Register 3 (Pmc3) (1/2)
Chapter 20 Port Functions (c) Port mode control register 3 (PMC3) The PMC3 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H.
Page 909 Chapter 20 Port Functions Figure 20-32: Port Mode Control Register 3 (PMC3) (2/2) PMC33 Port/Control Mode Specification of Pin P33 I/O port mode TXDC1 output mode PMC32 Port/Control Mode Specification of Pin P32 Note I/O port mode PM32 Function Output mode Input mode, External interrupt request input mode (INTP5) RXDC1 input mode,...
Page 910: Port 4
Chapter 20 Port Functions 20.3.5 Port 4 Port 4 is a 6-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register 4 (P4). •...
Page 911: Figure 20-33: Port Register 4 (P4)
Chapter 20 Port Functions Control registers (a) Port register 4 (P4) The P4 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P40 to P45. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content.
Page 912: Figure 20-35: Port Mode Control Register 4 (Pmc4)
Chapter 20 Port Functions (c) Port mode control register 4 (PMC4) The PMC4 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H.
Page 913: Port 5
Chapter 20 Port Functions 20.3.6 Port 5 Port 5 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register 5 (P5). •...
Page 914: Figure 20-36: Port Register 5 (P5)
Chapter 20 Port Functions Control registers (a) Port register 5 (P5) The P5 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P50 to P57. Writing to the P5 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the P5 register is accepted.
Page 915: Figure 20-38: Port Mode Control Register 5 (Pmc5))
Chapter 20 Port Functions (c) Port mode control register 5 (PMC5) The PMC5 register is an 8-bit register that specifies the port mode or control mode (alternate function). Writing to the PMC5 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the PMC5 register is accepted.
Page 916: Figure 20-39: Port Emergency Shut Off Control Register 5 (Pesc5)
Chapter 20 Port Functions (d) Port emergency shut off control register 5 (PESC5) The PESC5 register is an 8-bit register that controls the emergency shut off behaviour of output buffers of ports P51 to P56. Writing to the PESC5 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the PESC5 register is accepted.
Page 917: Figure 20-40: Port Emergency Shut Off Status Register 5 (Esost5))
Chapter 20 Port Functions (e) Port emergency shut off status register 5 (ESOST5) The ESOST5 register is an 8-bit register that indicates the emergency status control mode (alternate function). Writing to the ESOST5 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the ESOST5 register is accepted.
Page 918: Port 6
Chapter 20 Port Functions 20.3.7 Port 6 Port 6 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register 6 (P6). •...
Page 919: Figure 20-41: Port Register 6 (P6)
Chapter 20 Port Functions Control registers (a) Port register 6 (P6) The P6 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P60 to P67. Writing to the P6 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the P6 register is accepted.
Page 920: Figure 20-43: Port Mode Control Register 6 (Pmc6) (1/2)
Chapter 20 Port Functions (c) Port mode control register 6 (PMC6) The PMC6 register is an 8-bit register that specifies the port mode or control mode (alternate function). Writing to the PMC6 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the PMC6 register is accepted.
Page 921 Chapter 20 Port Functions Figure 20-43: Port Mode Control Register 6 (PMC6) (2/2) PMC63 Port/Control Mode Specification of Pin P63 I/O port mode Control mode PM63 Function TOR13 output mode TIR12 input mode PMC62 Port/Control Mode Specification of Pin P62 I/O port mode Control mode PM62...
Page 922: Figure 20-44: Port Emergency Shut Off Control Register 6 (Pesc6)
Chapter 20 Port Functions (d) Port emergency shut off control register 6 (PESC6) The PESC6 register is an 8-bit register that controls the emergency shut off behaviour of output buffers of ports P61 to P66. Writing to the PESC6 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the PESC6 register is accepted.
Page 923: Figure 20-45: Port Emergency Shut Off Status Register 6 (Esost6))
Chapter 20 Port Functions (e) Port emergency shut off status register 6 (ESOST6) The ESOST6 register is an 8-bit register that indicates the emergency status control mode (alternate function). Writing to the ESOST6 register is only possible in a specific sequence, where a write access to the command register (PRCMD) must be made before a write access to the ESOST6 register is accepted.
Page 924: Port 7
Chapter 20 Port Functions 20.3.8 Port 7 Port 7 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register 7 (P7). •...
Page 925: Figure 20-46: Port Register 7 (P7)
Chapter 20 Port Functions Control registers (a) Port register 7 (P7) The P7 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P70 to P75. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content.
Page 926: Figure 20-48: Port Mode Control Register 7 (Pmc7) (1/2)
Chapter 20 Port Functions (c) Port mode control register 4 (PMC7) The PMC7 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H.
Page 927 Chapter 20 Port Functions Figure 20-48: Port Mode Control Register 7 (PMC7) (2/2) PMC72 Port/Control Mode Specification of Pin P72 I/O port mode PM72 Function Output mode Input mode, External interrupt request input mode (INTP12) TECRT0 input mode External interrupt request input mode (INTP12) PMC71 Port/Control Mode Specification of Pin P71 I/O port mode...
Page 928: Port 8
Chapter 20 Port Functions 20.3.9 Port 8 Port 8 is a 7-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register 8 (P8). •...
Page 929: Figure 20-49: Port Register 8 (P8)
Chapter 20 Port Functions Control registers (a) Port register 8 (P8) The P8 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P80 to P86. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content.
Page 930: Figure 20-51: Port Mode Control Register 8 (Pmc8) (1/2)
Chapter 20 Port Functions (c) Port mode control register 8 (PMC8) The PMC8 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H.
Page 931 Chapter 20 Port Functions Figure 20-51: Port Mode Control Register 8 (PMC8) (2/2) PMC83 Port/Control Mode Specification of Pin P83 I/O port mode PM83 Function Output Input, External interrupt request input mode (INTP6) Control mode PM83 Function SCS300 output mode External interrupt request input mode (INTP6) PMC82 Port/Control Mode Specification of Pin P82...
Page 932: Port 9
Chapter 20 Port Functions 20.3.10 Port 9 Port 9 is a 7-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register 9 (P9). •...
Page 933: Figure 20-52: Port Register 9 (P9)
Chapter 20 Port Functions Control registers (a) Port register 9 (P9) The P9 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P90 to P96. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content.
Page 934: Figure 20-54: Port Mode Control Register 9 (Pmc9) (1/2)
Chapter 20 Port Functions (c) Port mode control register 9 (PMC9) The PMC9 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H.
Page 935 Chapter 20 Port Functions Figure 20-54: Port Mode Control Register 9 (PMC9) (2/2) PMC94 Port/Control Mode Specification of Pin P94 I/O port mode PM94 Function Output mode Input mode, External interrupt request input mode (INTP10) Note Control mode PM94 Function SCS311 output mode External interrupt request input mode (INTP10) PMC93...
Page 936: Port 10
Chapter 20 Port Functions 20.3.11 Port 10 Port 10 is a 3-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register 10 (P10). •...
Page 937: Figure 20-55: Port Register 10 (P10)
Chapter 20 Port Functions Control registers (a) Port register 10 (P10) The P10 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins P100 to P105. This register can be read or written in 8-bit or 1-bit units. Reset input causes an undefined register content.
Page 938: Figure 20-57: Port Mode Control Register 10 (Pmc10)
Chapter 20 Port Functions (c) Port mode control register 10 (PMC10) The PMC10 register is an 8-bit register that specifies the port mode or control mode (alternate function). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H.
Page 939: Port Al
Chapter 20 Port Functions 20.3.12 Port AL Port AL is a 16-bit I/O port that can be set to input or output mode in 1-bit units. When the higher 8 bits of port AL are used as port ALH (PALH) and the lower 8 bits as port ALL (PALL), port AL becomes two 8-bit ports that can be set in the input or output mode in 1-bit units.
Page 940: Figure 20-58: Port Register Al(Pal)
Chapter 20 Port Functions Control registers (a) Port register AL (PAL) The PAL register is a 16-bit register that controls reading the pin levels and writing the output levels of port pins PAL0 to PAL15. This register can be read or written in 16-bit units. If the higher 8 bits of the PAL register are used as PALH register, and the lower 8 bits as the PALL register, however, these registers can be read or written in 8-bit or 1-bit units.
Page 941: Figure 20-59: Port Mode Register Al(Pmal)
Chapter 20 Port Functions (b) Port mode register AL (PMAL) The PMAL register is a 16-bit register that specifies the input or output mode of port pins PAL0 to PAL15. This register can be read or written in 16-bit units. If the higher 8 bits of the PMAL register are used as PMALH register, and the lower 8 bits as the PMALL register, however, these registers can be read or written in 8-bit or 1-bit units.
Page 942: Figure 20-60: Port Mode Control Register Al (Pmcal)
Chapter 20 Port Functions (c) Port AL mode control register The PMCAL register is a 16-bit read/write register that specifies the port mode or control mode (alternate function) of Port AL. This register can be read or written in 16-bit units. If the higher 8 bits of the PMCAL register are used as PMCALH register, and the lower 8 bits as the PMCALL register, however, these registers can be read or written in 8-bit or 1-bit units.
Page 943: Port Ah
Chapter 20 Port Functions 20.3.13 Port AH Port AH is a 6-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register AH (PAH). •...
Page 944: Figure 20-62: Port Mode Register Ah (Pmah)
Chapter 20 Port Functions (b) Port mode register AH (PMAH) The PMAH register is an 8-bit register that specifies the input or output mode of port pins PAL0 to PAL15. This register can be read or written in 8-bit units. Reset input sets this register to FFH.
Page 945: Port Dl
Chapter 20 Port Functions 20.3.14 Port DL Port DL is a 16-bit I/O port that can be set to input or output mode in 1-bit units. When the higher 8 bits of port DL are used as port DLH (PDLH) and the lower 8 bits as port DLL (PDLL), port DL becomes two 8-bit ports that can be set in the input or output mode in 1-bit units.
Page 946: Figure 20-64: Port Register Dl(Pdl)
Chapter 20 Port Functions Control registers (a) Port register DL (PDL) The PDL register is a 16-bit register that controls reading the pin levels and writing the output levels of port pins PDL0 to PDL15. This register can be read or written in 16-bit units. If the higher 8 bits of the PDL register are used as PDLH register, and the lower 8 bits as the PDLL register, however, these registers can be read or written in 8-bit or 1-bit units.
Page 947: Figure 20-65: Port Mode Register Dl(Pmdl)
Chapter 20 Port Functions (b) Port mode register DL (PMDL) The PMDL register is a 16-bit register that specifies the input or output mode of port pins PDL0 to PDL15. This register can be read or written in 16-bit units. If the higher 8 bits of the PMDL register are used as PMDLH register, and the lower 8 bits as the PMDLL register, however, these registers can be read or written in 8-bit or 1-bit units.
Page 948: Figure 20-66: Port Mode Control Register Dl (Pmcdl)
Chapter 20 Port Functions (c) Port mode control register DL (PMCDL) The PMCDL register is a 16-bit read/write register that specifies the port mode or control mode (alternate function) of Port DL. This register can be read or written in 16-bit units. If the higher 8 bits of the PMCDL register are used as PMCDLH register, and the lower 8 bits as the PMCDLL register, however, these registers can be read or written in 8-bit or 1-bit units.
Page 949: Port Dh
Chapter 20 Port Functions 20.3.15 Port DH Port DH is a 16-bit I/O port that can be set to input or output mode in 1-bit units. When the higher 8 bits of port DH are used as port DHH (PDHH) and the lower 8 bits as port DHL (PDHL), port DH becomes two 8-bit ports that can be set in the input or output mode in 1-bit units.
Page 950: Figure 20-67: Port Register Dh(Pdh)
Chapter 20 Port Functions Control registers (a) Port register DH (PDH) The PDH register is a 16-bit register that controls reading the pin levels and writing the output levels of port pins PDH0 to PDH15. This register can be read or written in 16-bit units. If the higher 8 bits of the PDH register are used as PDHH register, and the lower 8 bits as the PDHL register, however, these registers can be read or written in 8-bit or 1-bit units.
Page 951: Figure 20-68: Port Mode Register Dh(Pmdh)
Chapter 20 Port Functions (b) Port mode register DH (PMDH) The PMDH register is a 16-bit register that specifies the input or output mode of port pins PDH0 to PDH15. This register can be read or written in 16-bit units. If the higher 8 bits of the PMDH register are used as PMDHH register, and the lower 8 bits as the PMDHL register, however, these registers can be read or written in 8-bit or 1-bit units.
Page 952: Figure 20-69: Port Mode Control Register Dh (Pmcdh)
Chapter 20 Port Functions (c) Port mode control register DH (PMCDH) The PMCDH register is a 16-bit read/write register that specifies the port mode or control mode (alternate function) of Port DH. This register can be read or written in 16-bit units. If the higher 8 bits of the PMCDH register are used as PMCDHH register, and the lower 8 bits as the PMCDHL register, however, these registers can be read or written in 8-bit or 1-bit units.
Page 953: Port Cs
Chapter 20 Port Functions 20.3.16 Port CS Port CS is a 4-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register CS (PCS). •...
Page 954: Figure 20-71: Port Mode Register Cs (Pmcs)
Chapter 20 Port Functions (b) Port mode register CS (PMCS) The PMCS register is an 8-bit register that specifies the input or output mode of port pins PCS0, PCS1, PCS3 and PCS4. This register can be read or written in 8-bit units. Reset input sets this register to FFH.
Page 955: Port Ct
Chapter 20 Port Functions 20.3.17 Port CT Port CT is a 2-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register CT (PCT). •...
Page 956: Figure 20-74: Port Mode Register Ct (Pmct)
Chapter 20 Port Functions (b) Port mode register CT (PMCT) The PMCT register is an 8-bit register that specifies the input or output mode of port pins PCT4 and PCT5. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH.
Page 957: Figure 20-75: Port Mode Control Register Ct (Pmcct)
Chapter 20 Port Functions (c) Port mode control register CT (PMCCT) The PMCCTL register is an 8-bit register that specifies the port mode or control mode (alternate function) of port pins PCT4 and PCT5. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H in single-chip mode 0, and to 30H in ROM-less mode and single-chip mode 1.
Page 958: Port Cm
Chapter 20 Port Functions 20.3.18 Port CM Port CM is a 4-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register CM (PCM). •...
Page 959: Figure 20-77: Port Mode Register Cm (Pmcm)
Chapter 20 Port Functions (b) Port mode register CM (PMCM) The PMCM register is an 8-bit register that specifies the input or output mode of port pins PCM0, PCM1, PCM6 and PCM7. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH.
Page 960: Figure 20-78: Port Mode Control Register Cm (Pmccm)
Chapter 20 Port Functions (c) Port mode control register CM (PMCCM) The PMCCML register is an 8-bit register that specifies the port mode or control mode (alternate function) of port pins PCM0, PCM1, PCM6 and PCM7. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H in single-chip mode 0, and to 01H in ROM-less mode and single-chip mode 1.
Page 961: Port Cd
Chapter 20 Port Functions 20.3.19 Port CD Port CD is a 4-bit I/O port that can be set to input or output mode in 1-bit units. Functions • Input/output data can be specified in 1-bit units by using the port register CD (PCD). •...
Page 962 Chapter 20 Port Functions PCDn Input/Output Data Control of Pin PCDn Input mode: Low level is input Output mode: Low level is output Input mode: High level is input Output mode: High level is output Remark: n = 2 to 5 User’s Manual U16580EE3V1UD00...
Page 963: Figure 20-80: Port Mode Register Cd (Pmcd)
Chapter 20 Port Functions (b) Port mode register CD (PMCD) The PMCD register is an 8-bit register that specifies the input or output mode of port pins PCD2 to PCD5. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to FFH.
Page 964: Figure 20-81: Port Mode Control Register Cd (Pmccd)
Chapter 20 Port Functions (c) Port mode control register CD (PMCCD) The PMCCDL register is an 8-bit register that specifies the port mode or control mode (alternate function) of port pins PCD2 to PCD5. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H in single-chip mode 0, and to 3CH in ROM-less mode and single-chip mode 1.
Page 965: Noise Elimination
Chapter 20 Port Functions 20.4 Noise Elimination A timing controller used to secure the noise elimination time is provided for the pins shown in Table 20-23 below. Input signals that change within the noise elimination time are not internally acknowledged. Table 20-23: Noise Elimination (1/2) Unit Delay...
Page 966 Chapter 20 Port Functions Table 20-23: Noise Elimination (2/2) Unit Delay Noise Elimination Sampling Clock Type Time Timer P (TMP) P10/TIP00/TEVTP1/TOP00 Digital 4 to 5 clocks /16 (250 ns @ P11/TIP01/TTRGP1/TOP01 delay = 64 MHz) P12/TIP10/TTRGP0/TOP10 /64 (1 µs @ P13/TIP11/TEVTP0/TOP11 = 64 MHz) P14/TIP20/TEVTP3/TOP20...
Page 967: Figure 20-82: Noise Elimination Control Register (Nrc) (1/2)
Chapter 20 Port Functions Noise elimination control register (NRC) The NRC register is an 8-bit register that specifies the sampling clock that is used to eliminate digital noise of input pins. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 00H.
Page 968 Chapter 20 Port Functions Figure 20-82: Noise Elimination Control Register (NRC) (2/2) NRC2 Note Noise elimination clock setting for pin group 2 /16 (250 ns @ f = 64 MHz) /64 (1 µs @ f = 64 MHz) NRC1 Note Noise elimination clock setting for pin group 1 /16 (250 ns @ f = 64 MHz)
Page 969 Chapter 20 Port Functions [MEMO] User’s Manual U16580EE3V1UD00...
Page 970 Chapter 20 Port Functions User’s Manual U16580EE3V1UD00...
Page 971: Chapter 21 Reset Function
Chapter 21 Reset Function 21.1 Features • Reset function by RESET input • Forced reset function by DCU (refer to Chapter 23 ”On-Chip Debug Function (OCD)” on page 977) • Reset generator (RG) eliminates noise from the RESET pin. 21.2 Configuration During a system reset, most pins (all except the DCK, DRST, DMS, DDI, DDO, RESET, X2, V DD10 to V...
Page 972: Operation
(2 / f ) CPU starts up Remarks: 1. If no clock is supplied to V850E/PH2 (i.e. the oscillator does not work) the internal system reset will not be released independently from input level of the external RESET pin.
Page 973: Chapter 22 Internal Ram Parity Check Function
Chapter 22 Internal RAM Parity Check Function The V850E/PH2 microcontroller is provided with a parity check function for the internal RAM (iRAM). 22.1 Features • Maskable interrupt (INTPERR) on detection of parity error • Indication of internal RAM address of detected parity error •...
Page 974: Control Registers
Chapter 22 Internal RAM Parity Check Function 22.3 Control Registers Internal RAM parity error status register (RAMERR) The RAMERR register is an 8-bit register that reflects the parity error flags of the four bytes of one word (32 bits) in the internal RAM. The corresponding error flag (bits RAE0 to RAE3) is set and a maskable interrupt (INTPERR) is generated, if a parity error is detected during read access.
Page 975: Figure 22-2: Internal Ram Parity Error Address Register (Rampadd)
Chapter 22 Internal RAM Parity Check Function Internal RAM parity error address register (RAMPADD) The RAMPAD register is a 16-bit register that latches the internal RAM address causing the first parity error after hardware reset was released or RAMERR register was cleared. This register can be read or written in 16-bit units.
Page 976 Chapter 22 Internal RAM Parity Check Function [MEMO] User’s Manual U16580EE3V1UD00...
Page 977: Chapter 23 On-Chip Debug Function (Ocd)
23.1 Function Overview 23.1.1 On-chip debug unit type The on-chip debug unit incorporated in the V850E/PH2 microcontroller is RCU1 (run control unit 1). The on-chip unit incorporated differs depending on the microcontroller, and also features different func- tions.
Page 978 Chapter 23 On-Chip Debug Function (OCD) Software break function In addition to the hardware break function, a software break function is available. Up to eight software breakpoints can be set in the internal ROM area. The number of software breakpoints that can be set in the internal RAM area differs depending on the debugger used.
Page 979: Connection With N-Wire Type Emulator
Chapter 23 On-Chip Debug Function (OCD) 23.2 Connection with N-Wire Type Emulator To connect a N-Wire type emulator, it is necessary to mount an emulator connector and circuit for connection on the target system. Select either the KEL connector, MICTOR connector (Part number: 2-767004-2, distributor: Tyco Electronics AMP K.K.), or 2.54 mm pitch 20-pin general-purpose connector as the emulator connector.
Page 980: Figure 23-2: Pin Configuration Of Emulator Connector (On Target System Side)
Chapter 23 On-Chip Debug Function (OCD) Pin configuration Figure 23-2 shows the pin configuration of the emulator connector (target system side), and Table 23-1 shows the pin functions. Figure 23-2: Pin Configuration of Emulator Connector (on Target System Side) B13 A13 B12 A12 (Top View) Caution:...
Page 981: Table 23-1: Pin Functions Of Connector For Ie-V850E1-Cd-Nw (On Target System Side)
3.3 V input (for monitoring power application to target) Cautions: 1. The processing of the pins not incorporated in the V850E/PH2 or unused pins depends on the emulator used. 2. The pattern on the target board must satisfy the following conditions.
Page 982: Figure 23-3: Example Of Recommended Emulator Connection Of V850E/Ph2
Chapter 23 On-Chip Debug Function (OCD) Recommended circuit example The following figure shows an example of the recommended circuit of the emulator connector (on the target system side). Figure 23-3: Example of Recommended Emulator Connection of V850E/PH2 3.3 V V850E/PH2 KEL connector 8830E-026-170S Ω...
Page 983: Precautions
Chapter 23 On-Chip Debug Function (OCD) 23.3 Precautions <1> The flash memory of the device used in debugging is rewritten during debugging, so the number of flash memory rewrites cannot be guaranteed. Therefore, do not use the device used in debugging for a mass production product.
Page 984 Chapter 23 On-Chip Debug Function (OCD) [MEMO] User’s Manual U16580EE3V1UD00...
Page 985: Chapter 24 Flash Memory
Chapter 24 Flash Memory The V850E/PH2 and has a 512 KB on-chip flash memory configured as 128 blocks of 4 KB block size. 24.1 Features • 4-byte/1-clock access (when instruction is fetched) • Capacity: - μPD70F3481: 512 KB - μPD70F3447: 384 KB •...
Page 986: Memory Configuration
Chapter 24 Flash Memory 24.2 Memory Configuration The internal flash memory area is divided into 4 KB blocks (128 blocks for μPD70F3187, and 96 blocks for μPD70F3447)and can be programmed/erased in block units. All the blocks can also be erased at once.
Page 987: Figure 24-2: Flash Memory Mapping Of Μpd70F3447
Chapter 24 Flash Memory μ Figure 24-2: Flash Memory Mapping of PD70F3447 FFF FFFFH 0005 FFFFH On-chip peripheral I/O area Block 95 (4 KB) (4 KB) FFF F000H 0005 F000H 0005 EFFFH FFF EFFFH Use prohibited Block 94 (4 KB) (36 KB) FFF 6000H 0005 E000H...
Page 988: Functional Outline
Chapter 24 Flash Memory 24.3 Functional Outline The internal flash memory of the V850E/PH2 can be rewritten by using the rewrite function of the dedi- cated flash programmer, regardless of whether the V850E/PH2 has already been mounted on the tar- get system or not (off-board/on-board programming).
Page 989: Table 24-2: Basic Functions
Chapter 24 Flash Memory Table 24-2: Basic Functions Function Functional Outline Support by On-Board/Off-Board Self Programming Programming Block erasure The contents of specified memory blocks are erased. Chip erasure The contents of the entire memory area are erased all at once.
Page 990: Table 24-3: Protection Functions
Chapter 24 Flash Memory Table 24-3: Protection Functions Function Functional Outline Operation On-Board/Off-Board Self-Programming Programming × Block erase Execution of a block erase Block erase command: Can always be read or ⊕ command command on all blocks is Chip erase command: rewritten regardless of ⊕...
Page 991: Rewriting By Dedicated Flash Programmer
Chapter 24 Flash Memory 24.4 Rewriting by Dedicated Flash Programmer The flash memory can be rewritten by using a dedicated flash programmer after the V850E/PH2 is mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter.
Page 992: Communication Mode
Chapter 24 Flash Memory 24.4.2 Communication mode Communication between the dedicated flash programmer and the V850E/PH2 is performed by serial communication using the UARTC0 or CSIB0 interfaces of the V850E/PH2. UARTA0 Transfer rate: 9,600 to 153,600 bps Figure 24-4: Communication with Dedicated Flash Programmer (UARTC0)
Page 993: Figure 24-6: Communication With Dedicated Flash Programmer (Csib0 + Hs)
SIB0 SCKB0 PCM0 The dedicated flash programmer outputs the transfer clock, and the V850E/PH2 operates as a slave. When the PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the V850E/PH2. For details, refer to the PG-FP4 User’s Manual (U15260E).
Page 994: Table 24-4: Signal Connections Of Dedicated Flash Programmer (Pg-Fp4)
3. Connect these pins to supply power from the PG-FP4, or supply power externally to the target board. 4. Clock supply is provided by an oscillator on the target board. Clock supply from PG-FP4 is not supported for V850E/PH2. ⊕: Must be connected. Remark: ×: Do not need to be connected.
Page 995: Flash Memory Control
Chapter 24 Flash Memory 24.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 24-7: Procedure for Manipulating Flash Memory Start Switch to flash memory Supplies FLMD0 pulse programming mode Select communication system Manipulate flash memory End? User’s Manual U16580EE3V1UD00...
Page 996: Selection Of Communication Mode
Chapter 24 Flash Memory 24.4.4 Selection of communication mode In the V850E/PH2, the communication mode is selected by inputting pulses (11 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer.
Page 997: Communication Commands
Response command Dedicated flash programmer V850E/PH2 The following shows the commands for flash memory control in the V850E/PH2. All of these commands are issued from the dedicated flash programmer, and the V850E/PH2 performs the processing corre- sponding to the commands.
Page 998: Pin Connection
FLMD0 pin via port control, etc., before writing to the flash memory. For details, refer to the self-programming application note (U16929E). Figure 24-10: FLMD0 Pin Connection Example V850E/PH2 Dedicated flash programmer connection pin FLMD0...
Page 999: Figure 24-11: Flmd1 Pin Connection Example
FLMD0 pin, the flash memory programming mode is entered, so 0 V must be input to the FLMD1 pin. The following shows an example of the connection of the FLMD1 pin. Figure 24-11: FLMD1 Pin Connection Example V850E/PH2 FLMD1 Other device...
Page 1000: Figure 24-12: Conflict Of Signals (Serial Interface Input Pin)
(output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 24-12: Conflict of Signals (Serial Interface Input Pin) V850E/PH2 Dedicated flash programmer connection pins Conflict of signals...

This manual is also suitable for:

Mupd70f3187

NEC V850E/PH2 User Manual

Preface

Table of Contents

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 5 Memory Access Control Function (Μpd70F3187 Only)

Chapter 6 DMA Functions (DMA Controller)

Chapter 7 Interrupt/Exception Processing Function

Chapter 8 Clock Generator

Chapter 9 16-Bit Timer/Event Counter P

Chapter 10 16-Bit Inverter Timer/Counter R

Chapter 11 16-Bit Timer/Event Counter T

Chapter 12 16-Bit 2-Phase Encoder Input Up/Down Counter/General Purpose

Chapter 13 Auxiliary Frequency Output Function (AFO)

Chapter 14 A/D Converter

Chapter 15 Asynchronous Serial Interface C (UARTC)

Chapter 16 Clocked Serial Interface B (CSIB)

Chapter 17 Clocked Serial Interface 3 (CSI3)

Chapter 18 AFCAN Controller

Chapter 3 Functions

Chapter 19 Random Number Generator (Μpd70F3187 Only)

Chapter 20 Port Functions

Chapter 21 Reset Function

Chapter 22 Internal RAM Parity Check Function

Chapter 23 On-Chip Debug Function (OCD)

Chapter 24 Flash Memory

Chapter 25 Electrical Specifications

Chapter 26 Package Drawings

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Summary of Contents for NEC V850E/PH2