NEC V850E/MA1 Manuals

Manuals and User Guides for NEC V850E/MA1. We have 2 NEC V850E/MA1 manuals available for free PDF download: User Manual, Application Note

NEC V850E/MA1 User Manual (567 pages)

32-Bit Single-Chip Microcontroller

Brand: NEC | Category: Microcontrollers | Size: 3.29 MB

Table of Contents
12
Chapter 1 Introduction

27
- Outline
  27
- Features
  28
- Applications
  30
- Ordering Information
  30
- Pin Configuration (Top View)
  31
- Function Blocks
  35
- Internal Block Diagram
  35
- On-Chip Units
  36
- Differences Among Products
  38
Chapter 2 Pin Functions

39
Chapter 3 Cpu Function

65
- Features
  65
- CPU Register Set
  66
- Program Register Set
  67
- System Register Set
  68
- Operating Modes
  70
- Operating Mode Specification
  71
- Address Space
  72
- CPU Address Space
  72
- Image
  73
- Wrap-Around of CPU Address Space
  74
- Memory Map
  75
- Area
  77
- External Memory Expansion
  82
- Recommended Use of Address Space
  83
- Peripheral I/O Registers
  85
- Specific Registers
  94
- System Wait Control Register (VSWC)
  94
- Cautions
  94
Chapter 4 Bus Control Function

95
- Features
  95
- Bus Control Pins
  95
- Pin Status During Internal ROM, Internal RAM, and Peripheral I/O Access
  96
- Memory Block Function
  97
- Chip Select Control Function
  98
- Bus Cycle Type Control Function
  101
- Bus Cycle Type Configuration Registers 0, 1 (BCT0, BCT1)
  102
- Bus Access
  103
- Number of Access Clocks
  103
- Bus Sizing Function
  104
- Endian Control Function
  105
- Big Endian Method Usage Restrictions in NEC Development Tools
  106
- Bus Width
  108
- Wait Function
  119
- Programmable Wait Function
  119
- External Wait Function
  124
- Relationship between Programmable Wait and External Wait
  124
- Bus Cycles in Which Wait Function Is Valid
  125
- Idle State Insertion Function
  126
- Bus Hold Function
  127
- Function Outline
  127
- Bus Hold Procedure
  128
- Operation in Power-Save Mode
  128
- Bus Hold Timing (SRAM)
  129
- Bus Hold Timing (EDO DRAM)
  131
- Bus Hold Timing (SDRAM)
  135
- Bus Priority Order
  139
- Boundary Operation Conditions
  140
- Program Space
  140
- Data Space
  140
Chapter 5 Memory Access Control Function

141
- SRAM, External ROM, External I/O Interface
  141
- Features
  141
- SRAM Connection
  142
- SRAM, External ROM, External I/O Access
  144
- Page ROM Controller (ROMC)
  150
- Features
  150
- Page ROM Connection
  151
- On-Page/Off
  152
- Page ROM Configuration Register (PRC)
  154
- Page ROM Access
  155
- DRAM Controller (EDO DRAM)
  159
- Features
  159
- DRAM Connection
  160
- Address Multiplex Function
  161
- DRAM Configuration Registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6)
  162
- DRAM Access
  165
- Refresh Control Function
  170
- Self-Refresh Control Function
  175
- DRAM Controller (SDRAM)
  177
- Features
  177
- SDRAM Connection
  177
- Address Multiplex Function
  178
- SDRAM Configuration Registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6)
  180
- SDRAM Access
  182
- Refresh Control Function
  196
- Self-Refresh Control Function
  201
- SDRAM Initialization Sequence
  203
Chapter 6 Dma Functions (Dma Controller)

206
- Features
  206
- Configuration
  207
- Control Registers
  208
- DMA Source Address Registers 0 to 3 (DSA0 to DSA3)
  208
- DMA Destination Address Registers 0 to 3 (DDA0 to DDA3)
  210
- DMA Byte Count Registers 0 to 3 (DBC0 to DBC3)
  212
- DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3)
  213
- DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3)
  215
- DMA Disable Status Register (DDIS)
  216
- DMA Restart Register (DRST)
  216
- DMA Terminal Count Output Control Register (DTOC)
  217
- DMA Trigger Factor Registers 0 to 3 (DTFR0 to DTFR3)
  218
- DMA Bus States
  221
- Types of Bus States
  221
- DMAC Bus Cycle State Transition
  223
- Transfer Modes
  224
- Single Transfer Mode
  224
- Single-Step Transfer Mode
  226
- Block Transfer Mode
  227
- Transfer Types
  228
- 2-Cycle Transfer
  228
- Flyby Transfer
  244
- Transfer Object
  255
- Transfer Type and Transfer Object
  255
- External Bus Cycles During DMA Transfer
  256
- DMA Channel Priorities
  256
- Next Address Setting Function
  257
- DMA Transfer Start Factors
  258
- Terminal Count Output Upon DMA Transfer End
  259
- Forcible Interruption
  259
- Forcible Termination
  260
- Times Related to DMA Transfer
  261
- Maximum Response Time for DMA Transfer Request
  261
- One-Time Transfer During Single Transfer Via DMARQ0 to DMARQ3 Signals
  262
- Cautions
  263
- Interrupt Factors
  263
- DMA Transfer End
  263
Chapter 7 Interrupt/Exception Processing Function

264
- Features
  264
- Non-Maskable Interrupts
  267
- Operation
  268
- Restore
  270
- Non-Maskable Interrupt Status Flag (NP)
  271
- Noise Elimination
  271
- Edge Detection Function
  271
- Maskable Interrupts
  272
- Operation
  272
- Restore
  274
- Priorities of Maskable Interrupts
  275
- Interrupt Control Register (Xxicn)
  279
- Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
  282
- In-Service Priority Register (ISPR)
  283
- Maskable Interrupt Status Flag (ID)
  283
- Noise Elimination
  284
- Interrupt Trigger Mode Selection
  284
- Software Exception
  288
- Operation
  288
- Restore
  289
- Exception Status Flag (EP)
  290
- Exception Trap
  291
- Illegal Opcode Definition
  291
- Debug Trap
  293
- Multiple Interrupt Servicing Control
  295
- Interrupt Latency Time
  297
- Periods in Which Interrupts Are Not Acknowledged
  298
Chapter 8 Prescaler Unit (Prs)

299
Chapter 9 Clock Generation Function

300
- Features
  300
- Configuration
  300
- Input Clock Selection
  301
- Direct Mode
  301

NEC V850E/MA1 Application Note (99 pages)

32-Bit Single-Chip Microcontrollers PCI Host Bridge Macro

Brand: NEC | Category: Microcontrollers | Size: 0.91 MB

Table of Contents
8
Chapter 1 Overview of each Product

10
- Outline
  
  10
- Features
  
  11
- Ordering Information
  
  12
- Pin Configuration
  
  14
- Internal Block Diagram
  
  25
Chapter 2 Overview of Pci Host Bridge Macro

29
- Outline
  
  29
- Features
  
  30
Chapter 3 Specifications of Pci Host Bridge Macro

31
- Internal Blocks of PCI Host Bridge Macro
  
  31
- Relationship between Internal Blocks and Signals
  
  32
- Pin Functions
  
  33
- Registers
  
  35
  - PCI_CONFIG_DATA Register
    35
  - PCI_CONFIG_ADD Register
    36
  - PCI_CONTROL Register
    37
  - PCI_IO_BASE Register
    38
  - PCI_MEM_BASE Register
    38
  - PCI_INT_CTL Register
    39
  - PCI_ERR_ADD Register
    40
  - SYSTEM_MEM_BASE Register
    41
  - SYSTEM_MEM_RANGE Register
    41
  - SDRAM_CTL Register
    42
- Address Map
  
  44
- Initializing PCI Host Bridge Macro
  
  45
- Bus Width of External Bus Interface
  
  46
- Timing
  
  47
  - External Bus Interface Timing
    47
  - PCI Bus Interface Timing
    50
Chapter 4 Configuration Examples of Fpga Integration

57
Cautions on Designing FPGA

65
Chapter 5 Application Examples

67
Block Diagram of Evaluation Board

67
Specifications of Evaluation Board

68
Example of Evaluation Board Connection Circuit

69
Evaluation Board Memory Space

70
Sample Program Examples

72

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NEC V850E/MA1 Manuals

NEC V850E/MA1 User Manual (567 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Function

Chapter 4 Bus Control Function

Chapter 5 Memory Access Control Function

Chapter 6 Dma Functions (Dma Controller)

Chapter 7 Interrupt/Exception Processing Function

Chapter 8 Prescaler Unit (Prs)

Chapter 9 Clock Generation Function

NEC V850E/MA1 Application Note (99 pages)

Table of Contents

Chapter 1 Overview of each Product

Outline

Features

Ordering Information

Pin Configuration

Internal Block Diagram

Chapter 2 Overview of Pci Host Bridge Macro

Outline

Features

Chapter 3 Specifications of Pci Host Bridge Macro

Internal Blocks of PCI Host Bridge Macro

Relationship between Internal Blocks and Signals

Pin Functions

Registers

Address Map

Initializing PCI Host Bridge Macro

Bus Width of External Bus Interface

Timing

Chapter 4 Configuration Examples of Fpga Integration

Conditions for Configuration Examples of FPGA Integration

Points to Remember When Creating Top Layer of FPGA

Reference Diagram for FPGA Top Connection

FPGA Top Pin Functions

FPGA Top Pin Configuration

Cautions on Designing FPGA

Chapter 5 Application Examples

Block Diagram of Evaluation Board

Specifications of Evaluation Board

Example of Evaluation Board Connection Circuit

Evaluation Board Memory Space

Sample Program Examples

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