Page 1 Preliminary User’s Manual V850E/CA2 JUPITER 32-/16-bit Romless Microcontroller Hardware µPD703128, µPD703129 Document No. U15839EE1V0UM00 Date Published August 2003  NEC Corporation 2003 Printed in Germany...
Page 2 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 3 NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 4 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 5: Preface
Preface Readers This manual is intended for users who want to understand the functions of the V850E/CA2 (nickname Jupiter). Purpose This manual presents the hardware manual of V850E/CA2. Organization This system specification describes the following sections: • Pin function • CPU function •...
Page 6 Preliminary User’s Manual U15839EE1V0UM00...
Page 7: Table Of Contents
Table of Contents Preface ............5 Chapter 1 Introduction.
Page 8 4.8.2 External wait function ..........133 4.8.3 Relationship between programmable wait and external wait .
Page 9 7.10 Forcible Interruption ........... 195 7.11 Forcible Termination.
Page 10 Register Description ........... 268 9.5.1 Power Save Control Register (PSC).
Page 11 13.2.7 Precautions ............391 13.3 Clocked Serial Interfaces (CSI00 to CSI02).
Page 12 16.3.9 Port 9 ............574 16.3.10Port AH .
Page 13 List of Figures Figure 1-1: V850E/CA2 Jupiter Pin Configuration ................. 27 Figure 1-2: V850E/CA2 Jupiter Block Diagram ................29 Figure 2-1: Pin I/O Circuits ......................54 Figure 3-1: CPU Register Set ......................56 Figure 3-2: Program Counter (PC) ....................57 Figure 3-3: Interrupt Source Register (ECR) .................
Page 14 Figure 7-11: DMA Trigger Factor Registers 1 (DTFR1) ..............180 Figure 7-12: DMA Trigger Factor Registers 2 (DTFR2) ..............181 Figure 7-13: DMA Trigger Factor Registers 3 (DTFR3) ..............182 Figure 7-14: Buffer Register Configuration ..................183 Figure 7-15: DMAC Bus Cycle State Transition Diagram .............. 186 Figure 7-16: Single Transfer Example 1 ..................
Page 15 Figure 9-11: Sub Watch mode released by RESET input ............. 263 Figure 9-12: Sub Watch mode release by Watchdog reset, NMI, INT........... 264 Figure 9-13: STOP mode released by RESET input ..............266 Figure 9-14: STOP mode release by Watchdog reset, NMI, INT........... 267 Figure 9-15: Power Save Control Register (PSC) ................
Page 16 Figure 10-53: Timing of PWM operation (match and clear) ............. 341 Figure 10-54: Timing when 0000H is set in GCCnm (match and clear) .......... 342 Figure 10-55: Timing when the same value as set in GCCn0/GCCn5 is set in GCCnm (match and clear).......................
Page 17 Figure 13-36: Timing Chart of Interrupt Request Signal Output in Delay Mode (1/2) ...... 413 Figure 13-37: Repeat Transfer (Receive-Only) Timing Chart ............415 Figure 13-38: Repeat Transfer (Transmission/Reception) Timing Chart ......... 417 Figure 13-39: Timing Chart of Next Transfer Reservation Period (1/2) ........... 418 Figure 13-40: Transfer Request Clear and Register Access Contention.........
Page 18 Figure 14-46: General Initialisation Sequence for the CAN Interface ..........515 Figure 14-47: Initialisation Sequence for a CAN module ..............517 Figure 14-48: Setting CAN Module into Initialisation State .............. 519 Figure 15-1: Block Diagram of A/D Converter ................526 Figure 15-2: A/D Converter Mode Register (ADM) ...............
Page 19 Figure 16-37: Port CT Mode Control Register (PMCCT) ............... 580 Figure 16-38: Port CM (PCM) ......................581 Figure 16-39: Port CM Mode Register (PMCM) ................582 Figure 16-40: Port CM Mode Control Register (PMCCM) ............. 582 Figure 17-1: Reset signal acknowledgment................... 585 Figure 17-2: Reset at power-on .....................
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Page 21 List of Tables Table 2-1: Port Pins ......................... 33 Table 2-2: Non-Port Pins ......................... 36 Table 2-3: Pin Status in Reset and Standby Mode................39 Table 2-4: Types of Pin I/O Circuit and Connection of Unused Pins ..........51 Table 3-1: Program Registers......................
Page 22 Table 14-8: Relative Addresses of CAN Module 4 Registers ............437 Table 14-9: Transmitted Data On the CAN Bus (ATS = 1) .............. 442 Table 14-10: Example for Automatic Transmission Priority Detection..........444 Table 14-11: Example for Transmit Buffer Allocation When More Than 5 Buffers Linked to a CAN Module....................
Page 23: Chapter 1 Introduction
Chapter 1 Introduction The V850E/CA2 Jupiter is a product in NEC’s V850 family of ROM-less microcontrollers designed for Automotive applications. 1.1 General The V850E/CA2 Jupiter Rom-less microcontroller, is a member of NEC's V850 32-bit RISC family, which match the performance gains attainable with RISC-based controllers to the needs of embedded control applications.
Page 24: Device Features
Chapter 1 Introduction 1.2 Device Features • - Core: V850E1 - Number of instructions: 31.25 ns (@ φ = 32 MHz) - Min. instruction execution time: 32 bits × 32 - General registers: • Instruction set: - V850E (compatible with V850 plus additional powerful instructions for reducing code and increas- ing execution speed) - Signed multiplication (16 bits x 16 bits →...
Page 25 Chapter 1 Introduction • Bus control unit: - Address/data separated bus 24-bit address/ 16-bit data bus - Supply voltage power for Bus Interface 3.3 V - Chip Select Signals • DMA control unit: 4 channels • I/O lines (5 V): •...
Page 26: Application Fields
Chapter 1 Introduction 1.3 Application Fields The V850E CA2/ Jupiter is ideally suited for automotive applications, like dashboard or gateway appli- cations. It is also an excellent choice for other applications where a combination of sophisticated periph- eral functions and CAN network support is required. 1.4 Ordering Information Internal ROM Internal RAM...
Page 27: Pin Configuration (Top View)
Chapter 1 Introduction 1.5 Pin Configuration (Top View) 144 pin QFP (fine pitch) (20 × 20 mm) • - µPD703128 (A) - µPD703129 (A) - µPD703129 (A1) Figure 1-1: V850E/CA2 Jupiter Pin Configuration P43/TIG13/TOG13 P42/TIG12/TOG12 P41/TIG11/TOG11 MODE2 P56/TOC00 PAH0/A16 P65/SI02...
Page 28 Chapter 1 Introduction Pin Identification A0 to A23 : Address Bus PAH0 to PAH7 : Port AH D0 to D15 : Data Bus PCM0 : Port CM0 ANI00 to ANI11 : Analog Input PCS0, PCS3, PCS4 : Port CS : Analog Power Supply PCT0, PCT1, PCT4 : Port CT : Analog Reference Voltage RESET...
Page 29: Function Block Diagram
Chapter 1 Introduction 1.6 Function Block Diagram Figure 1-2: V850E/CA2 Jupiter Block Diagram power supply Interrupt INTP0 to INTP5 Controller INTP00, INTP05 CPU Core INTP10, INTP15 INTP20, INTP21 TIG00 to TIG05 16-bit Timer Barrel Hardware A0 to A15 TMG0 Shifter...
Page 30: On-Chip Units
Chapter 1 Introduction 1.6.1 On-chip units The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits x 16 bits → 32 bits or 32 bits x 32 bits →...
Page 31 Chapter 1 Introduction Real-time pulse unit (RPU) This unit has 3 channels of 16-bit multi purpose timer/event counter and 2 channels of 16-bit inter- val timer built in, and it is possible to measure pulse widths or frequency and to output a program- mable pulse.
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Page 33: Chapter 2 Pin Functions
Chapter 2 Pin Functions 2.1 List of Pin Functions The names and functions of this product’s pins are listed below. These pins can be divided into port pins and non-port pins according to their functions. Port pins Table 2-1: Port Pins (1/3) Port Function Alternate...
Page 34 Chapter 2 Pin Functions Table 2-1: Port Pins (2/3) Port Function Alternate Note FCRXD4 Note FCTXD4 INTP4 Port 5 INTP5 7-bit input/output port TI0/INTP20 TI1/INTP21 INTP0 INTP1 INTP2 Port 6 8-bit input/output port INTP3 SCK2 ANI0 ANI1 ANI2 ANI3 Port 7 8-bit input port ANI4 ANI5...
Page 35 Chapter 2 Pin Functions Table 2-1: Port Pins (3/3) Port Function Alternate PAH0 PAH1 PAH2 PAH3 Port AH 8-bit input/output port PAH4 PAH5 PAH6 PAH7 PCS0 Port CS PCS3 3-bit input/output port PCS4 PCT0 Port CT PCT1 3-bit input/output port PCT4 PCM0 Port CM...
Page 36: Table 2-2: Non-Port Pins
Chapter 2 Pin Functions Non-port pins Table 2-2: Non-Port Pins (1/3) Pin Name Function Alternate – Power supply 5 V DD50 DD52 – GND potential for 5 V power supply SS50 SS52 Note 1 – Power supply 3.3 V DD30 DD36 –...
Page 37 Chapter 2 Pin Functions Table 2-2: Non-Port Pins (2/3) Pin Name Function Alternate FCRXD1 FCRXD2 input serial receive data input to FCAN1-FCAN4 Note 3 FCRXD3 Note 3 FCRXD4 FCTXD1 FCTXD2 output serial transmit data output to FCAN1-FCAN4 Note 3 FCTXD3 Note 3 FCTXD4 INTP0...
Page 38 Chapter 2 Pin Functions Table 2-2: Non-Port Pins (3/3) Pin Name Function Alternate TIG15 input Timer G 1 capture input 5 P45/TOG15 TOG11 output Timer G 1 compare output 1 P41/TIG11 TOG12 output Timer G 1 compare output 2 P42/TIG12 TOG13 output Timer G 1 compare output 3...
Page 39: Table 2-3: Pin Status In Reset And Standby Mode
Chapter 2 Pin Functions Pin status in RESET and STANDBY mode Table 2-3: Pin Status in Reset and Standby Mode Operating Status Sub- Idle state RESET STOP WATCH IDLE HALT WATCH (TI) D0 to D15 Hi-Z operate operate Hi-Z/-- Hi-Z/-- Hi-Z/-- Hi-Z/-- A0 to A23...
Page 40: Description Of Pin Functions
Chapter 2 Pin Functions 2.2 Description of Pin Functions P10 to P17 (Port 1) … Input/output Port 1 is an 8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, P10 to P17 operate as the serial interface (UART1, NOTE FCAN1, FCAN2, FCAN3 ) input/output.
Page 41 Chapter 2 Pin Functions P20 to P27 (Port 2) … Input/output Port 2 is an 8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P20 to P27 operate as the serial interface (UART0, CSI0,CS1) input/output.
Page 42 Chapter 2 Pin Functions P30 to P35 (Port 3) … Input/output Port 3 is a 6-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P30 to P35 operate as the real-time pulse unit (RPU) input/output and external interrupt request input.
Page 43 Chapter 2 Pin Functions P40 to P45 (Port 4) … Input/output Port 4 is a 6-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P40 to P45 operate as the real-time pulse unit (RPU) input/output and external interrupt request input.
Page 44 Chapter 2 Pin Functions P50 to P56 (Port 5) … Input/output Port 5 is a 7-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P50 to P56 operate as the real-time NOTE pulse unit (RPU) input/output, as the serial interface (FCAN4 ) and as external interrupt...
Page 45 Chapter 2 Pin Functions P60 to P67 (Port 6) … Input/Output Port 6 is an 8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P60 to P67 operate as the serial interface (CSI2) or as an external interrupt request input.
Page 46 Chapter 2 Pin Functions P70 to P77 (Port 7), P80 to P83 (Port 8) … Input Port 7 is an 8-bit input-only port in which all pins are fixed as input pins. Port 8 is a 4-bit input-only port. P70 to P77 and P80 to P83 can function as input ports and as analog input pins for the A/D converter in control mode.
Page 47 Chapter 2 Pin Functions PAH0 to PAH7 (Port AH) … Input/output Port AH is an 8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, this port operates as the address bus (A16 to A23) for when memory is accessed externally.
Page 48 Chapter 2 Pin Functions (11) PCT0, PCT1, PCT4 (Port CT) … Input/output Port CT is a 3-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, it operates as control signal output when memory is accessed externally.
Page 49 Chapter 2 Pin Functions (13) ANI00 to ANI11 (Analog input) … Input These are analog input pins to the A/D converter. (14) MODE0 to MODE2 (Mode) … Input These are the input pins that specify the operation mode. Operation modes are broadly divided into normal operation modes and flash memory programming mode.
Page 50 Chapter 2 Pin Functions (23) V to V (Ground) SS50 SS52 These are the ground pins for the 5 V power supply. (24) V to V (Power supply) DD30 DD36 These are the positive 3.3 V power supply pins. (25) V to V (Ground) SS30...
Page 51: Types Of Pin I/O Circuit And Connection Of Unused Pins
Chapter 2 Pin Functions 2.3 Types of Pin I/O Circuit and Connection of Unused Pins Table 2-4: Types of Pin I/O Circuit and Connection of Unused Pins (1/3) I/O Circuit Type Recommended connection FCRXD1 For input: individually connect to V or V via a resistor.
Page 52 Chapter 2 Pin Functions Table 2-4: Types of Pin I/O Circuit and Connection of Unused Pins (2/3) I/O Circuit Type Recommended connection For input: individually connect to V or V via a resistor. INTP0 For output: leave open. INTP1 INTP2 INTP3 SI02 SO02...
Page 53 Chapter 2 Pin Functions Table 2-4: Types of Pin I/O Circuit and Connection of Unused Pins (3/3) I/O Circuit Type Recommended connection PCT0 For input: individually connect to V or V via a resistor. PCT1 For output: leave open. PCT4 PCM0 WAIT AIN0-AIN11...
Page 54: Figure 2-1: Pin I/O Circuits
Chapter 2 Pin Functions Figure 2-1: Pin I/O Circuits Type 2 Type 3 P-ch Data N-ch Type 5 Type 4 data P-ch Data P-ch IN/OUT IN/OUT output N-ch Output disable N-ch disable input enable Type 5-K Type 9-C P-ch Data Comparator P-ch IN/OUT...
Page 55: Chapter 3 Cpu Function
Chapter 3 CPU Function The CPU of the V850E/CA2 Jupiter is based on a RISC architecture and executes almost all the instructions which can be accessed from the iCache in one clock cycle, using a 5-stage pipeline control. 3.1 Features •...
Page 56: Cpu Register Set
Chapter 3 CPU Function 3.2 CPU Register Set The registers of the V850E/CA2 Jupiter can be classified into two categories: a general program regis- ter set and a dedicated system register set. All the registers are 32-bit width. For details, refer to V850E User’s Manual Architecture.
Page 57: Program Register Set
Chapter 3 CPU Function 3.2.1 Program register set The program register set includes general registers and a program counter. General registers Thirty-two general registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable. However, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers.
Page 58: System Register Set
Chapter 3 CPU Function 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. To read/write these system registers, use the system register load/store instruction (LDSR or STSR instruction) with a specific system register number indicated below. Table 3-2: System Register Numbers Operand Specification System Register Name...
Page 59: Figure 3-3: Interrupt Source Register (Ecr)
Chapter 3 CPU Function Figure 3-3: Interrupt Source Register (ECR) 16 15 After reset FECC EICC 00000000H Bit Position Bit Name Function 31 to 16 FECC Exception code of non-maskable interrupt (NMI) 15 to 0 EICC Exception code of exception/maskable interrupt Preliminary User’s Manual U15839EE1V0UM00...
Page 60: Figure 3-4: Program Status Word (Psw)
Chapter 3 CPU Function Figure 3-4: Program Status Word (PSW) After reset 00000020H Bit Position Flag Function 31 to 8 Reserved field (fixed to 0). Indicates that non-maskable interrupt (NMI) processing is in progress. This flag is set when NMI is accepted, and disables multiple interrupts. 0: NMI servicing not under execution.
Page 61: Table 3-3: Saturation-Processed Operation Result
Chapter 3 CPU Function Table 3-3: Saturation-Processed Operation Result Flag Status Saturation-Processed Status of Operation Result Operation Result Maximum positive value exceeded 7FFFFFFFH Maximum negative value exceeded 80000000H Positive (maximum not exceeded) Retains the value Operation result itself before operation Negative (maximum not exceeded) Preliminary User’s Manual U15839EE1V0UM00...
Page 62: Operation Modes
Chapter 3 CPU Function 3.3 Operation Modes 3.3.1 Operation modes The V850E/CA2 Jupiter has the following operations modes. Mode specification is carried out by the MODE0 to MODE2 pins. Normal operation mode ROM-less mode Access to the external ROM is enabled.
Page 63: Operation Mode Specification
To program/erase the contents of the external memory device, it is required to enable a “Flash-Pro- gramming-Mode”. The following operation modes are generally available for the V850E/CA2 Jupiter device: (a) µPD703128, µPD703129...
Page 64 Chapter 3 CPU Function ROM-less Mode 0 When a system reset is released, the bus interface pins enter the peripheral mode and the pro- gram branches to the reset entry address in the external memory to start instruction execution. Address output is masked by additional circuitry in the ROMLESS Mode 0 to reduce EMI. Address is output only in case external access is performed.
Page 65: Address Space
Chapter 3 CPU Function 3.4 Address Space 3.4.1 CPU address space The CPU of the V850E/CA2 is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a maximum of 64 MB of linear address space (program space) is supported.
Page 66: Image
Chapter 3 CPU Function 3.4.2 Image 64 MB physical address space is seen as 64 images in the 4 GB CPU address space. In actuality, the same 64 MB physical address space is accessed regardless of the values of bits 31 to 26 of the CPU address.
Page 67: Wrap-Around Of Cpu Address Space
Chapter 3 CPU Function 3.4.3 Wrap-around of CPU address space Program space Of the 32 bits of the PC (program counter), the higher 6 bits are set to “0”, and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to 26 as a result of branch address calculation, the higher 6 bits ignore the carry or borrow.
Page 68: Memory Map
Chapter 3 CPU Function 3.5 Memory Map The V850E/CA2 reserves areas as shown in Figure 3-9. For µPD703128 Figure 3-9: Memory Map (µPD703128 (A)) Single-chip mode x3FF FFFFH Internal peripheral 4 Kbytes I/O area x3FF F000H x3FF EFFFH 16 Kbytes x3FF B000H x3FF AFFFH Internal RAM area...
Page 69: Figure 3-10: Memory Map (Μpd703129 (A), Μpd703129 (A1))
Chapter 3 CPU Function For µPD703129 Figure 3-10: Memory Map (µPD703129 (A), µPD703129 (A1)) Single-chip mode x3FF FFFFH Internal peripheral 4 Kbytes I/O area x3FF F000H x3FF EFFFH 12 Kbytes x3FF C000H x3FF BFFFH Internal RAM area 16 Kbytes x3FF 8000H x3FF 7FFFH 64 Mbytes External memory area...
Page 70: Area
Chapter 3 CPU Function 3.5.1 Area External ROM area The following areas can be used as external memory area. (a) µPD703128, µPD703129 x000 0000H to x3FF 7FFFH Access to the external memory area uses the chip select signal assigned to each memory block (which is carried out in the CS unit set by chip area selection control registers 0 and 1 (CSC0, CSC1)).
Page 71 Chapter 3 CPU Function Table 3-5: Interrupt/Exception Table (2/3) Start Address of Interrupt/ Interrupt/Exception Source Exception Table 0000 0140H CC coincidence Channel 0 0000 0150H CC coincidence Channel 1 0000 0160H CC coincidence Channel 2 0000 0170H CC coincidence Channel 3 0000 0180H CC coincidence Channel 4 0000 0190H...
Page 72 Chapter 3 CPU Function Table 3-5: Interrupt/Exception Table (3/3) Start Address of Interrupt/ Interrupt/Exception Source Exception Table 0000 0390H Reception Error UART51 0000 03A0H Reception Completion UART51 0000 03B0H Transmission Completion UART51 0000 03C0H DMA Channel 0 transfer completed 0000 03D0H DMA Channel 1 transfer completed 0000 03E0H DMA Channel 2 transfer completed...
Page 73: Figure 3-11: Internal Ram Area Of Μpd703129
Chapter 3 CPU Function Internal RAM area For the µPD703128 12 KB of memory, addresses 3FF 8000H to 3FF AFFFH, are reserved for the internal RAM area. In the µPD703129 the 16 KB of addresses 3FF 8000H to 3FF BFFFH are provided as internal physical RAM.
Page 74: Figure 3-13: Internal Peripheral I/O Area
Chapter 3 CPU Function Internal peripheral I/O area 4 KB of memory, addresses 3FFF000H to 3FFFFFFH, is provided as an internal peripheral I/O area. Figure 3-13: Internal Peripheral I/O Area 3FF FFFFH Internal Peripheral I/O area (4 Kbytes) 3FF 0000H Peripheral I/O registers associated with the operation mode specification and the state monitoring for the internal peripherals I/O are all memory-mapped to the internal peripheral I/O area.
Page 75: Recommended Use Of Address Space
Chapter 3 CPU Function 3.5.2 Recommended use of address space The architecture of the V850E/CA2 requires that a register is utilized for address generation when accessing operand data in the data space. Operand data access from instruction can be directly exe- cuted at the address in this pointer register ±32 KB.
Page 76: Peripheral I/O Registers
Chapter 3 CPU Function 3.5.3 Peripheral I/O Registers Table 3-6: List of Peripheral I/O Registers (1/7) Bit Units Initial for Manipulation Address Function Register Name Symbol Value 1-bit 8-bit 16-bit × × FFFF F002 Port AH × × FFFF F008 Port CS undefined ×...
Page 77 Chapter 3 CPU Function Table 3-6: List of Peripheral I/O Registers (2/7) Bit Units Initial for Manipulation Address Function Register Name Symbol Value 1-bit 8-bit 16-bit × FFFF F0C0 DMA transfer count register 0 DBC0 undefined × FFFF F0C2 DMA transfer count register 1 DBC1 undefined ×...
Page 78 Chapter 3 CPU Function Table 3-6: List of Peripheral I/O Registers (3/7) Bit Units Initial for Manipulation Address Function Register Name Symbol Value 1-bit 8-bit 16-bit × × FFFF F13E Interrupt control register 23 CCG13IC × × FFFF F140 Interrupt control register 24 CCG14IC ×...
Page 79 Chapter 3 CPU Function Table 3-6: List of Peripheral I/O Registers (4/7) Bit Units Initial for Manipulation Address Function Register Name Symbol Value 1-bit 8-bit 16-bit × × FFFF F1FA In-service Priority register ISPR × FFFF F1FC Command register PRCMD undefined ×...
Page 80 Chapter 3 CPU Function Table 3-6: List of Peripheral I/O Registers (5/7) Bit Units Initial for Manipulation Address Function Register Name Symbol Value 1-bit 8-bit 16-bit × × FFFF F554 Timer D1 Control register TMCD1 × × FFFF F560 Watch timer mode register ×...
Page 81 Chapter 3 CPU Function Table 3-6: List of Peripheral I/O Registers (6/7) Bit Units Initial for Manipulation Address Function Register Name Symbol Value 1-bit 8-bit 16-bit × FFFF F68A Timer Count Register 1 TMG11 0000H × FFFF F68C Capture/Compare register 0 GCC10 0000H ×...
Page 82 Chapter 3 CPU Function Table 3-6: List of Peripheral I/O Registers (7/7) Bit Units Initial for Manipulation Address Function Register Name Symbol Value 1-bit 8-bit 16-bit CHKSR_ × × FFFF FA46 Clock selection register CHKSR1 BRGC1 × × FFFF FA47 Baudrate definition register BRGC1 CSIM_C ×...
Page 83: Programmable Peripheral I/O Registers
Chapter 3 CPU Function 3.5.4 Programmable peripheral I/O registers In the V850E/CA2, the 16 KB area of x0000H to x3FFFH is provided as a programmable peripheral I/O area. In this area, the area between x0000H and x1200H is used exclusively for the FCAN controller. The internal bus of the V850E/CA2 becomes active when - the peripheral I/O register area (3FF F000H to 3FF FFFFH) or - the programmable peripheral I/O register area (xxxx m000H to xxxx nFFFH)
Page 84: Figure 3-16: Peripheral Area Selection Control Register (Bpc)
Chapter 3 CPU Function Peripheral area selection control register (BPC) The BPC register is a 16-bit register that specifies the base address or the programmable peripheral area. This register can be read/written in 16-bit units. Figure 3-16: Peripheral Area Selection Control Register (BPC) Initial Address value...
Page 85: Table 3-7: List Of Programmable Peripheral I/O Registers
Chapter 3 CPU Function A list of the programmable peripheral I/O registers is shown below: Table 3-7: List of programmable peripheral I/O registers (1/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn000H CAN message event pointer 000 M_EVT000 Undefined xxxxn001H...
Page 86 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (2/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn040H CAN message event pointer 020 M_EVT020 Undefined xxxxn041H CAN message event pointer 021 M_EVT021 Undefined xxxxn042H...
Page 87 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (3/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn082H CAN message event pointer 042 M_EVT042 Undefined xxxxn083H CAN message event pointer 043 M_EVT043 Undefined xxxxn084H...
Page 88 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (4/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn0C4H CAN message data length register 06 M_DLC06 Undefined xxxxn0C5H CAN message control register 06 M_DTRL06 Undefined xxxxn0C6H...
Page 89 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (5/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn106H CAN message time stamp register 08 M_TIME08 Undefined xxxxn108H CAN message data register 080 M_DATA080 Undefined xxxxn109H...
Page 90 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (6/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn149H CAN message data register 101 M_DATA101 Undefined xxxxn14AH CAN message data register 102 M_DATA102 Undefined xxxxn14BH...
Page 91 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (7/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn18BH CAN message data register 123 M_DATA123 Undefined xxxxn18CH CAN message data register 124 M_DATA124 Undefined xxxxn18DH...
Page 92 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (8/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn1CDH CAN message data register 145 M_DATA145 Undefined xxxxn1CEH CAN message data register 146 M_DATA146 Undefined xxxxn1CFH...
Page 93 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (9/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn20FH CAN message data register 167 M_DATA167 Undefined xxxxn210H CAN message ID register L16 M_IDL16 Undefined xxxxn212H...
Page 94 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (10/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn252H CAN message ID register H18 M_IDH18 Undefined xxxxn254H CAN message configuration register 18 M_CONF18 Undefined xxxxn255H...
Page 95 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (11/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn295H CAN message status register 20 M_STAT20 Undefined xxxxn296H CAN status set/cancel register 20 SC_STAT20 0000H xxxxn2A0H...
Page 96 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (12/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn2E0H CAN message event pointer 230 M_EVT230 Undefined xxxxn2E1H CAN message event pointer 231 M_EVT231 Undefined xxxxn2EH...
Page 97 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (13/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn322H CAN message event pointer 252 M_EVT252 Undefined xxxxn323H CAN message event pointer 253 M_EVT253 Undefined xxxxn324H...
Page 98 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (14/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn364H CAN message data length register 27 M_DLC27 Undefined xxxxn365H CAN message control register 27 M_CTRL27 Undefined xxxxn366H...
Page 99 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (15/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn3A6H CAN message time stamp register 29 M_TIME29 Undefined xxxxn3A8H CAN message data register 290 M_DATA290 Undefined xxxxn3A9H...
Page 100 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (16/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn3E9H CAN message data register 311 M_DATA311 Undefined xxxxn3EAH CAN message data register 312 M_DATA312 Undefined xxxxn3EBH...
Page 101 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (17/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit xxxxn1056H CAN1 error counter register C1ERC 0000H Note 1 xxxxn1058H CAN1 interrupt enable register C1IE R/(W) 0000H...
Page 102 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers (18/18) Bit Units for Manipulation Address Function Register Name Symbol Initial Value 1-bit 8-bit 16-bit Note 2 xxxxn10DEH CAN3 synchronization control register C3SYNC 0218H Note 2 xxxxn1100H CAN4 address mask register L0 C4MASKL0 Undefined Note 2...
Page 103: Specific Registers
(PHS). The V850E/CA2 Jupiter has five specific registers, the clock control register (CKC), the watchdog timer clock control register (WCC), the processor clock control register (PCC) and the power save control register (PSC).
Page 104: Command Register (Prcmd)
Chapter 3 CPU Function 3.6.1 Command Register (PRCMD) This command register (PRCMD) is to protect the registers that may have a significant influence on the application system (PSC, PSM) from an inadvertent write access, so that the system does not stop in case of a program hang-up.
Page 105: Peripheral Command Register (Phcmd)
Chapter 3 CPU Function 3.6.2 Peripheral Command Register (PHCMD) This command register (PHCMD) is to protect the registers that may have a significant influence on the application system (CKC, WCC, PCC) from an inadvertent write access, so that the system does not stop in case of a program hang-up.
Page 106: Peripheral Status Register (Phs)
Chapter 3 CPU Function 3.6.3 Peripheral Status Register (PHS) The flag PRERR in the peripheral status register PHS indicates protection error occurrence. This register can be read/written in 8-bit units or bit-wise. Figure 3-19: Peripheral Status Register (PHS) Format Address At Reset PRERR FFFFF802H Protection error detection:...
Page 107: Internal Peripheral Function Wait Control Register (Vswc)
Chapter 3 CPU Function 3.6.4 Internal peripheral function wait control register (VSWC) This register inserts wait states to the internal access of peripheral SFRs. This register can be read or written in 1-bit and 8-bit units. Figure 3-20: Internal peripheral function wait control register (VSWC) Format Reset Address Value...
Page 108: Table 3-8: The Values Of Vswc Register Depending On System Clock
Chapter 3 CPU Function Table 3-8: The Values of VSWC Register depending on System Clock System Clock Setup Wait Strobe Wait VSWC 4.0 MHz < f < 16.6 MHz 16.6 MHz < f < 25.0 MHz 25.0 MHz < f <...
Page 109: Chapter 4 Bus Control Function
Chapter 4 Bus Control Function The V850E/CA2 Jupiter is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 4.1 Features • 16-bit/8-bit data bus sizing function • 8 chip areas select function - 3 chip area select signals externally available (CS0,CS3 and CS4) •...
Page 110: Memory Block Function
Chapter 4 Bus Control Function 4.3 Memory Block Function The 64 MB memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB units. Figure 4-1: Memory Block Function 3FFF FFFH 3FFF FFFH Block 15 Internal peripheral I/O area (4 Kbytes) (2 Mbytes) 3E00 000H 3FFF 000H...
Page 111: Chip Select Control Function
Chapter 4 Bus Control Function 4.3.1 Chip Select Control Function The 64 MB memory area can be divided into 2 MB, 4 MB and 8 MB memory blocks by the chip area selection control registers 0 and 1 (CSC0, CSC1) to control the chip select signals. The memory area can be effectively used by dividing the memory area into memory blocks using the chip select control function.
Page 112 Chapter 4 Bus Control Function Figure 4-2: Chip Area Select Control Registers 0, 1 (2/2) Bit Position Bit Name Function 15 to 0 CSn0 to Chip Select CSn3 Enables chip select. (n = 0 to 7) CSnm CS Operation CS00 CS0 active during block 0 access CS01 CS0 active during block 1 access.
Page 113: Programmable Peripheral I/O Registers
Chapter 4 Bus Control Function 4.4 Programmable peripheral I/O registers In the V850E/CA2, the 16 KB area of x0000H to x3FFFH is provided as a programmable peripheral I/O area. In this area, the area between x0000H and x11FFH is used exclusively for the FCAN controller. The internal bus of the V850E/CA2 becomes active when the peripheral I/O register area (FFFF000H to FFFFFFFH) or the programmable peripheral I/O register area (xxxxm000H to xxxxnFFFH) is accessed (m = xx00B, n = xx11B).
Page 114: Figure 4-4: Peripheral Area Selection Control Register (Bpc)
Chapter 4 Bus Control Function Peripheral area selection control register (BPC) This register can be read/written in 16-bit units. Figure 4-4: Peripheral Area Selection Control Register (BPC) Initial Address value BPC PA15 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 FFFFF064H 0000H Bit Position Bit Name Function...
Page 115: Bus Cycle Type Control Function
Chapter 4 Bus Control Function 4.5 Bus Cycle Type Control Function In the V850E/CA2 Jupiter, the following external devices can be connected directly to each memory block. • SRAM, external ROM, external I/O • Page ROM Connected external devices are specified by the bus cycle type configuration registers 0, 1 (BCT0, BCT1).
Page 116: Bus Access
Chapter 4 Bus Control Function 4.6 Bus Access 4.6.1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows. Table 4-1: Number of Bus Access Clocks Resources (Bus width) Internal Instruc- Internal RAM Peripheral I/O External memory tion Cache...
Page 117: Endian Control Function
Chapter 4 Bus Control Function 4.6.3 Endian control function The endian control function can be used to set processing of word data in memory either by the Big Endian method or the Little Endian method for each CS area selected with the chip select signal (CS0 to CS7).
Page 118: Cache Configuration
Chapter 4 Bus Control Function 4.7 Cache Configuration The cache configuration register (BHC) is used to set the cache memory configuration for each CS area selected by the chip select signals (CS0 to CS7). Cache configuration register (BHC) This register can be read or written in 16-bit units. Initial Address value...
Page 119: Bus Width
Chapter 4 Bus Control Function 4.7.1 Bus width The V850E/CA2 Jupiter accesses peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each type of access. Access all data in order starting from the lower order side.
Page 120 Chapter 4 Bus Control Function (c) When the data bus width is 16 bits (Big Endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 2n + 1 Byte data External Byte data External data bus data bus...
Page 121 Chapter 4 Bus Control Function Halfword access (16 bits) (a) When the bus width is 16 bits (Little Endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) 1-st Access 2-nd Access Address Address Address 2n + 1 2n + 1 2n + 2...
Page 122 Chapter 4 Bus Control Function (c) When the data bus width is 16 bits (Big Endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) 1-st Access 2-nd Access Address Address Address 2n + 2 2n + 1 2n + 1 Halfword...
Page 123 Chapter 4 Bus Control Function Word access (32 bits) (a) When the bus width is 16 bits (Little Endian) <1> Access to address 4n 1-st Access 2-nd Access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data External...
Page 124 Chapter 4 Bus Control Function <3> Access to address 4n + 2 1-st Access 2-nd Access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data External data bus data bus <4>...
Page 125 Chapter 4 Bus Control Function (b) When the bus width is 8 bits (Little Endian) <1> Access to address 4n 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data...
Page 126 Chapter 4 Bus Control Function <3> Access to address 4n + 2 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data External Word data External...
Page 127 Chapter 4 Bus Control Function (c) When the data bus width is 16 bits (Big Endian) <1> Access to address 4n 1-st Access 2-nd Access Address Addres 4n + 2 4n + 1 4n + 3 Word data External Word data External data bus data bus...
Page 128 Chapter 4 Bus Control Function <3> Access to address 4n + 2 1-st Access 2-nd Access Address Address 4n + 2 4n + 4 4n + 3 4n + 5 Word data External Word data External data bus data bus <4>...
Page 129 Chapter 4 Bus Control Function (d) When the data bus width is 8 bits (Big Endian) <1> Access to address 4n 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data...
Page 130 Chapter 4 Bus Control Function <3> Access to address 4n + 2 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data External Word data External...
Page 131: Wait Function
Chapter 4 Bus Control Function 4.8 Wait Function 4.8.1 Programmable wait function Data wait control registers 0, 1 (DWC0, DWC1) With the purpose of realizing easy interfacing with low-speed memory or with I/Os, it is possible to insert up to 7 data wait states with respect to the starting bus cycle for each CS area. The number of wait states can be specified by data wait control registers 0 and 1 (DWC0, DWC1) in programming.
Page 132 Chapter 4 Bus Control Function Address setup wait control register (ASC) The V850E/CA2 Jupiter allows insertion of address setup wait states before the T1 cycle of the SRAM or page ROM cycle. The number of address setup wait states can be set with the ASC register for each CS area.
Page 133: External Wait Function
Chapter 4 Bus Control Function 4.8.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by the external wait pin (WAIT) to synchronize with the external device. Just as with programmable waits, access to internal ROM, internal RAM, and internal peripheral I/O areas cannot be controlled by external waits.
Page 134: Idle State Insertion Function
Chapter 4 Bus Control Function 4.9 Idle State Insertion Function To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted into the cur- rent bus cycle after the T2 state to meet the data output float delay time (tdf) on memory read access for each CS space.
Page 135: Bus Priority Order
Chapter 4 Bus Control Function 4.10 Bus Priority Order There are three external bus cycles: DMA cycle, operand data access and instruction fetch. As for the priority order, the highest priority has the DMA cycle, instruction fetch, and operand data access, in this order.
Page 136: Boundary Operation Conditions
4.11.2 Data space The V850E/CA2 Jupiter is provided with an address misalign function. Through this function, regardless of the data format (word data, halfword data, or byte data), data can be placed in all addresses. However, in the case of word data and halfword data, if data are not sub- jected to boundary alignment, the bus cycle will be generated a minimum of 2 times and bus efficiency will drop.
Page 137: Chapter 5 Memory Access Control Function
Chapter 5 Memory Access Control Function 5.1 SRAM, External ROM, External I/O Interface 5.1.1 Features • Access to SRAM takes a minimum of 2 states. • Up to 7 states of programmable data waits can be inserted through setting of the DWC0 and DWC1 registers.
Page 138: Sram Connections
Chapter 5 Memory Access Control Function 5.1.2 SRAM connections An example of connection to SRAM is shown below. Figure 5-1: Example of Connection to SRAM (a) When data bus width is 16 bits A1 to A17 A1 to A17 D0 to D15 D1 to D16 V850E/CA2 2-Mbit SRAM...
Page 139: Sram, External Rom, External I/O Access
Chapter 5 Memory Access Control Function 5.1.3 SRAM, external ROM, external I/O access Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/6) (a) During read System CLK Address Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) D0 to D15 (I/O) Data...
Page 140 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (2/6) (b) During read (address setup wait, idle state insertion) TASW System CLK Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) Data D0 to D15 (I/O) WAIT (input)
Page 141 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (3/6) (c) During write System CLK Address Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) Data Data D0 to D15 (I/O) WAIT (input) Remarks: 1.
Page 142 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (4/6) (d) During write (address setup wait, idle state insertion) TASW System CLK Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) D0 to D15 (I/O) Data WAIT (input)
Page 143 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (5/6) → (e) When read write operation System CLK Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) D0 to D15 (I/O) Data Data WAIT (input)
Page 144 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (6/6) → (f) When write read operation System CLK Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) Data D0 to D15 (I/O) Data WAIT (input) Remarks: 1.
Page 145: Page Rom Controller (Romc)
Chapter 5 Memory Access Control Function 5.2 Page ROM Controller (ROMC) The page ROM controller (ROMC) is provided for access to ROM (page ROM) with the page access function. Comparison of addresses with the immediately preceding bus cycle is carried out and wait control for normal access (off-page) and page access (on-page) is executed.
Page 146: Page Rom Connections
Chapter 5 Memory Access Control Function 5.2.2 Page ROM connections Examples of page ROM connections are shown below. Figure 5-3: Example of Page ROM Connections (a) In case of 16-bit data bus width A1 to A20 A0 to A19 D0 to D15 O1 to O16 V850E/CA2 16-Mbit page ROM...
Page 147: On-Page/Off
Chapter 5 Memory Access Control Function 5.2.3 On-page/off-page judgment Whether a page ROM cycle is on-page or off-page is judged by latching the address of the previous cycle and comparing it with the address of the current cycle. Through the page ROM configuration register (PRC), according to the configuration of the connected page ROM and the number of continuously readable bits, one of the addresses (A3 to A6) is set as the masking address (no comparison is made).
Page 148 Chapter 5 Memory Access Control Function Figure 5-4: On-Page/Off-Page Judgment during Page ROM Connection (2/2) (c) In case of 32-Mbit (2 M × 16 bits) page ROM (16-word page access) Internal address latch (immediately preceding address) PRC register setting Comparison V850E/CA2 address output Page ROM address...
Page 149: Page Rom Configuration Register (Prc)
Chapter 5 Memory Access Control Function 5.2.4 Page ROM configuration register (PRC) This register specifies whether page ROM on-page access is enabled or disabled. If on-page access is enabled, the masking address (no comparison is made) out of the addresses (A3 to A6) corresponding to the configuration of the page ROM being connected to and the number of bits that can be read con- tinuously, as well as the number of waits corresponding to the internal system clock, are set.
Page 150: Page Rom Access
Chapter 5 Memory Access Control Function 5.2.5 Page ROM access Figure 5-6: Page ROM Access Timing (1/4) (a) During read (when half word/word access with 8-bit bus width or when word access with 16-bit bus width) System CLK Off-page address On-page address A0 to A23 (output) CSn (output)
Page 151 Chapter 5 Memory Access Control Function Figure 5-6: Page ROM Access Timing (2/4) (b) During read (when byte access with 8-bit bus width or when byte/half word access with 16-bit bus width) System CLK Off-page address On-page address A0 to A23 (output) CSn (output) RD (output) UWR (output)
Page 152 Chapter 5 Memory Access Control Function Figure 5-6: Page ROM Access Timing (3/4) (c) During read (address setup wait, idle state insertion) (when half word/word access with 8-bit bus width or when word access with 16-bit bus width) TASW TASW System CLK Off-page address On-page address...
Page 153 Chapter 5 Memory Access Control Function Figure 5-6: Page ROM Access Timing (4/4) (d) During read (address setup wait, idle state insertion) (when byte access with 8-bit bus width or when byte/half word access with 16-bit bus width) TASW TASW System CLK Off-page address On-page address...
Page 154 [MEMO] Preliminary User’s Manual U15839EE1V0UM00...
Page 155: Chapter 6 Instruction Cache
Chapter 6 Instruction Cache The V850E/CA2 Jupiter device contains a 4 KByte 2-way-associative instruction memory (iCache) to improve the system’s instruction execution speed and performance. 6.1 Features • Use of Least Recently Used (LRU) algorithm. The LRU algorithm replaces the cache line, that has not been used since the longest time.
Page 156: Configuration
Chapter 6 Instruction Cache 6.2 Configuration To improve the instruction execution speed and the total system’s performance, the V850E/CA2 Jupiter device provides a 4 KByte 2-way associative instruction cache memory. The instruction cache is organ- ized as 4 words x 128 entries x 2 ways.
Page 157: Four Kbytes 2-Way Set-Associative Instruction Cache
Chapter 6 Instruction Cache 6.2.1 Four Kbytes 2-way set-associative Instruction Cache The data memory of a 4 KBytes 2-way set-associative instruction cache has two ways, each consisting of a block of 128 entries of 4 words per line, for a total capacity of 4 KB. Figure 6-2: Configuration of 4 KB 2-Way Set-Associative Instruction Cache INDEX Data part (4 words)
Page 158: Control Registers
Chapter 6 Instruction Cache 6.3 Control Registers Instruction Cache Control Register (ICC) The ICC register is the register that sets two types of functions, tag clear and autofill. The ICC reg- ister can be read or written in 16-bit, 8-bit or 1-bit units. Figure 6-3: Instruction Cache Control Register (ICC) Initial Address...
Page 159: Figure 6-4: Instruction Cache Data Configuration Register (Icd)
Chapter 6 Instruction Cache Instruction Cache Data Configuration Register (ICD) The ICD register sets the address of the memory area to be autofilled when using the autofill func- tion. The ICD register can be read or written in 16-bit units. Figure 6-4: Instruction Cache Data Configuration Register (ICD) Initial Address...
Page 160: Instruction Cache Operation
Chapter 6 Instruction Cache 6.4 Instruction Cache Operation Instruction Cache Basic Operation The instruction cache automatically performs a caching operation whenever there is a fetch access to a cacheable area set using the cache configuration register BHC. Operation on Instruction Cache Hit On a fetch access from memory, the CPU outputs the instruction fetch request and the concerned address to the instruction cache.
Page 161: Figure 6-7: Operation On Instruction Cache Miss
Chapter 6 Instruction Cache Operation on Instruction Cache Miss On a fetch access from memory, the CPU outputs the instruction fetch request and the concerned address to the instruction cache. If an instruction cache miss occurs due to the address not existing in the instruction cache, the fetch request and the address will be output from the instruction cache to the BCU.
Page 162: Figure 6-8: Refill Sequence To Instruction Cache (16-Bit Data Bus)
Chapter 6 Instruction Cache Figure 6-8: Refill Sequence to Instruction Cache (16-bit Data Bus) Data part (4 words) Lower address Higher address 1 word 1 word 1 word 1 word <8> (Addr.+EH) <7> (Addr.+CH) <6> (Addr.+AH) <5> (Addr.+8H) <4> (Addr.+6H) <3> (Addr.+4H) <2> (Addr.+2H) <1> (Addr.+0H) entries Remarks: 1.
Page 163 Chapter 6 Instruction Cache Tag Clear Function The tag clear function clears (invalidates) the tags of one way. In addition, it automatically clears (invalidates) the tags of all ways on a system reset. Instruction cache tag clear performs the follow- ing procedure: Read the instruction cache control register (ICC) and confirm that bits 0 and 1 (TCLR0, TCLR1) are all cleared.
Page 164 Chapter 6 Instruction Cache Sample Coding: <1> 0x3, r2 <2> LOP0: <3> Id.h ICC[r0], r1 <4> r0, r1 <5> LOP0 <6> st.h r2, ICC[r0] <7> LOP1: -- First TAG clear <8> Id.h ICC[r0], r1 <9> r0, r1 <10> LOP1 <11> st.h r2, ICC[r0] <12>...
Page 165 Chapter 6 Instruction Cache Autofill Function (Way 0 only) The autofill function automatically fills instructions for one way. Once autofilled, a way is automati- cally locked and write is disabled and it operates the same as a ROM that is accessible in one cycle.
Page 166: Instruction Cache Initialisation
Chapter 6 Instruction Cache 6.5 Instruction Cache Initialisation The instruction cache settings must be performed using the following procedure with the initial settings of the user program immediately following a system reset. Wait until the contents of the ICC register becomes 0000H (TAG initialization is completed). Clear all bits of the ICI register using the following instruction: st.h r0, 0xfffff072[r0]...
Page 167: Operating Precautions
Chapter 6 Instruction Cache 6.6 Operating Precautions Operation on Reset: At the time of a reset, tags are automatically cleared (invalidated), which puts the next data replacement in a state of being performed from way 0. Therefore, if there is an access to the instruction cache within a period of as many clock cycles as the number of lines after a reset, the CPU stops until the tags are cleared (become valid).
Page 168: Figure 6-9: Icache Area Setting Example
Chapter 6 Instruction Cache Access to memory boundary: If adjacent chip select (CSn) areas are a cacheable area and an uncacheable area, continuous access across the memory boundary is possible only by using a branch instruction. Operation is not guaranteed if the memory boundary is continuously accessed by instruction other than a branch instruction.
Page 169: Chapter 7 Dma Functions (Dma Controller)
Chapter 7 DMA Functions (DMA Controller) The V850E/CA2 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O or among I/Os, based on DMA requests issued by the on-chip peripheral I/O, or software triggers (memory refers to internal RAM). 7.1 Features •...
Page 170: Control Registers
Chapter 7 DMA Functions (DMA Controller) 7.2 Control Registers 7.2.1 DMA source address registers H0 to H3 (DSAH0 to DSAH3) These registers are used to set the DMA source addresses (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DSAHn and DSALn. Since these registers are configured as 2-stage FIFO buffer registers, a new source address for DMA transfer can be specified during DMA transfer (refer to 7.3 Next Address Setting Function).
Page 171: Figure 7-2: Dma Source Address Registers Dsal0 To Dsal3 (Dsal0 To Dsal3)
Chapter 7 DMA Functions (DMA Controller) DMA source address registers L0 to L3 (DSAL0 to DSAL3) These registers can be read/written in 16-bit units. Figure 7-2: DMA Source Address Registers DSAL0 to DSAL3 (DSAL0 to DSAL3) Address Initial value DSAL0 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF080H undef.
Page 172: Dma Destination Address Registers H0 To H3 (Ddah0 To Ddah3)
Chapter 7 DMA Functions (DMA Controller) 7.2.2 DMA destination address registers H0 to H3 (DDAH0 to DDAH3) These registers are used to set the DMA destination address (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DDAHn and DDALn. Since these registers are configured as 2-stage FIFO buffer registers, a new destination address for DMA transfer can be specified during DMA transfer (refer to 7.3 Next Address Setting Function).
Page 173: Figure 7-4: Dma Destination Address Registers L0 To L3 (Ddal0 To Ddal3)
Chapter 7 DMA Functions (DMA Controller) DMA destination address registers L0 to L3 (DDAL0 to DDAL3) These registers can be read/written in 16-bit units. Figure 7-4: DMA Destination Address Registers L0 to L3 (DDAL0 to DDAL3) Address Initial value DDAL0 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF084H undef.
Page 174: Dma Transfer Count Registers 0 To 3 (Dbc0 To Dbc3)
Chapter 7 DMA Functions (DMA Controller) 7.2.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) These 16-bit registers are used to set the transfer counts for DMA channels n. They store the remaining transfer counts during DMA transfer. Since these registers are configured as 2-stage FIFO buffer registers, a new DMA transfer count for DMA transfer can be specified during DMA transfer (refer to 7.3 Next Address Setting Function).
Page 175: Dma Addressing Control Registers 0 To 3 (Dadc0 To Dadc3)
Chapter 7 DMA Functions (DMA Controller) 7.2.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) These 16-bit registers are used to control the DMA transfer modes for DMA channel n. They can be read/written in 16-bit units. Figure 7-6: DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3) (1/2) Address Initial value...
Page 176 Chapter 7 DMA Functions (DMA Controller) Figure 7-6: DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3) (2/2) Bit Position Bit Name Function 5, 4 DAD1, Sets the count direction of the destination address for DMA channel n (n = 0 to 3). DAD0 DAD1 DAD0...
Page 177: Dma Channel Control Registers 0 To 3 (Dchc0 To Dchc3)
Chapter 7 DMA Functions (DMA Controller) 7.2.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n. These registers can be read/written in 8-bit or 1-bit units. (However, bit 7 is read only and bits 2 and 1 are write only.
Page 178: Dma Disable Status Register (Ddis)
Chapter 7 DMA Functions (DMA Controller) 7.2.6 DMA disable status register (DDIS) This register holds the contents of the ENn bit of the DCHCn register during NMI input. This register is read-only in 8-bit or 1-bit units. Figure 7-8: DMA Disable Status Register (DDIS) Address Initial value...
Page 179: Dma Trigger Factor Register 0 (Dtfr0)
Chapter 7 DMA Functions (DMA Controller) 7.2.8 DMA trigger factor register 0 (DTFR0) This 8-bit registers is used to control the DMA transfer start trigger of DMA channel 0 through interrupt requests from on-chip peripheral I/O. The interrupt requests set with these registers serve as DMA transfer start factors.
Page 180: Dma Trigger Factor Register 1 (Dtfr1)
Chapter 7 DMA Functions (DMA Controller) 7.2.9 DMA trigger factor register 1 (DTFR1) This 8-bit registers is used to control the DMA transfer start trigger of DMA channel 1 through interrupt requests from on-chip peripheral I/O. The interrupt requests set with these registers serve as DMA transfer start factors.
Page 181: Dma Trigger Factor Register 2 (Dtfr2)
Chapter 7 DMA Functions (DMA Controller) 7.2.10 DMA trigger factor register 2 (DTFR2) This 8-bit registers is used to control the DMA transfer start trigger of DMA channel 2 through interrupt requests from on-chip peripheral I/O. The interrupt requests set with these registers serve as DMA transfer start factors.
Page 182: Dma Trigger Factor Register 3 (Dtfr3)
Chapter 7 DMA Functions (DMA Controller) 7.2.11 DMA trigger factor register 3 (DTFR3) This 8-bit registers is used to control the DMA transfer start trigger of DMA channel 3 through interrupt requests from on-chip peripheral I/O. The interrupt requests set with these registers serve as DMA transfer start factors.
Page 183: Next Address Setting Function
Chapter 7 DMA Functions (DMA Controller) 7.3 Next Address Setting Function The DMA source address registers (DSAHn, DSALn), DMA destination address registers (DDAHn, DDALn), and DMA transfer count register (DBCn) are buffer registers with a 2-stage FIFO configuration. When the terminal count is issued, these registers are automatically rewritten with the value that was set immediately before.
Page 184: Dma Bus States
Chapter 7 DMA Functions (DMA Controller) 7.4 DMA Bus States 7.4.1 Types of bus states The DMAC bus states consist of the following 13 states. TI state The TI state is an idle state, during which no access request is issued. T0 state This is the DMA transfer ready state (state in which a DMA transfer request has been issued and the bus mastership is acquired for the first DMA transfer).
Page 185 Chapter 7 DMA Functions (DMA Controller) (11) T1FHI state Note This is the last state of a flyby transfer and the DMAC is awaiting the end of the transfer. After the T1FHI start, the bus is released and the DMAC transitions to the TE state (12) T2FH state Note This is the state in which the DMAC judges whether or not to continue flyby...
Page 186: Dmac Bus Cycle State Transition
Chapter 7 DMA Functions (DMA Controller) 7.4.2 DMAC bus cycle state transition Except for the block transfer mode, each time the processing for a DMA transfer is completed, the bus mastership is released. Figure 7-15: DMAC Bus Cycle State Transition Diagram (a) Two-cycle transfer T1RI T2RI...
Page 187: Transfer Mode
Chapter 7 DMA Functions (DMA Controller) 7.5 Transfer Mode 7.5.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword/word transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs.
Page 188: Figure 7-18: Single Transfer Example 3
Chapter 7 DMA Functions (DMA Controller) Figure 7-18, “Single Transfer Example 3,” on page 188 shows a DMA transfer example in single transfer mode in which a lower priority DMA transfer request is generated within one clock after the end of a sin- gle transfer.
Page 189: Single-Step Transfer Mode
Chapter 7 DMA Functions (DMA Controller) 7.5.2 Single-step transfer mode In single-step transfer mode, the DMAC releases the bus at each byte/halfword/word transfer. Once a DMA transfer request signal is received, transfer is performed again. This operation continues until a terminal count occurs.
Page 190: Line Transfer Mode
Chapter 7 DMA Functions (DMA Controller) 7.5.3 Line Transfer Mode In line transfer mode, the DMAC releases the bus after every four byte, halfword or word transfer. If there is a subsequent DMA transfer request, four transfers are performed again. This operation contin- ues until a terminal count occurs.
Page 191: Figure 7-24: Line Transfer Example 3
Chapter 7 DMA Functions (DMA Controller) Figure 7-24, “Line Transfer Example 3,” on page 191 and Figure 7-25, “Line Transfer Example 4,” on page 191 shows DMAC transfers in line transfer mode in which a lower priority DMA transfer request is generated within one clock after the end of a line transfer.
Page 192: Block Transfer Mode
Chapter 7 DMA Functions (DMA Controller) 7.5.4 Block transfer mode In the block transfer mode, once transfer begins, the DMAC continues the transfer operation without releasing the bus until a terminal count occurs. No other DMA requests are acknowledged during block transfer.
Page 193: Transfer Types
Chapter 7 DMA Functions (DMA Controller) 7.6 Transfer Types 7.6.1 Two-cycle transfer In two-cycle transfer, data transfer is performed in two cycles, a read cycle (source to DMAC) and a write cycle (DMAC to destination). In the first cycle, the source address is output and reading is performed from the source to the DMAC. In the second cycle, the transfer destination address is output and writing is performed from the DMAC to the transfer destination.
Page 194: Dma Channel Priorities
Chapter 7 DMA Functions (DMA Controller) 7.8 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 These priorities are valid in the TI state only. In the block transfer mode, the channel used for transfer is never switched.
Page 195: Forcible Interruption
Chapter 7 DMA Functions (DMA Controller) 7.10 Forcible Interruption DMA transfer can be forcibly interrupted by NMI input during DMA transfer. At such a time, the DMAC clears the ENn bit of the DCHCn register of all channels and the DMA transfer disabled state is entered. An NMI request can then be acknowledged after the DMA transfer executed during NMI input is termi- nated.
Page 196: Forcible Termination
Chapter 7 DMA Functions (DMA Controller) 7.11 Forcible Termination In addition to the forcible interruption operation by means of the NMI input, DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register. The following is an example of the operation of a for- cible termination.
Page 197: Dma Transfer Completion
Chapter 7 DMA Functions (DMA Controller) Figure 7-29, “DMA Transfer Forcible Termination Example 2,” on page 197 shows a forcible termination of a block transfer operation of DMA channel 1. A transfer containing a new configuration is executed. Figure 7-29: DMA Transfer Forcible Termination Example 2 DSAL1, DSAH1, DSAL1, DSAH1, DCHC1...
Page 198: Precautions
Chapter 7 DMA Functions (DMA Controller) 7.13 Precautions Memory boundary The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA objects (internal RAM, or peripheral I/O) during DMA transfer. Transfer of misaligned data DMA transfer of 16-bit/32-bit bus width misaligned data is not supported.
Page 199: Chapter 8 Interrupt/Exception Processing Function
Chapter 8 Interrupt/Exception Processing Function The V850E/CA2 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 64 maskable and three non-maskable interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 200: Table 8-1: Interrupt/Exception Source List
Chapter 8 Interrupt/Exception Processing Function Table 8-1: Interrupt/Exception Source List (1/3) Interrupt/Exception Source Classifi- Default Exception Handler Restored Type Controlling Generating cation Priority Code Address Name Generating Source Register Unit Reset Interrupt RESET – RESET input – 0000H 00000000H undef. NMI0 –...
Page 201 Chapter 8 Interrupt/Exception Processing Function Table 8-1: Interrupt/Exception Source List (2/3) Interrupt/Exception Source Classifi- Default Exception Handler Restored Type Controlling Generating cation Priority Code Address Name Generating Source Register Unit Interrupt INTCCC00 CCC0IC CC coincidence Channel 0 Timer C0 0230H 00000230H next PC Interrupt INTCCC01 CCC1IC CC coincidence Channel 1...
Page 202 Chapter 8 Interrupt/Exception Processing Function Table 8-1: Interrupt/Exception Source List (3/3) Interrupt/Exception Source Classifi- Default Exception Handler Restored Type Controlling Generating cation Priority Code Address Name Generating Source Register Unit DMA Channel 1 transfer Interrupt INTDMA1 DMA1IC DMA1 03D0H 000003D0H nextPC completed DMA Channel 2 transfer Interrupt INTDMA2 DMA2IC...
Page 203: Non-Maskable Interrupts
Chapter 8 Interrupt/Exception Processing Function 8.2 Non-Maskable Interrupts A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. Non-maskable interrupts of V850E/CA2 are available for the following two requests: • NMI pin input •...
Page 204: Figure 8-1: Example Of Non-Maskable Interrupt Request Acknowledgement Operation (1/2)
Chapter 8 Interrupt/Exception Processing Function Figure 8-1: Example of Non-Maskable Interrupt Request Acknowledgement Operation (1/2) (a) Multiple NMI requests generated at the same time NMI0 and NMIWDT requests generated simultaneously Main routine NMIWDT servicing NMI0 and NMIWDT requests System reset (generated simultaneously) Preliminary User’s Manual U15839EE1V0UM00...
Page 205 Chapter 8 Interrupt/Exception Processing Function Figure 8-1: Example of Non-Maskable Interrupt Request Acknowledgement Operation (2/2) (b) NMI request generated during NMI servicing NMI being NMI request generated during NMI servicing serviced NMI0 NMIWDT NMI0 request generated during NMIWDT request generated NMI0 NMI0 servicing during NMI0 servicing...
Page 206: Operation
Chapter 8 Interrupt/Exception Processing Function 8.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers con- trol to the handler routine: Saves the restored PC to FEPC. Saves the current PSW to FEPSW. Writes exception code 0010H to the higher halfword (FECC) of ECR. Sets the NP and ID bits of the PSW and clears the EP bit.
Page 207: Restore
Chapter 8 Interrupt/Exception Processing Function 8.2.2 Restore NMI0 Execution is restored from the non-maskable interrupt (NMI0) processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>...
Page 208: Non-Maskable Interrupt Status Flag (Np)
Chapter 8 Interrupt/Exception Processing Function 8.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execu- tion. This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 209: Maskable Interrupts
Chapter 8 Interrupt/Exception Processing Function 8.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850E/CA2 has 63 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 210: Figure 8-6: Maskable Interrupt Processing
Chapter 8 Interrupt/Exception Processing Function Figure 8-6: Maskable Interrupt Processing INT input INTC accepted xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 211: Restore
Chapter 8 Interrupt/Exception Processing Function 8.3.2 Restore Recovery from maskable interrupt processing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0.
Page 212: Priorities Of Maskable Interrupts
Chapter 8 Interrupt/Exception Processing Function 8.3.3 Priorities of maskable interrupts The V850E/CA2 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 213: Figure 8-8: Example Of Processing In Which Another Interrupt Request Is Issued While An Interrupt Is Being Processed (1/2)
Chapter 8 Interrupt/Exception Processing Function Figure 8-8: Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Processed (1/2) Main routine Processing of a Processing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the (level 3) (level 2) priority of b is higher than that of a and interrupts are...
Page 214 Chapter 8 Interrupt/Exception Processing Function Figure 8-8: Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Processed (2/2) Main routine Processing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 215: Figure 8-9: Example Of Processing Interrupt Requests Simultaneously Generated
Chapter 8 Interrupt/Exception Processing Function Figure 8-9: Example of Processing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Processing of interrupt request b Interrupt request b and c are NMI request Interrupt request c (level 1) acknowledged first according to their priorities.
Page 216: Interrupt Control Register (Xxic)
Chapter 8 Interrupt/Exception Processing Function 8.3.4 Interrupt control register (xxIC) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the con- trol conditions for each maskable interrupt request. This register can be read/written in 8-bit or 1-bit units. Figure 8-10: Interrupt Control Register (xxIC) Initial Address...
Page 217: Table 8-2: Addresses And Bits Of Interrupt Control Registers
Chapter 8 Interrupt/Exception Processing Function Table 8-2: Addresses and Bits of Interrupt Control Registers (1/2) Address Register FFFFF110H WTIC WTIF WTMK WTPR2 WTPR1 WTPR0 FFFFF112H TMD0IC TMD0IF TMD0MK TMD0PR2 TMD0PR1 TMD0PR0 FFFFF114H TMD1IC TMD1IF TMD1MK TMD1PR2 TMD1PR1 TMD1PR0 FFFFF116H WTIIC WTIIF WTIMK WTIPR2...
Page 218 Chapter 8 Interrupt/Exception Processing Function Table 8-2: Addresses and Bits of Interrupt Control Registers (2/2) Address Register FFFFF166H CSI0IC CSI0IF CSI0MK CSI0PR2 CSI0PR1 CSI0PR0 FFFFF168H CSI1IC CSI1IF CSI1MK CSI1PR2 CSI1PR1 CSI1PR0 FFFFF16AH CSI2IC CSI2IF CSI2MK CSI2PR2 CSI2PR1 CSI2PR0 FFFFF16CH SER0IC SER0IF SER0MK SER0PR2...
Page 219: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
Chapter 8 Interrupt/Exception Processing Function 8.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) These registers set the interrupt mask state for the maskable interrupts. The xxMK bit of the IMR0 to IMR3 registers is equivalent to the xxMK bit of the xxIC register. IMRm registers can be read/written in 16-bit units (m = 0 to 3).
Page 220: In-Service Priority Register (Ispr)
Chapter 8 Interrupt/Exception Processing Function 8.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an inter- rupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 221: Noise Elimination Circuit
Chapter 8 Interrupt/Exception Processing Function 8.4 Noise Elimination Circuit V850E/CA2 is provided with input filter for noise suppression for ports P3 to P5 and on all interrupt and timer G, timer C control inputs. For peripheral interrupts, programmable edge detection is available. Inputs for Timer G are equipped with edge detection and need only noise suppression.
Page 222: Analog Filter
Chapter 8 Interrupt/Exception Processing Function 8.4.1 Analog Filter The analog filter consists of a comparator stage, which compares the input pin level against a delayed input pin level. The filter output follows the filter input, if this compare operation matches. 8.4.2 Interrupt Trigger Mode Selection The valid edge of the INTP pins can be selected by the program.
Page 223: Interrupt Edge Detection Control Registers
Chapter 8 Interrupt/Exception Processing Function 8.4.3 Interrupt Edge Detection Control Registers Valid interrupt edges can be selected by INTM0 to INTM3 registers. Masking of interrupts is done inside the concerning interrupt control registers xxIC. Interrupt mode register 0 (INTM0) Figure 8-17: Interrupt Mode Register 0 (IMTM0) Address Initial value...
Page 224: Figure 8-18: Interrupt Mode Register 1 (Imtm1)
Chapter 8 Interrupt/Exception Processing Function Interrupt mode register 1 (INTM1) Figure 8-18: Interrupt Mode Register 1 (IMTM1) Address Initial value INTM1 ES071 ES070 ES061 ES060 ES051 ES050 ES041 ES040 FFFFF882H Bit Position Bit Name Function Edge selection for INTP05 to interrupt controller. Selects active edge for interrupt generation.
Page 225: Figure 8-19: Interrupt Mode Register 2 (Imtm2)
Chapter 8 Interrupt/Exception Processing Function Interrupt mode register 2 (INTM2) Figure 8-19: Interrupt Mode Register 2 (IMTM2) Address Initial value INTM2 ES111 ES110 ES101 ES100 ES091 ES090 ES081 ES080 FFFFF884H Bit Position Bit Name Function Edge selection for INTP21 to interrupt controller. Selects active edge for interrupt generation.
Page 226: Figure 8-20: Interrupt Mode Register 3 (Imtm3)
Chapter 8 Interrupt/Exception Processing Function Interrupt mode register 3 (INTM3) Figure 8-20: Interrupt Mode Register 3 (IMTM3) Initial Address value INTM3 ESN0 FFFFF886H Bit Position Bit Name Function Edge selection for NMI. Selects active edge for interrupt generation. ESN0 0: Falling edge. 1: Rising edge.
Page 227: Software Exception
Chapter 8 Interrupt/Exception Processing Function 8.5 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 8.5.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: Saves the restored PC to EIPC.
Page 228: Restore
Chapter 8 Interrupt/Exception Processing Function 8.5.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. Transfers control to the address of the restored PC and PSW.
Page 229: Exception Status Flag (Ep)
Chapter 8 Interrupt/Exception Processing Function 8.5.3 Exception status flag (EP) The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Figure 8-23: Exception Status Flag (EP) Initial 8 7 6 5 4 3 2 1 0 value...
Page 230: Exception Trap
Chapter 8 Interrupt/Exception Processing Function 8.6 Exception Trap An exception trap is an interrupt that is requested when an illegal execution of an instruction takes place. In the V850E/CA2, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap.
Page 231: Figure 8-25: Restore Processing From Exception Trap
Chapter 8 Interrupt/Exception Processing Function Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW.
Page 232: Debug Trap
Chapter 8 Interrupt/Exception Processing Function 8.6.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. Operation When the debug trap is generated, the CPU performs the following processing, transfers control to the debug monitor routine, and shifts to debug mode.
Page 233: Figure 8-27: Restore Processing From Debug Trap
Chapter 8 Interrupt/Exception Processing Function Restore Recovery from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW.
Page 234: Multiple Interrupt Processing Control
Chapter 8 Interrupt/Exception Processing Function 8.7 Multiple Interrupt Processing Control Multiple interrupt processing control is a process by which an interrupt request that is currently being processed can be interrupted during processing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is received and processed first.
Page 235 Chapter 8 Interrupt/Exception Processing Function Generation of exception in service program Service program of maskable interrupt or exception • EIPC saved to memory or register • EIPSW saved to memory or register • TRAP instruction ¨ Exception such as TRAP instruction acknowledged. •...
Page 236: Interrupt Response Time
Chapter 8 Interrupt/Exception Processing Function 8.8 Interrupt Response Time The following table describes the V850E/CA2 interrupt response time (from interrupt generation to start of interrupt processing). Except in the following cases, the interrupt response time is a minimum of 5 clocks. To input interrupt requests continuously, leave a space of at least 5 clocks between interrupt request inputs.
Page 237: Periods In Which Interrupts Are Not Acknowledged
Chapter 8 Interrupt/Exception Processing Function Table 8-3: Interrupt Response Time Interrupt Response Time (Internal System Clocks) Condition Internal Interrupt External interrupt Minimum 5 + analog delay time The following cases are exceptions: • In IDLE/software STOP mode • External bit access Maximum 11 + analog delay time •...
Page 238 [MEMO] Preliminary User’s Manual U15839EE1V0UM00...
Page 239: Chapter 9 Clock Generator
Chapter 9 Clock Generator 9.1 Features • Multiplication function by PLL synthesizer - Spread Spectrum PLL for CPU/BCU clock supply • Clock sources - Oscillation through oscillator connection - Oscillation through sub-oscillator connection during sub-watch-mode • Power save modes - WATCH mode - Sub-WATCH mode - HALT mode - IDLE mode...
Page 240: Configuration
Chapter 9 Clock Generator 9.2 Configuration Figure 9-1: Block Diagram of the Clock Generator STOP WATCH/S-WATCH SSCG 64 (f = 4 MHz) WATCH/S-WATCH 50 (f = 5 MHz) IDLE HALT CPU/BCU STOP STOP WATCH/S-WATCH WATCH/S-WATCH Main System PLL Circuit Clock OSC WATCH IDLE Peripherals...
Page 241: Control Registers
Chapter 9 Clock Generator 9.3 Control Registers 9.3.1 Clock Control Register (CKC) This is an 8-bit register that controls the clock management. Data can be written to it only in a sequence of specific instructions so that its contents are not easily rewritten in case of program hang-up. See also PHCMD register.
Page 242 Chapter 9 Clock Generator Figure 9-2: Clock Control Register (CKC) (2/2) Bit name Function Sub-clock source select bit WTSEL1 0: Main oscillator/128 is clock source for sub-clock 1: Sub-oscillator is clock source for sub-clock Sub-clock divider select for f CKSEL2 0: f = sub-clock/4 WTSEL0...
Page 243: Clock Generator Status Register (Cgstat)
Chapter 9 Clock Generator 9.3.2 Clock Generator Status Register (CGSTAT) This is an 8-bit register that monitors the status of the SSCG and main oscillator hard macro operation. This register can be read in 8- or 1-bit units. Figure 9-3: Clock Generator Status Register (CGSTAT) Initial Address value...
Page 244: Watchdog Timer Clock Control Register (Wcc)
Chapter 9 Clock Generator 9.3.3 Watchdog Timer Clock Control Register (WCC) This is an 8-bit register that controls the watchdog timer clock. Data can be written to it only in a sequence of specific instructions so that its contents are not easily rewritten in case of program hang-up.
Page 245: Processor Clock Control Register (Pcc)
Chapter 9 Clock Generator 9.3.4 Processor Clock Control Register (PCC) This is an 8-bit register that controls the CPU clock. Data can be written to it only in a sequence of spe- cific instructions so that its contents are not easily rewritten in case of program hang-up. See also PHCMD register.
Page 246 Chapter 9 Clock Generator Figure 9-5: Processor Clock Control Register (PCC) (2/2) Bit name Function Specifies the CPU clock source CKS1 CKS0 CPU Clock Main oscillator SSCG CLS, CKS1, CKS0 PLL (Main oscillator frequency × 4) PLL (Main oscillator frequency × 8) Sub-Oscillator Note: X: don’t care Caution:...
Page 247: Reset Source Monitor Register (Rsm)
Chapter 9 Clock Generator 9.3.5 Reset Source Monitor Register (RSM) This is a 8-bit register that indicates the source of the last system reset. This register can only be read in 8- or 1-bit units. Figure 9-6: Reset Source Monitor Register (RSM) Initial Address value...
Page 248: Sscg Frequency Modulation Control Register (Scfmc)
Chapter 9 Clock Generator 9.3.6 SSCG Frequency Modulation Control Register (SCFMC) This is a 5-bit register that controls the frequency modulation of SSCG in dithering mode and the post scale factor of the SSCG. This register can be read or written in 8- or 1-bit units. Figure 9-7: SSCG Frequency Modulation Control Register (SCFMC) Initial Address...
Page 249: Sscg Frequency Control Register 0 (Scfc0)
Chapter 9 Clock Generator 9.3.7 SSCG Frequency Control Register 0 (SCFC0) This is an 8-bit register that controls the first frequency divider of the SSCG. It determines the lower SSCG output frequency in dithering mode. This register can be read or written in 8- or 1-bit units. Figure 9-8: SSCG Frequency Control Register 0 (SCFC0) Initial Address...
Page 250: Sscg Frequency Control Register 1 (Scfc1)
Chapter 9 Clock Generator 9.3.8 SSCG Frequency Control Register 1 (SCFC1) This is an 8-bit register that controls the second frequency divider of the SSCG. It determines the SSCG output frequency in fixed frequency mode and the upper SSCG output frequency in dithering mode.
Page 251: Power Saving Functions
Chapter 9 Clock Generator 9.4 Power Saving Functions 9.4.1 General The device provides the following power saving functions. These modes can be combined and switched to suit the target application, which enables effective implementation of low-power systems. The device provides the following power saving functions. These modes can be combined and switched to suit the target application, which enables effective implementation of low-power systems.
Page 252: Figure 9-10: Power Save Mode State Transition Diagram
Chapter 9 Clock Generator Figure 9-10 shows the operation of the clock generator in normal operation mode, HALT mode, IDLE mode, WATCH mode, SUB WATCH mode and software STOP mode. An effective low power consumption system can be realized by combining these modes and switching modes according to the required use.
Page 253: Power Save Modes Outline
Chapter 9 Clock Generator 9.4.2 Power Save Modes Outline V850E/CA2 Jupiter is provided with the following standby modes: HALT, IDLE, WATCH, and software STOP. Application systems, which are designed so that these modes are switched appropriately according to operation purposes, reduce power consumption efficiently.
Page 254: Power Saving Mode Functions
Chapter 9 Clock Generator 9.4.3 Power Saving Mode Functions The Clock Controller supports 3 type of standby modes: IDLE, WATCH, STOP. The behaviour of all out- put clocks is described in the following tables. Table 9-2: Power Saving Mode Functions Condition release release...
Page 255: Table 9-3: Power Saving Mode Functions
Chapter 9 Clock Generator Table 9-3: Power Saving Mode Functions Pin Function RESET STOP WATCH IDLE HALT WATCH Hi-Z/--- Hi-Z/--- Hi-Z/--- Hi-Z/--- D[15:0] Hi-Z operate Note 1 Note 1 Note 1 Note 1 A[23-0] Hi-Z HOLD HOLD HOLD HOLD operate CS[4:3, 0] Hi-Z operate...
Page 256: Halt Mode
Chapter 9 Clock Generator 9.4.4 HALT mode In this mode, the CPU clock is stopped, though the clock generators (oscillator, SSCG and PLL synthe- sizer) continue to operate for supplying clock signals to other peripheral function circuits. Setting the HALT mode when the CPU is idle reduces the total system power consumption. In the HALT mode, program execution is stopped but the contents of all registers and internal RAM prior are retained as is.
Page 257: Table 9-5: Operation After Halt Mode Release By Interrupt Request
Chapter 9 Clock Generator Table 9-5: Operation after HALT mode release by interrupt request Release cause EI state DI state NMI request Branches to handler address. Maskable interrupt Branches to handler address, or Executes the next instruction. request executes the next instruction. Remark: If HALT mode is entered during execution of a particular interrupt handler and an unmasked interrupt request with a higher priority than the previous one is subsequently generated, the...
Page 258: Idle Mode
Chapter 9 Clock Generator 9.4.5 IDLE Mode In this mode, the CPU clock is stopped resulting in stop of the entire system, though the clock genera- tors (oscillator, SSCG and PLL synthesizer) continue to operate. As it is not necessary to secure the oscillator oscillation stabilization time and the PLL lock-up time, it is possible to quickly switch to the normal operating mode in response to a release cause.
Page 259: Watch Mode
Chapter 9 Clock Generator 9.4.6 WATCH mode In this mode f clock is stopped while the oscillator continue to operate to achieve low power, though only oscillator & Watch timer / Watchdog timer continue to operate. This mode compensates the HALT modes concerning the oscillator stabilization time and power con- sumption.
Page 260: Table 9-8: Operation After Watch Mode Release By Interrupt Request
Chapter 9 Clock Generator Table 9-8: Operation after WATCH mode release by interrupt request Release cause EI state DI state NMI request Branches to handler address. Maskable interrupt Branches to handler address, or Executes the next instruction. request executes the next instruction. Remark: If WATCH mode is entered during execution of a particular interrupt handler and an unmasked interrupt request with a higher priority than the previous one is subsequently...
Page 261: Sub Watch Mode
Chapter 9 Clock Generator 9.4.7 SUB WATCH mode In this mode f clock and the main oscillator are stopped while the sub oscillator continue to operate to achieve low power, though only oscillator & Watch timer / Watchdog timer continue to operate. This mode compensates the HALT modes concerning the oscillator stabilization time and power con- sumption.
Page 262: Table 9-10: Operation After Sub Watch Mode Release By Interrupt Request
Chapter 9 Clock Generator Release by interrupt request: The SUB WATCH mode is released unconditionally by an unmasked maskable interrupt request regardless of its priority level. After the main oscillator stabilization time has passed, CPU starts operation. However, if the SUB WATCH mode is entered during execution of an interrupt handler, the operation differs on interrupt priority levels as follows: (a) If an interrupt request less priorities than the currently serviced interrupt request is generated, the SUB WATCH mode is release but the interrupt is not acknowledged.
Page 263: Figure 9-11: Sub Watch Mode Released By Reset Input
Chapter 9 Clock Generator When released by RESET input This operation is the same as normal reset operation. The Oscillator stabilization time must be ensured by reset input. Figure 9-11: Sub Watch mode released by RESET input Sub-Watch mode setting Main Oscillation circuit System clock Main OSC STOP state...
Page 264: Figure 9-12: Sub Watch Mode Release By Watchdog Reset, Nmi, Int
Chapter 9 Clock Generator When released by Watchdog Timer RESET input CPU operation starts after main oscillation stabilization time has been secured. Figure 9-12: Sub Watch mode release by Watchdog reset, NMI, INT Sub-Watch mode setting Main Oscillation circuit System clock Main OSC STOP state NMI or INT input Stabilization counter...
Page 265: Software Stop Mode
Chapter 9 Clock Generator 9.4.8 Software STOP mode In this mode, the CPU clock is stopped including the clock generators (oscillator, SSCG and PLL syn- thesizer), resulting in stop of the entire system for ultra-low power consumption (the only consumed is device leakage current).
Page 266: Figure 9-13: Stop Mode Released By Reset Input
Chapter 9 Clock Generator When released by RESET input This operation is the same as normal reset operation. Oscillator stabilization time must be ensured by reset input. Figure 9-13: STOP mode released by RESET input STOP mode setting Main Oscillation circuit System clock STOP state RESET signal...
Page 267: Figure 9-14: Stop Mode Release By Watchdog Reset, Nmi, Int
Chapter 9 Clock Generator When released by Watchdog Timer RESET input CPU operation starts after main oscillation stabilization time has been secured Figure 9-14: STOP mode release by Watchdog reset, NMI, INT STOP mode setting Main Oscillation circuit System clock STOP state NMI or INT input Oscillation stabilization counter...
Page 268: Register Description
Chapter 9 Clock Generator 9.5 Register Description 9.5.1 Power Save Control Register (PSC) This is an 8-bit register that controls the power save mode. Data can be written only in a sequence of specific instructions so that its contents are not easily rewritten in case of program hang-up. This register can be read or written in 8-bit or 1-bit units.
Page 269 Chapter 9 Clock Generator Sample coding <1> ST.B r11, PSM [r0] ; Set PSM register <2> MOV 0x04, r10 <3> ST.B r10, PRCMD [r0] ; Write PRCMD register <4> ST.B r10, PSC [r0] ; Set PSC register <5> NOP ; Dummy instruction <6>...
Page 270: Power Save Mode Register (Psm)
Chapter 9 Clock Generator 9.5.2 Power Save Mode Register (PSM) This is an 8-bit register that control the power save mode and sub-oscillator control. This register can be read or written in 8-bit or 1-bit units. Figure 9-16: Power Save Mode Register (PSM) Initial Address value...
Page 271: Chapter 10 Timer
Chapter 10 Timer 10.1 Timer C 10.1.1 Features (Timer C) One channel of Timer C is implemented. Timer C (TMC0) is a 16-bit timer/counter that can perform the following operations. • 2 capture/compare register • Programmable pulse generator function • Interval timer function •...
Page 272: Function Overview (Timer C)
Chapter 10 Timer 10.1.2 Function overview (Timer C) • 16-bit timer/counter (TMC0): 1 channel • Capture/compare registers: 2 • Count clock division selectable by prescaler (maximum frequency of count clock: 8 MHz) • Prescaler divide ratio from f /2 to f /256 PCLK PCLK...
Page 273: Figure 10-1: Block Diagram Of Timer C
Chapter 10 Timer Figure 10-1: Block Diagram of Timer C PCLK 1/16 Clear & start 1/32 1/64 1/128 COUNT 1/256 TMC1 (16-bit) INTTMC0 Sub Clock Calibration PSM.CMODE Edge TIC00 Detection INTWT CCC00 TOC0 CCC01 Edge TIC01 Detection INTCCC0 INTCCC1 Remark: : internal peripheral clock PCLK Preliminary User’s Manual U15839EE1V0UM00...
Page 274: Basic Configuration
Chapter 10 Timer 10.1.3 Basic configuration Table 10-1: Timer C Configuration List Read/ Generated Capture Timer Output Timer Count Clock Register Write Interrupt Signal Trigger TMC0 Read INTTMC0 /2, f PCLK PCLK Read/ /8,f CCC00 INTCCC00 INTCCC00 TOC0 (S) PCLK PCLK Timer C write...
Page 275 Chapter 10 Timer Selection of the internal count clock TMC0 operates as a free-running timer. TMC0 is counted up for each input clock cycle specified by the CS2 to CS0 bits of the TMCC00 register. A division by the prescaler can be selected for the count clock from among /2, f /4, f /8, f...
Page 276: Figure 10-3: Capture/Compare Register 0 (Ccc00)
Chapter 10 Timer Capture/compare registers (CCC00 and CCC01) These capture/compare registers are 16-bit registers. They can be used as capture registers or compare registers according to the CMS1 bit and CMS0 bit specifications of Timer C control register 1 (TMCC01). These registers can be read/written in 16-bit units (However, write operations can only be performed in compare mode).
Page 277 Chapter 10 Timer (a) Setting CCC0n registers to capture registers (set CMS1, CMS0 bits of TMCC01 to 0) When these registers are set to capture registers, the valid edges of the corresponding external interrupt signals TICn0 (n = 0, 1) are detected as capture triggers. The counter register TMC0 is synchronized with the capture trigger, and the value of TMC0 is latched in the CCC00 and CCC01 registers (capture operation).
Page 278: Control Registers
Chapter 10 Timer 10.1.4 Control registers Timer C control register 0 (TMCC00) The TMCC00 register controls the operation of TMC0. This register can be read/written in 8-bit or 1-bit units. Caution: The CAE bit and CE bit cannot be set at the same time. Be sure to set the CAE bit prior to setting the CE bit.
Page 279 Chapter 10 Timer Figure 10-5: Timer C control Register 0 (TMCC00) (2/2) Bit Position Bit Name Function Selects the internal count clock for TMC0. Count Clock PCLK PCLK PCLK PCLK PCLK 6 to 4 CS2 to CS0 PCLK /128 PCLK /256 PCLK Caution: Do not change the CS2 to CS0 bits during timer operation.
Page 280: Figure 10-6: Timer C Control Register 1 (Tmcc01) (1/2)
Chapter 10 Timer Timer C control register 1 (TMCC01) The TMCC01 register controls the operation of TMC0. This register can be read/written in 8-bit or 1-bit units. Cautions: 1. Do not change the bits of the TMCC01 register during timer operation. If they are to be changed, they must be changed after setting the CE bit of the TMCC00 register to 0.
Page 281 Chapter 10 Timer Figure 10-6: Timer C control Register 1 (TMCC01) (2/2) Bit Position Bit name Function Enables/disables TMC0 clearing during compare operation. 0: Disable clearing. 1: Enable clearing (TMC0 is cleared when CCC00 and TMC0 match during com- pare operation). Selects operation mode of capture/compare register (CCC01).
Page 282: Figure 10-7: Valid Edge Selection Register (Sesc0)
Chapter 10 Timer Valid edge selection register (SESC0) This register specifies the valid edge of external interrupt requests from an external TICmn pin (n, m = 0 to 1). The rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin.
Page 283: Operation
Chapter 10 Timer 10.1.5 Operation Count operation Timer C can function as a 16-bit free-running timer. When it operates as a free-running timer and the CCC00 register or CCC01 register and the TMC0 count value match, an interrupt signal is generated and the timer output signal (TOC0) can be set or reset.
Page 284: Figure 10-9: Timing Of Interrupt Operation After Overflow
Chapter 10 Timer Overflow When the TMC0 register has counted the count clock from FFFFH to 0000H, the OVF bit of the TMCC00 register is set to "1", and an overflow interrupt (INTTMC0) is generated at the same time. However, if the CCC00 register is set to compare mode (CMS0 = 1) and to the value FFFFH, when match clearing is enabled (CCLR = 1) the TMC0 counter register is considered to be cleared and the OVF bit is not set to "1"...
Page 285: Figure 10-10: Timing Of Capture For Pulse Cycle Measurement (Rising Edge)
Chapter 10 Timer Capture operation The TMC0 register has two capture/compare registers. These are the CCC00 register and the CCC01 register. A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMS0 bits of the TMCC01 register. If the CMS1 and CMS0 bits of the TMCC01 register are set to "0", the register operates as a capture register.
Page 286: Figure 10-11: Timing Of Capture For Pulse Width Measurement (Both Edges)
Chapter 10 Timer (b) Example: capture for pulse cycle measurement If both the rising and falling edges are set as capture triggers, the input pulse width from an external source can be measured. Figure 10-11: Timing of capture for pulse width measurement (both edges) (TMC0 count values) TMC0 Count start...
Page 287 Chapter 10 Timer (c) Example: Cycle measurement By setting the TMCC00 and TMCC01 registers as described below Timer C can measure the cycle of signals input to the TICn0 pin. The valid edge of the TIC00 pin is selected according to the IES01 and IES00 bits of the SESC0 register.
Page 288: Figure 10-12: Timing Of Cycle Measurement Operation
Chapter 10 Timer Calculation: The cycle of signals input to the INTCCC00 pin is calculated by obtaining the difference between the TMC0 register’s count value (Dx) that was captured in the CCC00 register according to the x-th valid edge input of the TIC00 pin and the TMC0 register’s count value (D(x+1)) that was captured in the CCC00 register according to the (x+1)-th valid edge input of the TIC00 pin and multiplying the value of this difference by the cycle of the clock control signal.
Page 289: Figure 10-13: Timing Of Compare Operation
Chapter 10 Timer Compare operation The TMC0 register has two capture/compare registers. These are the CCC00 register and the CCC01 register. A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMS0 bits of the TMCC01 register. If "1" is set in the CMS1 and CMS0 bits of the TMCC01 register, the register operates as a compare register.
Page 290: Figure 10-14: Timing Of Interval Timer Operation
Chapter 10 Timer (a) When CCC00 register is set to 0000H If the CCC00 register is set to 0000H, the 0000H after the TMC0 register counts up from FFFFH to 0000H is judged as a match. The 0000H when the TMC0 register begins counting is not judged as a match.
Page 291: Figure 10-15: Timing Of Pwm Output Operation (Overview)
Chapter 10 Timer PWM output Timer C has one timer output pin (TOC0). An external pulse output (TOC0) can be generated when a match of the two compare registers (CCC00 and CCC01) and the TMC0 register is detected. If a match is detected when the TMC0 count value and the CCC00 value are compared, the output level of the TOC0 pin is set.
Page 292: Figure 10-16: Timing Of Pwm Output Operation (Detail)
Chapter 10 Timer (a) Example PWM output By setting the TMCC00 and TMCC01 registers as described below Timer C can output a PWM of an arbitrary frequency with the values that were set in advance in the CCC00 and CCC01 registers determining the intervals.
Page 293: Sub Oscillator Calibration Function
Chapter 10 Timer 10.1.6 Sub Oscillator Calibration Function For automotive dashboard application, customer need to achieve a watch timer accuracy of about 1 sec/week. This target is difficult to manage using a 32 KHz crystal for sub oscillator because of the temperature dependency of these crystal types.
Page 294: Figure 10-17: Multiplexed Inputs For Timer C Sub Oscillator Calibration Function
Chapter 10 Timer Figure 10-17: Multiplexed Inputs for Timer C Sub Oscillator Calibration Function PCLK Prescale COUNT Main Sub Clock PSM.CMODE Calibration Watch INTWT Timer CCC01 Edge TIC01 Detection To use the sub oscillator calibration feature, the watch timer clock must be derived from the sub oscillator.
Page 295: Precautions Timer C
Chapter 10 Timer 10.1.7 Precautions Timer C Various precautions concerning Timer C are shown below. The following bits and registers must not be rewritten during operation (TMCC00 register CE = 1). • CS2 to CS0 bits of TMCC00 register • TMCC01 register •...
Page 296: Timer D
Chapter 10 Timer 10.2 Timer D 2 x 16-bit interval timer of Timer D are implemented: • Timer D1 • Timer D2 10.2.1 Features Timer D Timer Dn (TMD) functions as a 16-bit interval timer. 10.2.2 Function overview Timer Dn •...
Page 297: Basic Configuration
Chapter 10 Timer 10.2.3 Basic configuration Table 10-3: Timer Dn Configuration List (n = 0, 1) Generated Capture Timer Other Timer Count Clock Register R/W Interrupt Trigger Output S/R Functions Signal /2, f /4, f TMDn – – – – PCLK PCLK PCLK...
Page 298: Figure 10-19: Timer Dn Counter Register (Tmdn) (N = 0, 1)
Chapter 10 Timer Timer D counter Register (TMDn) (n = 0, 1) Timer Dn is a 16-bit timer. It is mainly used as an interval timer for software (n = 0, 1). Starting and stopping TMDn is controlled by the CE bit of the Timer Dn control register (TMCDn). A division by the prescaler can be selected for the count clock from among f /2 and f /256...
Page 299: Figure 10-20: Timer Dn Compare Register (Cmdn) (N = 0, 1)
Chapter 10 Timer Timer Dn compare register (CMDn) (n = 0, 1) CMDn and the TMDn registers’ count value are compared, and an interrupt request signal (INTTMDn) is generated when a match occurs. TMDn is cleared, synchronized with this match. If the CAE bit of the TMCDn register is set to "0", a reset is performed asynchronously, and the registers are initialized (n = 0, 1).
Page 300: Figure 10-21: Timing Of Timer Dn Operation
Chapter 10 Timer Figure 10-21: Timing of Timer Dn Operation (a) When TMDn < CMDn TMDn CMDn INTTMDn (b) When TMDn > CMDn TMDn FFFFH CMDn INTTMDn Remarks: 1. p = TMDn value when overwritten 2. q = CMDn value when overwritten 3.
Page 301: Control Register
Chapter 10 Timer 10.2.4 Control register Timer Dn control register (TMCDn) (n = 0, 1) The TMCDn register controls the operation of Timer Dn (n = 0, 1). This register can be read/written in 8-bit or 1-bit units. Figure 10-22: Timer Dn Control Register (TMCDn) (n = 0, 1) Initial Address value...
Page 302: Operation
Chapter 10 Timer 10.2.5 Operation Compare operation TMDn can be used for a compare operation in which the value that was set in a compare register (CMDn) is compared with the TMDn count value (n = 0, 1). If a match is detected by the compare operation, an interrupt (INTTMDn) is generated. The generation of the interrupt causes TMDn to be cleared to "0"...
Page 303 Chapter 10 Timer Figure 10-23: Timing of Compare Operation (2/2) (b) When CMDn is set to 0 COUNT Count up TMDn clear Clear TMDn FFFFH CMDn Match detected (INTTMDn) Overflow Remark: Interval time = (FFFFH + 2) × Count clock cycle Preliminary User’s Manual U15839EE1V0UM00...
Page 304: Application Example
Chapter 10 Timer 10.2.6 Application example Interval timer This section explains an example in which Timer Dn is used as an interval timer with 16-bit precision. Interrupt requests (INTTMDn) are output at equal intervals (refer to Figure 10-23, “Timing of Com- pare Operation (1/2),”...
Page 305: Precautions For Timer Dn
Chapter 10 Timer 10.2.7 Precautions for Timer Dn Various precautions concerning Timer Dn are shown below. To operate Timer Dn, first set to "1" the CAE bit of the TMCDn register. Up to f /2 clocks are required after a value is set in the CE bit of the TMCDn register until the PCLK set value is transferred to internal units.
Page 306: Timer G
Chapter 10 Timer 10.3 Timer G 2 x 16-bit multi purpose timer of Timer G are implemented: • Timer G0 • Timer G1 10.3.1 Features of Timer G The Timer Gn (n = 0, 1) operate as: • Pulse interval and frequency measurement counter •...
Page 307: Function Overview Of Each Timer Gn
Chapter 10 Timer 10.3.2 Function overview of each Timer Gn • 16-bit timer/counter (TMGn0, TMGn1): 2 channels • Bit length - Timer Gn registers (TMGn0, TMGn1): 16 bits • Capture/compare register (GCCny): 6 - 16-bit - 2 registers are assigned fix to the corresponding one of the 2 counters - 4 free assignable registers to one of the 2 counters •...
Page 308: Figure 10-24: Block Diagram Of Timer Gn
Chapter 10 Timer Figure 10-24: Block Diagram of Timer Gn 16-bit Architecture PCLK PCLK INTTMGn0 PCLK COUNT0 TMGn0 (16-bit) PCLK PCLK Clear PCLK PCLK INTCCGn0 /128 PCLK Noise Elimination GCCn0 (16-bit) TIGn0 Edge Detection capture/compare INTCCGn1 TOGn1 Noise Elimination GCCn1 (16-bit) TIGn1 Control Edge Detection...
Page 309: Basic Configuration
Chapter 10 Timer 10.3.3 Basic configuration The basic configuration is shown below. Table 10-4: Timer Gn Configuration List Generated Capture Timer Output Timer Count Clock Register Interrupt Signal Trigger TMGn0 INTTMGn0 PCLK TMGn1 INTTMGn1 PCLK PCLK GCCn0 INTCCGn0 TIGn0 PCLK GCCn1 INTCCGn1 TIGn1...
Page 310: Figure 10-25: Timer Gn Counter 0 Value Registers Tmgn0
Chapter 10 Timer Timer Gn 16-bit counter registers (TMGn0, TMGn1) The features of the 2 counters TMGn0 and TMGn1 are listed below: • Free-running counter that enables counter clearing by compare match of registers GCCn0/GCCn5 • Counter clear can be set by software. •...
Page 311: Figure 10-27: Timer Gn Counter Tmgn0 Assigned Capture/Compare Register (Gccn0)
Chapter 10 Timer Timer Gn capture/compare registers of the 2 counters (GCCn0, GCCn5) The GCCn0, GCCn5 registers are 16-bit capture/compare registers of Timer Gn. These registers are fixed assigned to the counter registers (TMGn0 and TMGn1). In the capture register mode, GCCn0 (GCCn5) captures the TMGn0 (TMGn1) count value if an edge is detected at Pin TIGn0 (TIGn5).
Page 312: Figure 10-29: Timer Gn Free Assignable Capture/Compare Registers (Gccnm) (M = 1 To 4)
Chapter 10 Timer Timer G capture/compare registers with external PWW-output function (GCCn1 to GCCn4) The GCCn1 to GCCn4 registers are 16-bit capture/compare registers of Timer Gn. They can be assigned to one of the 2 counters either TMGn0 or TMGn1. In the capture register mode, these registers capture the value of TMGn0 when the TBGm bit (m = 1 to 4) of the TMGCMHn register = 0.
Page 313: Control Registers
Chapter 10 Timer 10.3.4 Control registers Timer Gn Mode Register (TMGMn) (n = 0, 1) This register can be read/written in 16-bit, 8-bit or 1-bit units. Figure 10-30: Timer Gn Mode Register (TMGMn) (1/2) Initial Address value TMGM0 POWER OLDE CSE12 CSE11 CSE10 CSE02 CSE01 CSE00 CCSG5 CCSG0 CLRG1 TMG1E CLRG0 TMG0E FFFF F640H 0000H TMGM1 POWER OLDE CSE12 CSE11 CSE10 CSE02 CSE01 CSE00 CCSG5 CCSG0...
Page 314 Chapter 10 Timer Figure 10-30: Timer Gn Mode Register (TMGMn) (2/2) Bit Position Bit Name Function Specifies the mode of the TMGn0 (TMGn1)(CCSG5n for TMGn1, CCSG0n for TMGn0): 0: Free-run mode for TMGn1 (TMGn0), GCCn5 (GCCn0) in capture mode (an detected edge at Pin TIGn5 (TIGn0) stores the value of TMGn1 (TMGn0) in GCCn5 (GCCn0) and an interrupt INTCCGn5 (INTCCGn0) is output) CCSG5n,...
Page 315: Figure 10-31: Timer Gn Mode Register Low (Tmgmnl)
Chapter 10 Timer Timer Gn Mode Register Low (TMGMnL) (n = 0, 1) This register is the low byte of the TMGMn register. This register can be read/written in 8-bit or 1-bit units. Figure 10-31: Timer Gn Mode Register Low (TMGMnL) Initial Address value...
Page 316: Figure 10-33: Timer Gn Channel Mode Register (Tmgcmn)
Chapter 10 Timer Timer Gn Channel Mode Register (TMGCMn) This register specifies the assigned counter (TMGn0 or TMGn1) for the GCCnm register. Furthermore it specifies the edge detection for the TIGy-input-pins (y = 0 to 5). This register can be read/written in 16-bit, 8-bit or 1-bit units. Figure 10-33: Timer Gn Channel Mode Register (TMGCMn) Initial Address...
Page 317: Figure 10-34: Timer Gn Channel Mode Register (Tmgcmnl)
Chapter 10 Timer Timer Gn Channel Mode Register Low (TMGCMnL) This register is the low byte of the TMGCMn register. This register can be read/written in 8-bit or 1-bit units. Figure 10-34: Timer Gn Channel Mode Register (TMGCMnL) Initial Address value TMGCM0L IEG31...
Page 318: Figure 10-36: Timer Gn Output Control Register (Octlgn)
Chapter 10 Timer Timer Gn output control register (OCTLGn) This register controls the timer output from the TOGm pin (m = 1 to 4) and the capture or compare modus for the GCCnm register. This register can be read/written in 16-bit, 8-bit or 1-bit units. Cautions: 1.
Page 319: Figure 10-37: Timer Gn Output Control Register Low (Octlgnl)
Chapter 10 Timer Timer Gn output control register Low (OCTLGnL) This register is the low byte of the OCTLGnH register. This register can be read/written in 8-bit or 1-bit units. Figure 10-37: Timer Gn Output Control Register Low (OCTLGnL) Initial Address value OCTLG0L SWFG2...
Page 320: Figure 10-39: Timer Gn Status Register (Tmgstn)
Chapter 10 Timer (10) Time base status register (TMGSTn) The TMGSTn register indicates the status of TMGn0 and TMGn1. For the CCFGy bit see Chapter 10.3.7 “Operation in Free-run mode” on page 324. This register can be read in 8-bit or 1-bit units. Figure 10-39: Timer Gn Status Register (TMGSTn) Initial Address...
Page 321: Output Delay Operation
Chapter 10 Timer 10.3.5 Output delay operation When the OLDE bit is set, different delays of count clock period are added to the TOGnm pins: delay Output-pin COUNT TOGn1 TOGn2 TOGn3 TOGn4 The figure below shows the timing for the case where the count clock is set to f /2.
Page 322: Explanation Of Basic Operation
Chapter 10 Timer 10.3.6 Explanation of basic operation Overview of the mode settings The Timer Gn includes 2 channels of 16-bit counters (TMGn0/TMGn1), which can operate as independently timebases. TMGn0 (TMGn1) can be set by CCSG0 bit (CCSG5 bit) in the following modes: - free-run mode, - match and clear mode.
Page 323: Table 10-6: Interrupt Output And Timer Output States Dependent On The Register Setting Values
Chapter 10 Timer Table 10-6: Interrupt output and timer output states dependent on the register setting values Register setting value State of each output pin CCSG5n TBGm SWFGm CCSGm INTTMGn1 INTCCGn5 INTCCGnm TOGnm TIm edge detection Tied to inactive CMPGm match level Overflow TI5 edge...
Page 324: Operation In Free-Run Mode
Chapter 10 Timer 10.3.7 Operation in Free-run mode This operation mode is the standard mode for Timer Gn operations. In this mode the 2 counter TMGn0 and TMGn1 are counting up from 0000H to FFFFH, generates an overflow and start again. In the match and clear mode, which is described in Chapter 10.3.8 on page 335 the fixed assigned register GCCn0 (GCCn5) is used to reduce the bit-size of the counter TMGn0 (TMGn1).
Page 325 Chapter 10 Timer (a) Example: Pulse width or period measurement of the TIGny input signal (free run) Capture setting method: When using one of the TOGn1 to TOGn4 pins, select the corresponding counter with the TBGm bit. When TIGn0 is used, the corresponding counter is TMGn0. When TIGn5 is used, the corresponding counter is TMGn1.
Page 326: Figure 10-41: Timing When Both Edges Of Tign0 Are Valid (Free Run)
Chapter 10 Timer Figure 10-41: Timing when both edges of TIGn0 are valid (free run) PCLK COUNTx 0000H 0001H FFFFH 0000H TMGn0 Count start Clear TIGn0 GCCn0 INTCCGn0 INTTMGn0 CCFGn0 No overflow Overflow No overflow Remark: The figure above shows an image. In actual circuitry, 3 to 4 periods of the count-up signal are required from the input of a waveform to TIGn0 until a capture interrupt is output.
Page 327: Figure 10-42: Timing Of Capture Trigger Edge Detection (Free Run)
Chapter 10 Timer (b) Timing of capture trigger edge detection The Tin inputs are fitted with an edge-detection and noise-elimination circuit. Because of this circuit, 3 periods to less than 4 periods of the count clock are required from edge input until an interrupt signal is output and capture operation is performed.
Page 328: Figure 10-43: Timing Of Starting Capture Trigger Edge Detection
Chapter 10 Timer (c) Timing of starting capture trigger edge detection A capture trigger input signal (TIGny) is synchronized in the noise eliminator for internal use. Edge detection starts when 1 count clock period (f ) has been input after timer count COUNT operation starts.
Page 329: Figure 10-44: Timing Of Compare Mode (Free Run)
Chapter 10 Timer Compare operation (free run) Basic settings (m = 1 to 4): Value Remark CCSG0 free run mode CCSG5 SWFGm disable TOGnm Compare mode CCSGm for GCCnm assign counter for GCCnm TBGm 0: TMGn0 1: TMGn1 (a) Example: Interval timer (free run) Setting method interval timer: An usable compare register is one of GCCn1 to GCCn4, and the corresponding counter (TMGn0 or TMGn1) must be selected with the TBGm bit.
Page 330: Figure 10-45: Timing When Gccn1 Is Rewritten During Operation (Free Run)
Chapter 10 Timer (b) When the value 0000H is set in GCCnm INTCCGnm is activated when the value of the counter becomes 0001H. INTTMGn0/INTTMGn1 is activated when the value of the counter changes from FFFFH to 0000H. Note, however, that even if no data is set in GCCnm, INTCCGnm is activated immediately after the counter starts.
Page 331 Chapter 10 Timer PWM output (free run) Basic settings (m = 1 to 4): Value Remark CCSG0 free run mode CCSG5 Note SWFGm enable TOGnm Compare mode Note CCSGm for GCCnm assign counter for GCCnm TBGm 0: TMGn0 1: TMGn1 Note: The PWM mode is activated by setting the SWFGm and the CCSGm bit to "1".
Page 332: Figure 10-46: Timing Of Pwm Operation (Free Run)
Chapter 10 Timer PWM operation: When the value of the counter matches the value of GCCnm, a match interrupt (INTCCGnm) is output. When the counter overflows, an overflow interrupt (INTTMGn0 or INTTMGn1) is generated. TOGnm does not make a transition until the first overflow occurs. (Even if the counter is cleared by software, TOGnm does not make a transition until the next overflow occurs.
Page 333: Figure 10-47: Timing When 0000H Is Set In Gccnm (Free Run)
Chapter 10 Timer (a) When 0000H is set in GCCnm (m = 1 to 4) When 0000H is set in GCCnm, TOGnm is tied to the inactive level. The figure below shows the state of TOGn1 when 0000H is set in GCCn1, and TMGn0 is selected. Figure 10-47: Timing when 0000H is set in GCCnm (free run) ENFG0 FFFFH...
Page 334: Figure 10-49: Timing When Gccnm Is Rewritten During Operation (Free Run)
Chapter 10 Timer (c) When GCCnm is rewritten during operation (m = 1 to 4) When GCCn1 is rewritten from 5555H to AAAAH, the operation shown below is performed. The figure below shows a case where TMGn0 is selected for GCCn1. Figure 10-49: Timing when GCCnm is rewritten during operation (free run) ENFG0 FFFFH...
Page 335: Match And Clear Mode
Chapter 10 Timer 10.3.8 Match and clear mode The match and clear mode is mainly used reduce the number of valid bits of the counters (TMGn0, TMGn1). Therefore the fixed assigned register GCCn0 (GCCn1) is used to compare its value with the counter TMGn0 (TMGn1).
Page 336: Figure 10-50: Timing When Both Edges Of Tigm Are Valid (Match And Clear)
Chapter 10 Timer (b) Example: Capture where both edges of TIGm are valid (match and clear) For the timing chart TMGn0 is selected as the counter corresponding to TOGn1, and 0FFFH is set in GCCn0. Figure 10-50: Timing when both edges of TIGm are valid (match and clear) PCLK COUNTx TMGn0...
Page 337 Chapter 10 Timer Compare operation (match and clear) Basic settings (m = 1 to 4): Value Remark CCSG0n match and clear mode CCSG5n SWFGm disable TOGnm Compare mode CCSGm for GCCnm assign counter for GCCnm TBGm 0: TMGn0 1: TMGn1 (a) Example: Interval timer (match and clear) Setting Method An usable compare register is one of GCCn1 to GCCn4, and the corresponding counter must be...
Page 338: Figure 10-51: Timing Of Compare Operation (Match And Clear)
Chapter 10 Timer Figure 10-51: Timing of compare operation (match and clear) ENFG0 0FFFH 0FFFH 0FFFH Match TMGn0 GCCn1 INTCCGn1 INTCCGn0 In this example, the data N is set in GCCn1, and TMGn0 is selected. 0FFFH is set in GCCn0. Here, N < 0FFFH. (b) When 0000H is set in GCCn0 or GCCn5 (match and clear) When 0000H is set in GCCn0 or GCCn5, the value of the counter is fixed at 0000H, and does not operate.
Page 339: Figure 10-52: Timing When Gccnm Is Rewritten During Operation (Match And Clear)
Chapter 10 Timer (f) When GCCnm (m = 1 to 4) is rewritten during operation (match and clear) When the value of GCCn1 is changed from 0555H to 0AAAH, the operation described below is performed. TMGn0 is selected as the counter, and 0FFFH is set in GCCn0. Figure 10-52: Timing when GCCnm is rewritten during operation (match and clear) PCLK ENFG0...
Page 340 Chapter 10 Timer PMW output (match and clear) Basic settings (m = 1 to 4): Value Remark CCSG0 match and clear mode CCSG5 Note SWFGm enable TOGnm Compare mode Note CCSGm for GCCnm assign counter for GCCnm TBGm 0: TMGn0 1: TMGn1 Note: The PWM mode is activated by setting the SWFGm and the CCSGm bit to "1".
Page 341: Figure 10-53: Timing Of Pwm Operation (Match And Clear)
Chapter 10 Timer Operation of PWM (match and clear): When the value of the counter matches the value of GCCnm, a match interrupt (INTCCGnm) is output. Caution: Do not set 0000H in GCCn0 or GCCn5 in match and clear modus. When the value of GCCn0 (GCCn5) matches the value of the counter, INTCCGn0 (INTCCGn5) is output, and the counter is cleared.
Page 342: Figure 10-54: Timing When 0000H Is Set In Gccnm (Match And Clear)
Chapter 10 Timer (a) When FFFFH is set in GCCn0 or GCCn5 (match and clear) When FFFFH is set in GCCn0 (GCCn5), operation equivalent to the free-run mode is performed. When an overflow occurs, INTTMGn0 (INTTMGn1) is generated, but INTCCGn0 (INTCCGn5) is not generated.
Page 343: Figure 10-55: Timing When The Same Value As Set In Gccn0/Gccn5 Is Set In Gccnm (Match And Clear)
Chapter 10 Timer (c) When the same value as set in GCCn0 or GCCn5 is set in GCCnm (match and clear) When the same value as set in GCCn0 (GCCn5) is set in GCCnm, TOGnm outputs the inactive level for only one clock period immediately after each match and clear event (excluding the first match and clear event).
Page 344: Figure 10-56: Timing When The Value Of Gccnm Exceeding Gccn0 Or Gccn5 (Match And Clear)
Chapter 10 Timer (d) When a value exceeding the value set in GCCn0 or GCCn5 is set in GCCnm (match and clear) When a value exceeding the value set in GCCn0 (GCCn5) is set in GCCnm, TOGnm starts and continues outputting the active level immediately after the first match and clear event (until count operation stops.) The figure shows the state of TOGn1 when 0FFFH is set in GCCn0, 1FFFH is set in GCCn1, and TMGn0 is selected.
Page 345: Figure 10-57: Timing When Gccnm Is Rewritten During Operation (Match And Clear)
Chapter 10 Timer (e) When GCCnm is rewritten during operation (match and clear) When GCCn1 is rewritten from 0555H to 0AAAH, the operation shown below is performed. The figure below shows a case where 0FFFH is set in GCCn0, and TMGn0 is selected for GCCn1. Figure 10-57: Timing when GCCnm is rewritten during operation (match and clear) ENFG0 0FFFH...
Page 346: Edge Noise Elimination
Chapter 10 Timer 10.3.9 Edge noise elimination The edge detection circuit has a noise elimination function. This function regards: • a pulse not wider than 1 count clock period as a noise, and does not detect it as an edge. •...
Page 347: 10Precautions Timer Gn
Chapter 10 Timer 10.3.10 Precautions Timer Gn When POWER bit of TMGMHn register is set The rewriting of the CSEn2 to CSEn0 bits (n = 0, 1) of TMGMHn register is prohibited. These bits set the prescaler for the Timer Gn counter. The rewriting of the CCSGy bits (y = 0 to 5) is prohibited.
Page 348 Chapter 10 Timer Timing The delay of each timer output TOGnm (m = 1 to 4) varies according to the setting of the count clock with the CSEx2 to CSEx0 bits (x = 0, 1). In capture operation 3 to 4 periods of the count-clock (f ) signal are required from the TIGny COUNT pin (y = 0 to 5) until a capture interrupt is output.
Page 349: Chapter 11 Watch Timer
Chapter 11 Watch Timer 11.1 Function The watch timer has the following functions: • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. Figure 11-1 shows the block diagram of the watch timer. Figure 11-1: Block Diagram of Watch Timer Clear 5-bit counter...
Page 350: Configuration
Chapter 11 Watch Timer 11.2 Configuration The watch timer consists of the following hardware: Table 11-1: Configuration of Watch Timer Item Configuration Counter 5 bits × 1 Prescaler 11 bits × 1 Control register Watch timer mode control register (WTM) 11.3 Watch Timer Control Register The watch timer mode control register (WTM) controls the watch timer.
Page 351 Chapter 11 Watch Timer Figure 11-2: Watch Timer Mode Control Register (WTM) (2/2) WTM3 WTM2 Selects Set Time of Watch Flag WTM1 Controls Operation of 5-bit Counter Clears after operation stops Starts WTM0 Enables Operation of Watch Timer Stops operation (clears both prescaler and timer) Enables operation Remark: : Watch timer clock frequency...
Page 352: Operations
Chapter 11 Watch Timer 11.4 Operations 11.4.1 Selection of the Watch Timer Clock With the settings of the clock generator different clocks can be assigned to the Watch Timer. With the WTSELn bits (n = 0, 1) of the CKC register 6 different clocks can be switched as the Watch Timer clock. Table 11-2: Selection of the Watch Timer Clock CKC Register WTM Register...
Page 353: Control Of The Watch Timer
Chapter 11 Watch Timer 11.4.2 Control of the watch timer The watch timer operates with time intervals from 500 µs to 16.4 s. The watch timer generates at its overflow the INTWT interrupt request at fixed time intervals. With the WTM1 bit and the WTM0 bit the watch timer function can be started. With the WTM1 bit the watch timer function can be stopped independently from the interval timer function.
Page 354: Operation As Interval Timer
Chapter 11 Watch Timer 11.4.3 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance. The Interval Timer and the Watch Timer can used at the same time. The interval time of the interval timer is smaller than the interval time of the Watch Timer, every time.
Page 355: Figure 11-3: Operation Timing Of Watch Timer/Interval Timer
Chapter 11 Watch Timer Figure 11-3: Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock f Watch timer interrupt INTWT Note Note Interrupt time of watch timer Interrupt time of watch timer Interval timer interrupt INTWTI Interval time (T) Interval time (T) Note: The Watch Timer frequency depends of the CKC register (Clock Generator) and the WTM...
Page 356 [MEMO] Preliminary User’s Manual U15839EE1V0UM00...
Page 357: Chapter 12 Watchdog Timer Function
Chapter 12 Watchdog Timer Function 12.1 Functions The watchdog timer has the following functions. • Watchdog Timer with non maskable interrupt INTWDT • Watchdog Timer with hardware RESET. Figure 12-1: Block Diagram of Watchdog Timer Clear Prescaler Output INTWDT Control RESET Circuit WDCS2 WDCS1 WDCS0...
Page 358: Configuration
Chapter 12 Watchdog Timer Function 12.2 Configuration The watchdog timer consists of the following hardware. Table 12-1: Watchdog Timer Configuration Item Configuration Watchdog timer clock selection register (WDCS) Watchdog timer mode register (WDTM) Control registers Watch Dog Timer command register (WCMD) Watch Dog Timer command status register (WPHS) Preliminary User’s Manual U15839EE1V0UM00...
Page 359: Watchdog Timer Control Register
Chapter 12 Watchdog Timer Function 12.3 Watchdog Timer Control Register The registers to control the watchdog timer is shown below. • Watchdog timer clock selection register (WDCS) • Watchdog timer mode register (WDTM) Watchdog timer clock selection register (WDCS) This register selects the overflow times of the watchdog timer. WDCS is set by an 8-bit memory manipulation instruction.
Page 360: Figure 12-3: Watchdog Timer Mode Register (Wdtm)
Chapter 12 Watchdog Timer Function Watchdog timer mode register (WDTM) This register sets the operating mode of the watchdog timer, and enables and disables counting. Data can be written to it only in a sequence of specific instructions so that its contents are not eas- ily rewritten in case of program hang-up.
Page 361: Figure 12-4: Watchdog Timer Mode Register (Wcmd)
Chapter 12 Watchdog Timer Function Watchdog timer command register (WCMD) This command register WCMD is used to protect the WDTM register from unintended writing. Writing to WDTM register is possible only immediately after writing to WCMD register. Data written into WCMD register are ignored. Data read from WCMD register are undefined, too. WDTM is set by an 8-bit memory manipulation instruction.
Page 362: Operation
Chapter 12 Watchdog Timer Function 12.4 Operation 12.4.1 Operating as watchdog timer Once the watchdog timer is started (RUN = 1) after reset, the RUN, WDTM4, and WDTM3 bits cannot be changed. These bits can be cleared only by reset input. Watchdog Timer Mode 1 (Interrupt) Set WDTM4 bit of the watchdog timer mode register (WDTM) to “1”...
Page 363: Chapter 13 Serial Interface Function
Chapter 13 Serial Interface Function 13.1 Features The serial interface function provides three types of serial interfaces combining a total of 9 transmit/ receive channels. All channels can be used simultaneously. The three interface formats are as follows. • Asynchronous serial interfaces (UART50, UART51): 2 channels •...
Page 364: Asynchronous Serial Interfaces Uart5N (Uart50, Uart51)
Chapter 13 Serial Interface Function 13.2 Asynchronous Serial Interfaces UART5n (UART50, UART51) 13.2.1 Features • Transfer rate: 300 bps to 625 Kbps (using a dedicated baud rate generator and an internal peripheral clock of 20 MHz) • Full-duplex communications - On-chip reception buffer register (RXBn) - On-chip transmission buffer register (TXBn) •...
Page 365: Configuration
Chapter 13 Serial Interface Function 13.2.2 Configuration UART5n is controlled by the asynchronous serial interface mode register (ASIMn), asynchronous serial interface status register (ASISn), and asynchronous serial interface transmission status register (ASIFn). Receive data is maintained in the reception buffer register (RXBn), and transmit data is written to the transmission buffer register (TXBn).
Page 366 Chapter 13 Serial Interface Function Transmission buffer registers (TXB0, TXB1) TXBn is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to TXBn. The transmission completion interrupt request (INTSTn) is generated synchronized with the completion of transmission of one frame.
Page 367: Control Registers
Chapter 13 Serial Interface Function 13.2.3 Control registers Asynchronous serial interface mode registers (ASIM0, ASIM1) The ASIMn register is an 8-bit register that controls the UART5n transfer operation. This register can be read/written in 8 bit or 1-bit units (n = 0, 1). Figure 13-2: Asynchronous Serial Interface Mode Registers (ASIM0, ASIM1) (1/3) Initial Address...
Page 368 Chapter 13 Serial Interface Function Figure 13-2: Asynchronous Serial Interface Mode Registers (ASIM0, ASIM1) (2/3) Bit Position Bit Name Function Enables/disables reception. 0: Disable reception (Perform synchronous reset of reception circuit) 1: Enable reception Cautions: 1. Set the RXE bit to 1 after setting the Power bit to 1 when starting transfer.
Page 369 Chapter 13 Serial Interface Function Figure 13-2: Asynchronous Serial Interface Mode Registers (ASIM0, ASIM1) (3/3) Bit Position Bit Name Function • 0 parity During transmission, the parity bit is cleared (0) regardless of the transmit data. During reception, no parity error is generated because no parity bit is checked. 4, 3 PS1, PS0 •...
Page 370: Figure 13-3: Asynchronous Serial Interface Status Registers (Asis0, Asis1)
Chapter 13 Serial Interface Function Asynchronous serial interface status registers (ASIS0 to ASIS2) The ASISn register, which consists of 3-bit error flags (PE, FE and OVE), indicates the error status when UART5n reception is completed. The status flag, which indicates a reception error, always indicates the status of the error that occurred most recently.
Page 371: Figure 13-4: Asynchronous Serial Interface Transmit Status Registers (Asif0, Asif1)
Chapter 13 Serial Interface Function Asynchronous serial interface transmission status registers (ASIF0, ASIF1) The ASIFn register, which consists of 2-bit status flags, indicates the status during transmission. By writing the next data to the TXBn register after data is transferred from the TXBn register to the transmission shift register, transmit operations can be performed continuously without suspension even during an interrupt interval.
Page 372: Figure 13-5: Reception Buffer Registers (Rxb0, Rxb1)
Chapter 13 Serial Interface Function Reception buffer registers (RXB0, RXB1) The RXBn register is an 8-bit buffer register for storing parallel data that had been converted by the reception shift register. When reception is enabled (RXE bit = 1 in the ASIMn register), receive data is transferred from the reception shift register to the RXBn register, synchronized with the completion of the shift-in processing of one frame.
Page 373: Figure 13-6: Transmission Buffer Registers (Txb0, Txb1)
Chapter 13 Serial Interface Function Transmission buffer registers (TXB0, TXB1) The TXBn register is an 8-bit buffer register for setting transmit data. When transmission is enabled (TXE bit = 1 in the ASIMn register), the transmit operation is started by writing data to TXBn register. When transmission is disabled (TXE bit = 0 in the ASIMn register), even if data is written to TXBn register, the value is ignored.
Page 374: Interrupt Requests
Chapter 13 Serial Interface Function 13.2.4 Interrupt requests The following three types of interrupt requests are generated from UART50, UART51. • Reception error interrupt (INTSERn) • Reception completion interrupt (INTSRn) • Transmission completion interrupt (INTSTn) The default priorities among these three types of interrupt requests is, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt (n = 0, 1).
Page 375: Operation
Chapter 13 Serial Interface Function 13.2.5 Operation Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 13-7. The character bit length within one data frame, the type of parity, and the stop bit length are specified according to the asynchronous serial interface mode register (ASIMn) (n = 0, 1).
Page 376: Figure 13-8: Asynchronous Serial Interface Transmission Completion Interrupt Timing
Chapter 13 Serial Interface Function Transmit operation When Power bit is set to 1 in the ASIMn register, a high level is output from the TXD5n pin. Then, when TXE bit is set to 1 in the ASIMn register, transmission is enabled, and the transmit operation is started by writing transmit data to transmission buffer register (TXBn) (n = 0, 1).
Page 377: Table 13-2: Transmission Status And Whether Or Not Writing Is Enabled
Chapter 13 Serial Interface Function Continuous transmission operation UART5n can write the next transmit data to the TXBn register at the time that the transmission shift register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during the INTSTn interrupt service after the transmission of one data frame.
Page 378: Figure 13-9: Continuous Transmission Starting Procedure
Chapter 13 Serial Interface Function (a) Starting procedure Figure 13-9 shows the procedure to start continuous transmission. Figure 13-9: Continuous Transmission Starting Procedure TXD5n Start Data (1) Parity Stop Start Data (2) Parity Stop (output) INTST5n (output) TXB5n Data (1) Data (2) Data (3) register...
Page 379: Figure 13-10: Continuous Transmission End Procedure
Chapter 13 Serial Interface Function (b) Ending procedure Figure 13-10: Continuous Transmission End Procedure TXD5n Data Data (n − 1) Parity Start Parity Start Parity Stop Stop Data (n) Stop (n − 2) (output) INTST5n (output) TXB5n Data (n − 1) Data (n) register Transmission...
Page 380: Figure 13-11: Asynchronous Serial Interface Reception Completion Interrupt Timing
Chapter 13 Serial Interface Function Receive operation An awaiting reception state is set by setting Power bit to 1 in the ASIMn register and then setting RXE bit to 1 in the ASIMn register. To start a receive operation, detects a start bit first. The start bit is detected by sampling RXD5n pin.
Page 381: Figure 13-12: When Reception Error Interrupt Is Separated From Intsrn Interrupt (Isrm Bit = 0)
Chapter 13 Serial Interface Function Reception error The three types of error that can occur during a receive operation are a parity error, framing error, or overrun error. The data reception result is that the various flags of the ASISn register are set (1), and a reception error interrupt (INTSERn) or a reception completion interrupt (INTSRn) is generated at the same time.
Page 382 Chapter 13 Serial Interface Function Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at the transmission and reception sides. (a) Even parity - During transmission The parity bit is controlled so that the number of bits with the value “1”...
Page 383: Figure 13-14: Noise Filter Circuit
Chapter 13 Serial Interface Function Receive data noise filter The RXD5n signal is sampled at the rising edge of the prescaler output basic clock (Clock). If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data.
Page 384: Dedicated Baud Rate Generators (Brg) Of Uart5N (N = 0, 1)
Chapter 13 Serial Interface Function 13.2.6 Dedicated baud rate generators (BRG) of UART5n (n = 0, 1) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception at UART5n (n = 0, 1). The dedicated baud rate generator output can be selected as the serial clock for each channel.
Page 385: Figure 13-17: Clock Select Registers (Chksr0, Chksr1)
Chapter 13 Serial Interface Function Serial clock generation A serial clock can be generated according to the settings of the CKSRm and BRGCm registers. The basic clock to the 8-bit counter is selected according to the TPS3 to TPS0 bits of the CKSRm register.
Page 386: Figure 13-18: Baud Rate Generator Control Registers (Brgc0, Brgc1)
Chapter 13 Serial Interface Function (b) Baud rate generator control registers (BRGC0, BRGC1) The BRGCm register is an 8-bit register that controls the baud rate (serial transfer speed) of UART5n. This register can be read or written in 8-bit or 1-bit units (m = 0, 1). Figure 13-18: Baud Rate Generator Control Registers (BRGC0, BRGC1) Initial Address...
Page 387 Chapter 13 Serial Interface Function (c) Baud rate The baud rate is the value obtained according to the following formula. ---------- Baud rate 2 k ⋅ = Frequency [Hz] of basic clock selected according to TPS3 to TPS0 bits of CKSRm register.
Page 388: Table 13-4: Baud Rate Generator Setting Data
Chapter 13 Serial Interface Function (e) Baud rate setting example Table 13-4: Baud Rate Generator Setting Data = 20 MHz = 16 MHz = 5 MHz = 4 MHz PCLK PCLK PCLK PCLK Baud Rate [bps] /256 /256 0.16 0.16 0.16 0.16 PCLK...
Page 389: Figure 13-19: Allowable Baud Rate Range During Reception
Chapter 13 Serial Interface Function Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution: The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 390: Table 13-5: Maximum And Minimum Allowable Baud Rate Error
Chapter 13 Serial Interface Function When the latch timing margin is made 2 basic clocks (Clock), the minimum allowable transfer rate (FLmin) is as follows. – × × × ----------- - ------------------- FLmin 11 FL – Therefore, the transfer destination’s maximum baud rate (BRmax) that can be received is as follows.
Page 391: Precautions
Chapter 13 Serial Interface Function Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of basic clock (Clock) longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit.
Page 392: Clocked Serial Interfaces (Csi00 To Csi02)
Chapter 13 Serial Interface Function 13.3 Clocked Serial Interfaces (CSI00 to CSI02) 13.3.1 Features • High-speed transfer: Maximum 5 Mbps • Master mode or slave mode can be selected • Transmission data length: 8 bits or 16 bits • Transfer data direction can be switched between MSB first and LSB first •...
Page 393: Configuration
Chapter 13 Serial Interface Function 13.3.2 Configuration CSI0n is controlled via the clocked serial interface mode register (CSIMn) (n = 0 to 2). Transmission/reception of data is performed with reading SIOn register (n = 0 to 2). Clocked serial interface mode registers (CSIM0 to CSIM2) The CSIMn register is an 8-bit register that specifies the operation of CSI0n.
Page 394: Figure 13-21: Block Diagram Of Clocked Serial Interfaces
Chapter 13 Serial Interface Function (12) Clocked serial interface initial transmission buffer registers Low (SOTBFL0 to SOTBFL2) The SOTBFLn register is an 8-bit buffer register that stores initial transmit data in the repeat transfer mode. (13) Selector The selector selects the serial clock to be used. (14) Serial clock control circuit Controls the serial clock supply to the shift register.
Page 395: Control Registers
Chapter 13 Serial Interface Function 13.3.3 Control registers Clocked serial interface mode registers (CSIM0 to CSIM2) The CSIMn register controls the CSI0n operation (n = 0 to 2). These registers can be read/written in 8-bit or 1-bit units (however, bit 0 is read-only). Figure 13-22: Clocked Serial Interface Mode Registers (CSIM0 to CSIM2) Initial Address...
Page 396: Figure 13-23: Clocked Serial Interface Clock Selection Registers (Csic0 To Csic2) (1/2)
Chapter 13 Serial Interface Function Clocked serial interface clock selection registers (CSIC0 to CSIC2) The CSICn register is an 8-bit register that controls the CSI0n transfer operation (n = 0 to 2). This register can be read/written in 8-bit or 1-bit units. Figure 13-23: Clocked Serial Interface Clock Selection Registers (CSIC0 to CSIC2) (1/2) Initial Address...
Page 397 Chapter 13 Serial Interface Function Figure 13-23: Clocked Serial Interface Clock Selection Registers (CSIC0 to CSIC2) (2/2) Bit Position Bit Name Function Specifies input clock CKS2 CKS1 CKS0 Input Clock Mode Master mode PCLK Internal BRG Channel 0 Master mode Internal BRG Channel 1 Master mode Master mode...
Page 398: Figure 13-24: Clocked Serial Interface Reception Buffer Registers (Sirb0 To Sirb2)
Chapter 13 Serial Interface Function Clocked serial interface reception buffer registers (SIRB0 to SIRB2) The SIRBn register is a 16-bit buffer register that stores receive data (n = 0 to 2). When the receive-only mode is set (TRMD bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBn register.
Page 399: Figure 13-25: Clocked Serial Interface Reception Buffer Registers Low (Sirbl0 To Sirbl2)
Chapter 13 Serial Interface Function Clocked serial interface reception buffer registers Low (SIRBL0 to SIRBL2) The SIRBLn register is an 8-bit buffer register that stores receive data (n = 0 to 2). When the receive-only mode is set (TRMD bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBLn register.
Page 400: Figure 13-26: Clocked Serial Interface Read-Only Reception Buffer Registers (Sirbe0 To Sirbe2)
Chapter 13 Serial Interface Function Clocked serial interface read-only reception buffer registers (SIRBE0 to SIRBE2) The SIRBEn register is a 16-bit buffer register that stores receive data (n = 0 to 2). These registers are read-only, in 16-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSIE bit of the CSIMn register.
Page 401: Figure 13-27: Clocked Serial Interface Read-Only Reception Buffer Registers Low (Sirbel0 To Sirbel1)
Chapter 13 Serial Interface Function Clocked serial interface read-only reception buffer registers Low (SIRBEL0 to SIRBEL2) The SIRBELn register is an 8-bit buffer register that stores receive data (n = 0 to 2). These registers are read-only, in 8-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSIE bit of the CSIMn register.
Page 402: Figure 13-28: Clocked Serial Interface Transmission Buffer Registers (Sotb0 To Sotb2)
Chapter 13 Serial Interface Function Clocked serial interface transmission buffer registers (SOTB0 to SOTB2) The SOTBn register is a 16-bit buffer register that stores transmit data (n = 0 to 2). When the transmission/reception mode is set (TRMD bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBn register.
Page 403: Figure 13-29: Clocked Serial Interface Transmission Buffer Registers Low (Sotbl0 To Sotbl2)
Chapter 13 Serial Interface Function Clocked serial interface transmission buffer registers Low (SOTBL0 to SOTBL2) The SOTBLn register is an 8-bit buffer register that stores transmit data (n = 0 to 2). When the transmission/reception mode is set (TRMD bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBLn register.
Page 404: Figure 13-30: Clocked Serial Interface Initial Transmission Buffer Registers (Sotbf0 To Sotbf2)
Chapter 13 Serial Interface Function Clocked serial interface initial transmission buffer registers (SOTBF0 to SOTBF2) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0 to 2). The transmission operation is not started even if data is written to the SOTBFn register. These registers can be read/written in 16-bit units.
Page 405: Figure 13-31: Clocked Serial Interface Initial Transmission Buffer Registers Low (Sotbfl0 To Sotbfl2)
Chapter 13 Serial Interface Function (10) Clocked serial interface initial transmission buffer registers Low (SOTBFL0 to SOTBFL2) The SOTBFLn register is an 8-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0 to 2). The transmission operation is not started even if data is written to the SOTBFLn register.
Page 406: Figure 13-32: Serial I/O Shift Registers (Sio0 To Sio2)
Chapter 13 Serial Interface Function (11) Serial I/O shift registers (SIO0 to SIO2) The SIOn register is a 16-bit shift register that converts parallel data into serial data (n = 0 to 2). The transfer operation is not started even if the SIOn register is read. These registers are read-only, in 16-bit units.
Page 407: Figure 13-33: Serial I/O Shift Registers Low (Siol0 To Siol2)
Chapter 13 Serial Interface Function (12) Serial I/O shift registers Low (SIOL0 to SIOL2) The SIOLn register is an 8-bit shift register that converts parallel data into serial data (n = 0 to 2). The transfer operation is not started even if the SIOLn register is read. These registers are read-only, in 8-bit units.
Page 408: Operation
Chapter 13 Serial Interface Function 13.3.4 Operation Single transfer mode (a) Usage Note 1 In the receive-only mode (TRMD bit of CSIMn register = 0), transfer is started by reading receive data buffer register (SIRBn/SIRBLn) (n = 0 to 2). In the transmission/reception mode (TRMD bit of CSIMn register = 1), transfer is started by Note 2 writing...
Page 409: Figure 13-34: Timing Chart In Single Transfer Mode (1/2)
Chapter 13 Serial Interface Function Figure 13-34: Timing Chart in single Transfer Mode (1/2) (a) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKP bit = 0, DAP bit = 0 SCK0n (input/output) SO0n...
Page 410 Chapter 13 Serial Interface Function Figure 13-34: Timing Chart in single Transfer Mode (2/2) (b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKP bit = 0, DAP bit = 1 SCK0n (input/output) SO0n...
Page 411: Figure 13-35: Timing Chart According To Clock Phase Selection (1/2)
Chapter 13 Serial Interface Function (b) Clock phase selection The following shows the timing when changing the conditions for clock phase selection (CKP bit of CSICn register) and data phase selection (DAP bit of CSICn register) under the following conditions. •...
Page 412 Chapter 13 Serial Interface Function Figure 13-35: Timing Chart According to Clock Phase Selection (2/2) (c) When CKP bit = 0, DAP bit = 1 SCK0n (input/output) SI0n (input) DO6 DO5 DO4 DO3 DO2 DO1 SO0n (output) Reg_R/W INTCSIn interrupt CSOT bit (d) When CKP bit = 1, DAP bit = 1 SCK0n (input/output)
Page 413: Figure 13-36: Timing Chart Of Interrupt Request Signal Output In Delay Mode (1/2)
Chapter 13 Serial Interface Function (c) Transmission/reception completion interrupt request signals (INTCSI0 to INTCSI2) INTCSI0n is set (1) upon completion of data transmission/reception. Caution: The delay mode (CSIT bit = 1) is valid only in the master mode (bits CKS2 to CKS0 of the CSICn register are not 111B).
Page 414 Chapter 13 Serial Interface Function Figure 13-36: Timing Chart of Interrupt Request Signal Output in Delay Mode (2/2) (b) When CKP bit = 1, DAP bit = 1 Input clock SCK0n (input/output) SI0n (input) SO0n (output) Reg_R/W INTCSIn interrupt CSOT bit Delay Remarks: 1.
Page 415: Figure 13-37: Repeat Transfer (Receive-Only) Timing Chart
Chapter 13 Serial Interface Function Repeat transfer mode (a) Usage (receive-only) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the receive-only mode (TRMD bit of CSIMn register = 0). <2> Read SIRBn register (start transfer with dummy read). <3>...
Page 416 Chapter 13 Serial Interface Function (b) Usage (transmission/reception) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the transmission/reception mode (TRMD bit of CSIMn register = 1). <2> Write the first data to the SOTBFn register. <3>...
Page 417: Figure 13-38: Repeat Transfer (Transmission/Reception) Timing Chart
Chapter 13 Serial Interface Function Figure 13-38: Repeat Transfer (Transmission/Reception) Timing Chart SCK0n (input/output) dout-1 dout-2 dout-3 dout-4 dout-5 SO0n (output) din-1 din-2 din-3 din-4 din-5 SI0n (input) SOTBFLn dout-1 register SOTBLn dout-2 dout-3 dout-4 dout-5 register SIOLn din-5 register SIRBLn din-1 din-2...
Page 418: Figure 13-39: Timing Chart Of Next Transfer Reservation Period (1/2)
Chapter 13 Serial Interface Function (c) Next transfer reservation period In the repeat transfer mode, the next transfer must be prepared with the period shown in Figure 13-39. Figure 13-39: Timing Chart of Next Transfer Reservation Period (1/2) (a) When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 0 SCK0n (input/output) INTCSIn...
Page 419 Chapter 13 Serial Interface Function Figure 13-39: Timing Chart of Next Transfer Reservation Period (2/2) (c) When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 1 SCK0n (input/output) INTCSIn interrupt Reservation period: 6.5 SCK0n cycles (d) When data length: 16 bits, operation mode: CKP bit = 0, DAP bit = 1 SCK0n (input/output)
Page 420: Figure 13-40: Transfer Request Clear And Register Access Contention
Chapter 13 Serial Interface Function (d) Cautions To continue repeat transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is over, the following occurs.
Page 421: Figure 13-41: Interrupt Request And Register Access Contention
Chapter 13 Serial Interface Function - In case of contention between interrupt request and register access Since continuous transfer has stopped once, executed as a new repeat transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 13-41). In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal data is sent.
Page 422: Output Pins
Chapter 13 Serial Interface Function 13.3.5 Output pins SCK0n pin When the CSI0n operation is disabled (CSIE bit of CSIMn register = 0), the SCK0n pin output status is as follows (n = 0 to 2). SCK0n CKS2 CKS1 CKS0 Pin Output Don’t care Don’t care...
Page 423: Dedicated Baud Rate Generators 0, 1 (Brg0, Brg1)
Chapter 13 Serial Interface Function 13.3.6 Dedicated baud rate generators 0, 1 (BRG0, BRG1) Selecting the baud rate generator The CSI00 to CSI02 serial clocks can be selected between dedicated baud rate generator output or internal peripheral clock (f PCLK The serial clock source is specified by bits CKS2 to CKS0 of registers CSIC0 and CSIC1 (refer to 12.3.3 (2) Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1)).
Page 424: Figure 13-43: Prescaler Mode Registers 0, 1 (Prsm0, Prsm1)
Chapter 13 Serial Interface Function Configuration BRGn is configured of an 8-bit timer counter that generates the baud rate signal, a prescaler mode register n (PRSMn) that controls baud rate signal generation, a prescaler compare register n (PRSCMn) that sets the value of the 8-bit timer counter, and a prescaler (n = 0 to 2). (a) Input clock The internal peripheral clock (f ) is input to BRGn.
Page 425: Figure 13-44: Prescaler Compare Registers 0, 1 (Prscm0, Prscm1)
Chapter 13 Serial Interface Function (c) Prescaler compare registers 0, 1 (PRSCM0, PRSCM1) PRSCMn is an 8-bit compare register that sets the value of the 8-bit timer counter. This register can be read/written in 8-bit or 1-bit units (n = 0 to 2). Figure 13-44: Prescaler Compare Registers 0, 1 (PRSCM0, PRSCM1) Initial Address...
Page 426: Table 13-6: Baud Rate Generator Setting Data
Chapter 13 Serial Interface Function (e) Baud rate setting example Table 13-6: Baud Rate Generator Setting Data <1> When f = 16 MHz PCLK BGCS1 BGCS0 PRSCM Register Value Clock (Hz) 4000000 2000000 1000000 500000 250000 100000 50000 25000 10000 5000 <2>...
Page 427: Chapter 14 Fcan Interface Function
Chapter 14 FCAN Interface Function 14.1 Features • Active support of extended format (ISO 11898, former CAN specification version 2.0B active), sup- porting transmission and reception of standard and extended frame format messages Note • 2 or 4 CAN modules •...
Page 428: Outline Of The Fcan System
Chapter 14 FCAN Interface Function 14.2 Outline of the FCAN System 14.2.1 General Note The FCAN (Full-CAN) system of the V850E/CA2 supports 2 or 4 independent CAN modules (CAN Note Note module 1, CAN module 2, CAN module 3 , CAN module 4 ), which provide each an interface to a Controller Area Network (CAN).
Page 429: Can Memory And Register Layout
Chapter 14 FCAN Interface Function 14.2.2 CAN memory and register layout All buffers and registers of the FCAN system are arranged within a memory layout of 4.5 KB. Figure 14-2: Memory Area of the FCAN System Address Offset 113FH Note CAN4 register section (2 bytes/register)
Page 430: Table 14-1: Configuration Of The Can Message Buffer Section
Chapter 14 FCAN Interface Function The sections within the FCAN memory layout contain areas, which are defined as illegal addresses or CANx temporary buffer (x = 1 to 2 for the derivative µPD703128 (A), x = 1 to 4 for the derivatives µPD703129 (A) and µPD703129 (A1)).
Page 431: Table 14-2: Can Message Buffer Registers Layout
2. The address of a message buffer entry is calculated according to the following formula: effective address = PP_BASE + address offset 3. The V850E/CA2 Jupiter device does not contain an event processor. Therefore the mes- sage event bytes are reserved.
Page 432: Table 14-3: Relative Addresses Of Can Interrupt Pending Registers
Chapter 14 FCAN Interface Function CAN Interrupt Pending Registers Section The layout of the interrupt pending register section is shown in Table 14-3. Table 14-3: Relative Addresses of CAN Interrupt Pending Registers Access Type Address Ref. Symbol Name Comment Note Page Offset R/W 1 bit 8 bits...
Page 433: Table 14-4: Relative Addresses Of Can Common Registers
Chapter 14 FCAN Interface Function CAN Common Registers Section The layout of the common register section is shown in Table 14-4. Table 14-4: Relative Addresses of CAN Common Registers Access Type Address Ref. Symbol Name Comment Note Page Offset R/W 1 bit 8 bits bits ×...
Page 434: Table 14-5: Relative Addresses Of Can Module 1 Registers
Chapter 14 FCAN Interface Function CAN Module Registers Section The appropriate register section of each CAN module is shown in Table 14-5 for CAN module 1, in Table 14-6, “Relative Addresses of CAN Module 2 Registers,” on page 435 for CAN module 2, in Table 14-7, “Relative Addresses of CAN Module 3Note1 Registers,”...
Page 435: Table 14-6: Relative Addresses Of Can Module 2 Registers
Chapter 14 FCAN Interface Function Table 14-6: Relative Addresses of CAN Module 2 Registers Access Type Address Ref. Symbol Name Comment Note Page Offset R/W 1 bit 8 bits bits × × 1080H C2MASKL0 CAN2 mask 0 register L lower half-word ×...
Page 436: Table 14-7: Relative Addresses Of Can Module 3
Chapter 14 FCAN Interface Function Note1 Table 14-7: Relative Addresses of CAN Module 3 Registers Access Type Address Ref. Symbol Name Comment Note2 Page Offset R/W 1 bit 8 bits bits × × 10C0H C3MASKL0 CAN3 mask 0 register L lower half-word ×...
Page 437: Table 14-8: Relative Addresses Of Can Module 4 Registers
Chapter 14 FCAN Interface Function Note1 Table 14-8: Relative Addresses of CAN Module 4 Registers Access Type Address Ref. Symbol Name Comment Note2 Page Offset R/W 1 bit 8 bits bits × × 1100H C4MASKL0 CAN4 mask 0 register L lower half-word ×...
Page 438: Clock Structure
Chapter 14 FCAN Interface Function 14.2.3 Clock structure All functional blocks within the FCAN system are supplied by a unique clock (f ) derived from the internal system clock (f PLCK Figure 14-3: Clock Structure of the FCAN System Time System General Time System PCLK...
Page 439: Interrupt Handling
Chapter 14 FCAN Interface Function 14.2.4 Interrupt handling The very high number of interrupt events generated by the FCAN system does not allow to assign an independent interrupt vector of the V850E/CA2 to each event. Therefore, the interrupt request signals are bundled into groups and the grouped interrupt request signal is then assigned to an independent interrupt vector.
Page 440 Chapter 14 FCAN Interface Function The interrupt pending registers of the FCAN system are: - CGINTP: Global interrupt pending register - C1INTP: CAN module 1 interrupt pending register - C2INTP: CAN module 2 interrupt pending register - C3INTP: CAN module 3 interrupt pending register - C4INTP: CAN module 4 interrupt pending register Additionally the entire interrupt pending flags are summarized in one register, the CAN interrupt pend- ing register (CCINTP).
Page 441: Time Stamp
Chapter 14 FCAN Interface Function 14.2.5 Time stamp The FCAN system offers a time stamp capture capability at message reception and transmission. The time stamp capture function is used to realize a synchronized, global clock in a CAN network, also called global time system.
Page 442: Figure 14-6: Time Stamp Capturing At Message Transmission
Chapter 14 FCAN Interface Function For the time stamp capturing at message transmission the SOF signal of the transmit message is used as the event trigger (see Figure 14-6). The captured value from the CGTSC counter is written into particular data bytes of the transmit mes- sage’s data field.
Page 443: Message Handling
Chapter 14 FCAN Interface Function 14.2.6 Message handling In the FCAN system the assignment of message buffers to the CAN modules is not defined by hard- ware. Each message buffer in the message buffer section can be assigned to any CAN module by soft- ware.
Page 444: Table 14-10: Example For Automatic Transmission Priority Detection
Chapter 14 FCAN Interface Function Table 14-10: Example for Automatic Transmission Priority Detection Message Buffer Message Buffer Message Buffer Message Buffer Waiting for Identifier Note1 Note2 Number Link Transmission Address Offset Type 400H · · · · · · 300H 2E0H 2C0H CAN 1...
Page 445: Table 14-11: Example For Transmit Buffer Allocation When More Than 5 Buffers
Chapter 14 FCAN Interface Function Table 14-11: Example for Transmit Buffer Allocation When More Than 5 Buffers Linked to a CAN Module Message Buffer Message Buffer Message Buffer Message Buffer Identifier Address Offset Note 2 Number Link Type Note 1 400H ·...
Page 446: Table 14-12: Storage Priority For Reception Of Data Frames
Chapter 14 FCAN Interface Function Message reception Due to the vast initialisation possibilities for each message buffer in the FCAN system, it is possi- ble that a received message fits in several message buffers assigned to a CAN module. A fixed rule according to the priority classes has been implemented to avoid arbitrary message storage and uncontrolled behaviour.
Page 447: Table 14-14: Inner Storage Priority Within A Priority Class
Chapter 14 FCAN Interface Function Table 14-14: Inner Storage Priority Within a Priority Class Priority First Criteria Priority Second Criteria 1 (high) lowest physical message buffer number 1 (high) DN flag not set 2 (low) next physical message buffer number 1 (high) lowest physical message buffer number 2 (low)
Page 448: Mask Handling
Chapter 14 FCAN Interface Function 14.2.7 Mask handling The FCAN system supports two concepts of message reception, the BasicCAN concept and the Full- CAN concept. In the Full-CAN concept a particular message buffer accepts only one single message, hence there is no further sorting and filtering required by software.
Page 449: Remote Frame Handling
Chapter 14 FCAN Interface Function 14.2.8 Remote frame handling The FCAN macro offers enhanced features for generating remote frames and for the reaction of a CAN module upon remote frames. Generation of a remote frame According to the CAN specification a remote frame has the same format as a data frame except the RTR bit of the control field, which has recessive level, and the data field, which is omitted com- pletely.
Page 450 Chapter 14 FCAN Interface Function Reception of a remote frame The FCAN allows the reception of remote frames in message buffers defined for reception or for transmission. (a) Reception in a receive message buffer If a remote frame is received in a message buffer m (m = 00 to 31) configured for reception, the fol- lowing message buffer information will be updated: M_DLCm message data length code register...
Page 451: Table 14-15: Remote Frame Handling Upon Reception Into A Transmit Message Buffer
Chapter 14 FCAN Interface Function (b) Reception in a transmit message buffer When the FCAN system searches for the corresponding message buffer after reception of a remote frame and finds a message buffer with a matching identifier, which is defined for transmis- sion, the content of the remote frame is not stored but programmable reactions are launched.
Page 452: Control And Data Registers
Chapter 14 FCAN Interface Function 14.3 Control and Data Registers 14.3.1 Bit set/clear function Direct writing of data (bit operations, read-modify write, direct writing of a target value) is not allowed to few specific registers, where bit setting and bit clearing might be performed by CPU and by the FCAN system.
Page 453: Figure 14-7: 16-Bit Data Write Operation For Specific Registers
Chapter 14 FCAN Interface Function Figure 14-7: 16-Bit Data Write Operation for Specific Registers SE_7 SE_6 SE_5 SE_4 SE_3 SE_2 SE_1 SE_0 CL_7 CL_6 CL_5 CL_4 CL_3 CL_2 CL_1 CL_0 Bit Name Function Sets the register bit n. SE_n 0: No change of register bit n 1: Register bit n is set (1) Clears the register bit n.
Page 454: Common Registers
Chapter 14 FCAN Interface Function 14.3.2 Common registers CAN stop register (CSTOP) The CSTOP register controls the clock supply of the FCAN system. This register can be read/written in 8-bit and16-bit units. Figure 14-8: CAN Stop Register (CSTOP) Address Initial Note value Offset...
Page 455: Figure 14-9: Can Main Clock Select Register (Cgsc) (1/2)
Chapter 14 FCAN Interface Function CAN main clock select register (CGCS) The CGCS register controls the internal memory access clock (f ), which is used as main clock for each CAN module, as well as the global time system clock (f ), used for the time stamp func- tion and event generation.
Page 456: Figure 14-10: Configuration Of Fcan System Main Clock
Chapter 14 FCAN Interface Function Figure 14-9: CAN Main Clock Select Register (CGSC) (2/2) Bit Position Bit Name Function Specifies the prescaler for the memory access clock (f ) (ref. to Fig. 9-10). Memory Clock Prescaler MCP3 MCP2 MCP1 MCP0 / (m+1) (m+1) MEM1...
Page 457: Figure 14-12: Can Global Status Register (Cgst) (1/3)
Chapter 14 FCAN Interface Function CAN global status register (CGST) The CGST register indicates and controls the operation modes of the FCAN system. This register can be read in 1-bit, 8-bit and 16-bit units. It can be written in 16-bit units only. For setting and clearing certain bits a special set/clear method applies.
Page 458 Chapter 14 FCAN Interface Function Figure 14-12: CAN Global Status Register (CGST) (2/3) Read (2/2) Bit Position Bit Name Function Indicates the global operating mode. 0: Access to CAN module registers is prohibited, except mask registers and tempo- Note 1 rary buffers.
Page 459 Chapter 14 FCAN Interface Function Figure 14-12: CAN Global Status Register (CGST) (3/3) Write Bit Position Bit Name Function Sets/clears the EFSD bit. ST_EFSD CL_EFSD Status of EFSD Bit ST_EFSD, EFSD bit is cleared (0). 11, 3 CL_EFSD EFSD bit is set (1). Others No change in EFSD bit value.
Page 460: Figure 14-13: Can Global Interrupt Enable Register (Cgie) (1/2)
Chapter 14 FCAN Interface Function CAN global interrupt enable register (CGIE) The CGIE register enables the global interrupts of the FCAN system. This register can be read in 1-bit, 8-bit and16-bit units. It can be written in 16-bit units only. For set- ting and clearing certain bits a special set/clear method applies.
Page 461 Chapter 14 FCAN Interface Function Figure 14-13: CAN Global Interrupt Enable Register (CGIE) (2/2) Write Bit Position Bit Name Function Sets/clears the G_IE7 bit. ST_G_IE7 CL_G_IE7 Status of G_IE7 Bit ST_G_IE7, G_IE7 bit is cleared (0). 15, 7 CL_G_IE7 G_IE7 bit is set (1). Others No change in G_IE7 bit value.
Page 462: Figure 14-14: Can Timer Event Enable Register (Cgten)
Chapter 14 FCAN Interface Function CAN timer event enable register (CGTEN The CGTEN register enables/disables the 4 timer events. This register can read and written in 8-bit and 16-bit units. Figure 14-14: CAN Timer Event Enable Register (CGTEN) Address Initial Note1 value Offset...
Page 463: Figure 14-16: Can Global Time System Counter (Cgtsc)
Chapter 14 FCAN Interface Function CAN global time system counter (CGTSC) The CGTSC register holds the value of the free-running 16-bit CAN global time system counter. (For details refer to chapters 14.2.3 “Clock structure” on page 438 and 14.2.5 “Time stamp” on page 441) Note 1 This register can be read and written...
Page 464: Figure 14-17: Can Message Search Start Register (Cgmss)
Chapter 14 FCAN Interface Function CAN message search start register (CGMSS) The CGMSS register controls the start of a message search. It can be used for a fast message retrieval within the message buffers matching a search criteria (e.g. messages with DN flag set). This register is write-only and must be written in 16-bit units.
Page 465: Figure 14-18: Can Message Search Result Register (Cgmsr)
Chapter 14 FCAN Interface Function CAN message search result register (CGMSR) The CGMSR register returns the result of a message search, started by writing the CGMSS regis- ter. This register is read-only and can be read in 16-bit units. Figure 14-18: CAN Message Search Result Register (CGMSR) Address Initial 15 14 13 12 11 10...
Page 466: Figure 14-19: Can Test Bus Register (Ctbr)
Chapter 14 FCAN Interface Function CAN test bus register (CTBR) For test purposes an internal test bus is available. The CTBR register controls this test bus capa- bility. This register can be read and written in 8-bit and 16-bit units. Figure 14-19: CAN Test Bus Register (CTBR) Address Initial...
Page 467: Can Interrupt Pending Registers
Chapter 14 FCAN Interface Function 14.3.3 CAN interrupt pending registers CAN interrupt pending register (CCINTP) The CCINTP register summarizes all grouped interrupt pending signals. Each of them is assigned to an unambiguous interrupt vector of the V850E/CA2. This register is read-only and can be read in 8-bit and16-bit units. Figure 14-21: CAN Interrupt Pending Registers (CCINTPL, CCINTPH) Address Initial...
Page 468: Figure 14-22: Can Global Interrupt Pending Register (Cgintp) (1/2)
Chapter 14 FCAN Interface Function CAN global interrupt pending register (CGINTP) The CGINTP register indicates the global interrupt pending signals. The interrupt pending flags can be cleared by writing to the register according to the special bit-clear method. (Refer to chap- ter 14.3.1 “Bit set/clear function”...
Page 469 Chapter 14 FCAN Interface Function Figure 14-22: CAN Global Interrupt Pending Register (CGINTP) (2/2) Write Bit Position Bit Name Function Clears the interrupt pending bit GINT7. CL_GINT7 0: No change of GINT7 bit. 1: GINT7 bit is cleared (0). Clears the interrupt pending bit GINT3. CL_GINT3 0: No change of GINT3 bit.
Page 470: Figure 14-23: Can 1 To 4 Interrupt Pending Registers (C1Intp To C4Intp) (1/2)
Chapter 14 FCAN Interface Function CAN 1 to 4 interrupt pending registers (C1INTP to C4INTP) The C1INTP to C4INTP registers indicate the corresponding CAN module interrupt pending sig- nals. The interrupt pending flags can be cleared by writing to the registers according to the special bit-clear method.
Page 471 Chapter 14 FCAN Interface Function Figure 14-23: CAN 1 to 4 Interrupt Pending Registers (C1INTP to C4INTP) (2/2) Read (2/2) Bit Name Bit Position Function Note Indicates a error passive or bus off status on transmission of CAN module x. CxINT2 0: No Interrupt pending 1: Interrupt pending...
Page 472: Can Message Buffer Registers
Chapter 14 FCAN Interface Function 14.3.4 CAN message buffer registers Message identifier registers L00 to L31 and H00 to H31 (M_IDL00 to M_IDL31, M_IDH00 to M_IDH31) The M_IDLm, M_IDHm registers specify the identifier and format of the corresponding message m (m = 00 to 31).
Page 473: Figure 14-25: Message Configuration Registers 00 To 31 (M_Conf00 To M_Conf31) (1/2)
Chapter 14 FCAN Interface Function Message configuration registers 00 to 31 (M_CONF00 to M_CONF31) The M_CONFm registers specify the message type, mask link and CAN module assignment of the corresponding message m (m = 00 to 31). These registers can be read/written 8-bit units. Figure 14-25: Message Configuration Registers 00 to 31 (M_CONF00 to M_CONF31) (1/2) Address Initial value...
Page 474 Chapter 14 FCAN Interface Function Figure 14-25: Message Configuration Registers 00 to 31 (M_CONF00 to M_CONF31) (2/2) Bit Position Bit Name Function Assigns the message buffer to a CAN module. CAN module assignment Message buffer is not assigned to a CAN Note 5 module Message buffer is assigned to CAN module 1.
Page 475: Figure 14-26: Message Status Registers 00 To 31 (M_Stat00 To M_Stat31)
Notes: 1. The register address is calculated according to the following formula: effective address = PP_BASE + address offset 2. V850E/CA2 Jupiter has no CAN bridge implemented. 3. CAN module 3 and CAN module 4 are available in the derivatives µPD703129 (A) and µPD703129 (A1) only.
Page 476: Table 14-16: Can Message Processing By Trq And Rdy Bits
Chapter 14 FCAN Interface Function Processing of a transmit or receive message by TRQ and RDY flags is summarized in 14-16. Table 14-16: CAN Message Processing by TRQ and RDY Bits Message Type Message Processing Message buffer is disabled for any processing by the ×...
Page 477: Figure 14-27: Message Set/Clear Status Registers 00 To 31 (Sc_Stat00 To Sc_Stat31)
Chapter 14 FCAN Interface Function Message set/clear status registers 00 to 31 (SC_STAT0 to SC_STAT31) The SC_STATm registers set/clear the flags of the corresponding M_STATm registers (m = 00 to 31). By means of this register transmission can be requested and reception can be con- firmed.
Page 478: Figure 14-28: Message Data Registers M0 To M7 (M_Datam0 To M_Datam7) (M = 00 To 31) (1/2)
Chapter 14 FCAN Interface Function Message data registers m0 to m7 (M_DATAm0 to M_DATAm7) (m = 00 to 31) The M_DATAm0 to M_DATAm7 registers are used to hold the receive or transmit data of the corre- sponding message m (m = 00 to 31). These registers can be read/written in 8-bit units.
Page 479 Chapter 14 FCAN Interface Function Figure 14-28: Message Data Registers m0 to m7 (M_DATAm0 to M_DATAm7) (m = 00 to 31) (2/2) Bit Position Bit Name Function 7 to 0 D0_7 to Contents of the message data byte 0. (first message data byte) (M_DATAm0) D0_0 7 to 0...
Page 480: Figure 14-29: Message Data Length Code Registers 00 To 31 (M_Dlc00 To M_Dlc31)
Chapter 14 FCAN Interface Function Message data length code registers 00 to 31 (M_DLC0 to M_DLC31) The M_DLCm registers specify the data length code (DLC) of the corresponding message m (m = 00 to 31). The DLC determines how many data bytes have to be transmitted, or received respectively, for the corresponding data frame.
Page 481: Figure 14-30: Message Control Registers 00 To 31 (M_Ctrl00 To M_Ctrl31) (1/2)
Chapter 14 FCAN Interface Function Message control registers 00 to 31 (M_CTRL0 to M_CTRL31) The M_CTRLm registers control the behaviour on reception or transmission of the corresponding message buffer m (m = 00 to 31). These registers can be read/written in 8-bit units. Figure 14-30: Message Control Registers 00 to 31 (M_CTRL00 to M_CTRL31) (1/2) Address Initial...
Page 482 Chapter 14 FCAN Interface Function Figure 14-30: Message Control Registers 00 to 31 (M_CTRL00 to M_CTRL31) (2/2) Bit Position Bit Name Function Enables message buffer m related interrupts. 0: Interrupts related to message buffer m disabled. 1: Interrupts related to message buffer m enabled. Remark: If the message related interrupt is enabled, an interrupt is generated for any of the following conditions: Condition...
Page 483: Figure 14-31: Message Time Stamp Registers 00 To 31 (M_Time00 To M_Time31)
Chapter 14 FCAN Interface Function Message time stamp registers 00 to 31 (M_TIME00 to M_TIME31) The M_TIMEm registers store the captured time stamp value on reception of the corresponding message m (m = 00 to 31). These registers can be read/written in 16-bit units. Figure 14-31: Message Time Stamp Registers 00 to 31 (M_TIME00 to M_TIME31) Address Initial...
Page 484: (M_Evtm0, M_Evtm1, M_Evtm2, M_Evtm3) (M = 00 To 31)
Remark: m = 00 to 31 Note: V850E/CA2 Jupiter has no CAN bridge implemented. Therefore the “Message Event Bytes” have no function. To avoid unexpected settings of the ERQ flag, it is recommended to initialize all “Message Event Bytes” with the value 0x00 at the first initialization and let that initialization unchanged always.
Page 485: Can Module Registers
Chapter 14 FCAN Interface Function 14.3.5 CAN Module Registers Note CAN 1 to 4 mask 0 to 3 registers L, H (CxMASKL0 to CxMASKL3, CxMASKH0 to Note CxMASKH3) (x = 1 to 4 The CxMASKL0 to CxMASKL3, and CxMASKH0 to CxMASKH3 registers specify the four accept- Note ance masks for each CAN module x (x = 1 to 4 (For more details refer to chapter 14.2.7 “Mask handling”...
Page 486: Table 14-17: Address Offsets Of The Can 1 To 4 Mask Registers
Chapter 14 FCAN Interface Function Table 14-17: Address Offsets of the CAN 1 to 4 Mask Registers Note 3 Address Offset Note1,2 Symbol Note 1, 2 Note 1, 2 x = 1 x = 2 x = 3 x = 4 CxMASKL0 1040H 1080H...
Page 487: Figure 14-34: Can 1 To 4 Control Registers (C1Ctrl To C4Ctrl) (1/5)
Chapter 14 FCAN Interface Function CAN 1 to 4 control registers (C1CTRL to C4CTRL) The CxCTRL registers control the operating modes and indicate the operating status of the corresponding CAN module x (x = 1 to 4 for the derivatives µPD703129(A) and µPD703129(A1), x = 1 to 2 for the derivative µPD703128(A)).
Page 488 Chapter 14 FCAN Interface Function Figure 14-34: CAN 1 to 4 Control Registers (C1CTRL to C4CTRL) (2/5) Read (1/2) Bit Position Bit Name Function Indicates the transmission error counter status. TECS1 TECS0 Transmission Error Counter Status Transmission error counter below warning level (< 96) TECS1, 15, 14 TECS0...
Page 489 Chapter 14 FCAN Interface Function Figure 14-34: CAN 1 to 4 Control Registers (C1CTRL to C4CTRL) (3/5) Read (2/2) Bit Position Bit Name Function Specifies the CAN message buffer overwrite mode. 0: A new CAN message overwrites a message buffer with DN flag set (1). 1: A new CAN message is discarded, if it would be stored in a message buffer with DN bit set (1).
Page 490 Chapter 14 FCAN Interface Function Figure 14-34: CAN 1 to 4 Control Registers (C1CTRL to C4CTRL) (4/5) Write (1/2) Bit Position Bit Name Function Sets/clears the TPE bit. ST_TPE CL_TPE Status of TPE bit ST_TPE, TPE bit is cleared (0). 15, 7 CL_TPE TPE bit is set (1).
Page 491 Chapter 14 FCAN Interface Function Figure 14-34: CAN 1 to 4 Control Registers (C1CTRL to C4CTRL) (5/5) Write (2/2) Bit Position Bit Name Function Sets/clears the SLEEP bit. ST_SLEEP CL_SLEEP Status of SLEEP bit ST_SLEEP, SLEEP bit is cleared (0). 9, 1 CL_SLEEP SLEEP bit is set (1).
Page 492: Figure 14-35: Can 1 To 4 Definition Registers (C1Def To C4Def) (1/4)
Chapter 14 FCAN Interface Function CAN 1 to 4 definition registers (C1DEF to C4DEF) The CxDEF registers define normal and diagnostic operation and indicate CAN bus error and states of the corresponding CAN module x (x = 1 to 4 for the derivatives µPD703129(A) and µPD703129(A1), x = 1 to 2 for the derivative µPD703128(A)).
Page 493 Chapter 14 FCAN Interface Function Figure 14-35: CAN 1 to 4 Definition Registers (C1DEF to C4DEF) (2/4) Read (1/2) Bit Position Bit Name Function Specifies the storage of receive message in diagnostic mode. 0: receive only and store valid message in message buffer type 7. 1: receive only and store valid message as in normal operation mode Remarks: 1.
Page 494 Chapter 14 FCAN Interface Function Figure 14-35: CAN 1 to 4 Definition Registers (C1DEF to C4DEF) (3/4) Read (2/2) Bit Position Bit Name Function Defines the priority by message buffer numbers. 0: Transmission priority is given by message identifier. 1: Transmission priority is given by the number of the message buffer. Remark: Normally the message identifier defines the transmission priority.
Page 495 Chapter 14 FCAN Interface Function Figure 14-35: CAN 1 to 4 Definition Registers (C1DEF to C4DEF) (4/4) Write Bit Position Bit Name Function Sets/clears the DGM bit. ST_DGM CL_DGM Status of DGM bit ST_DGM, DGM bit is cleared (0). 15, 7 CL_DGM DGM bit is set (1).
Page 496: Figure 14-36: Can 1 To 4 Information Registers (C1Last To C4Last)
Chapter 14 FCAN Interface Function CAN 1 to 4 information registers (C1LAST to C4LAST) The CxLAST registers return the number of the last received message and last CAN protocol error of the corresponding CAN module x (x = 1 to 4 for the derivatives µPD703129(A) and µPD703129(A1), x = 1 to 2 for the derivative µPD703128(A)).
Page 497: Figure 14-37: Can 1 To 4 Error Counter Registers (C1Erc To C4Erc)
Chapter 14 FCAN Interface Function CAN 1 to 4 error counter registers (C1ERC to C4ERC) The CxERC registers reflect the status of the transmit and the receive error counters of the corresponding CAN module x (x = 1 to 4 for the derivatives µPD703129(A) and µPD703129(A1), x = 1 to 2 for the derivative µPD703128(A)).
Page 498: Figure 14-38: Can 1 To 4 Interrupt Enable Registers (C1Ie To C4Ie) (1/3)
Chapter 14 FCAN Interface Function CAN 1 to 4 interrupt enable registers (C1IE to C4IE) The CxIE registers enable the transmit, receive and error interrupts of the corresponding CAN module x (x = 1 to 4 for the derivatives µPD703129(A) and µPD703129(A1), x = 1 to 2 for the derivative µPD703128(A)).
Page 499 Chapter 14 FCAN Interface Function Figure 14-38: CAN 1 to 4 Interrupt Enable Registers (C1IE to C4IE) (2/3) Read Bit Position Bit Name Function Enables CAN module error interrupt (INT6). E_INT6 0: Interrupt disabled 1: Interrupt enabled Enables CAN bus error interrupt (INT5). E_INT5 0: Interrupt disabled 1: Interrupt enabled...
Page 500 Chapter 14 FCAN Interface Function Figure 14-38: CAN 1 to 4 Interrupt Enable Registers (C1IE to C4IE) (3/3) Write Bit Position Bit Name Function Sets/clears the E_INT6 bit. ST_E_INT6 CL_E_INT6 Status of E_INT6 bit ST_E_INT6 E_INT6 bit is cleared (0). 14, 6 CL_E_INT6 E_INT6 bit is set (1).
Page 501: Figure 14-39: Can 1 To 4 Bus Activity Registers (C1Ba To C4Ba) (1/2)
Chapter 14 FCAN Interface Function CAN 1o 4 bus activity registers (C1BA to C4BA) The CxBA registers indicate the status of the CAN bus activities of the corresponding CAN module x (x = 1 to 4 for the derivatives µPD703129(A) and µPD703129(A1), x = 1 to 2 for the derivative µPD703128(A)).
Page 502 Chapter 14 FCAN Interface Function Figure 14-39: CAN 1 to 4 Bus Activity Registers (C1BA to C4BA) (2/2) Bit Position Bit Name Function Indicates the message buffer, which is either waiting to be transmitted or in transmis- sion progress. TMNO7 to TMNO0 Number of Transmit Message Buffer Current transmit message buffer (waiting for transmission, TMNO7 to 0 to 31...
Page 503: Figure 14-40: Can 1 To 4 Bit Rate Prescaler Registers (C1Brp To C4Brp) (1/2)
Chapter 14 FCAN Interface Function CAN 1 to 4 bit rate prescaler registers (C1BRP to C4BRP) The CxBRP registers specify the bit rate prescaler and CAN bus speed of the corresponding CAN module x (x = 1 to 4 for the derivatives µPD703129(A) and µPD703129(A1), x = 1 to 2 for the derivative µPD703128(A)).
Page 504 Chapter 14 FCAN Interface Function Figure 14-40: CAN 1 to 4 Bit Rate Prescaler Registers (C1BRP to C4BRP) (2/2) Bit Position Bit Name Function Specifies the bit rate prescaler for the CAN protocol layer. TLM = 0: Bit Rate Prescaler BRP5 BRP4 BRP3...
Page 505: Figure 14-41: Can Bus Bit Timing
Chapter 14 FCAN Interface Function CAN 1 to 4 synchronization control registers (C1SYNC to C4SYNC) A bit in a CAN frame is built by a programmable number of time quanta (TQ), as shown in the Figure 14-41 below. Figure 14-41: CAN Bus Bit Timing SYNC_SEG PROP_SEG PHASE_SEG1...
Page 506: Figure 14-42: Can 1 To 4 Synchronization Control Registers (C1Sync To C4Sync) (1/2))
Chapter 14 FCAN Interface Function The CxSYNC registers specify the data bit time (DBT), sampling point position (SPT) and syn- chronisation jump width (SJW) of the corresponding CAN module x (x = 1 to 4 for the derivatives µPD703129(A) and µPD703129(A1), x = 1 to 2 for the derivative µPD703128(A)). These registers can be read/written in 8-bit and 16-bit units.
Page 507 Chapter 14 FCAN Interface Function Figure 14-42: CAN 1 to 4 Synchronization Control Registers (C1SYNC to C4SYNC) (2/2) Bit Position Bit Name Function Specifies the number of TQ per bit. Data Bit Time DBTR4 DBTR3 DBTR2 DBTR1 DBTR0 DBTR = (q + 1) TQ ·...
Page 508: Figure 14-43: Can 1 To 4 Bus Diagnostic Information Registers (C1Dinf To C4Dinf)
Chapter 14 FCAN Interface Function (10) CAN 1 to 4 bus diagnostic information registers (C1DINF to C4DINF) The CxDINF registers reflect the last transmission on CAN bus of the corresponding CAN module x (x = 1 to 4 for the derivatives µPD703129(A) and µPD703129(A1), x = 1 to 2 for the derivative µPD703128(A)).
Page 509: Operating Considerations
Chapter 14 FCAN Interface Function 14.4 Operating Considerations 14.4.1 Rules to be observed for correct baud rate settings Observing the following rules for the baud rate setting assures correct operation of a CAN module and compliance to the CAN protocol specification. Rule for sampling point (SPT) setting: The sample point position needs to be programmed between 3 TQ and 17 TQ, which corresponds to the SPTR4 to SPTR0 bits of the CxSYNC register (x = 1 to 4 for the derivatives µPD703129(A)
Page 510: Example For Baudrate Setting Of Can Module
Chapter 14 FCAN Interface Function 14.4.2 Example for baudrate setting of CAN module To illustrate how to calculate the correct setting of the registers CxBRP and CxSYNC the following example is given to 4: Requirements from CAN bus: - FCAN system global frequency f = 16 MHz - CAN bus baud rate f = (83...
Page 511 Chapter 14 FCAN Interface Function Regarding the maximum sampling point setting and the resulting sampling point, two settings meet all the requirements above. Therefore the correct settings are: TLM=0: BRP5 to BRP0 = 000101B (prescaler BRP = 12 TQ) DBTR4 to DBTR0 = 01111B (15) (data bit time DBT = 16 TQ) SPTR4 to SPTR0 = 01100B...
Page 512: Ensuring Data Consistency
Chapter 14 FCAN Interface Function 14.4.3 Ensuring data consistency If the CPU reads data from the CAN message buffers, the consistency of data read has to be ensured. Therefore two mechanisms are provided: • Sequential data read • Burst mode data read Sequential data read If the data is read by the CPU by sequential accesses to the CAN message buffers, the following sequence has to be observed:...
Page 513 Chapter 14 FCAN Interface Function Burst Mode Data Read For faster access to a complete message the burst read mode is applicable. In burst read mode the complete message is copied from the internal message buffer to a tempo- rary read buffer located outside the CAN memory section. This allows read access without any wait, if the CAN memory is accessed by the CAN modules while the CPU tries to read data.
Page 514: Operating States Of The Can Modules
Chapter 14 FCAN Interface Function 14.4.4 Operating states of the CAN modules The different operating states and the state transitions of the CAN modules are shown in the state transition diagram in Figure 14-45. Figure 14-45: State Transition Diagram for CAN Modules Initialisation Mode INIT = 0 CxCTRL[ ISTAT ] =1...
Page 515: Initialisation Routines
Chapter 14 FCAN Interface Function 14.4.5 Initialisation routines Below the necessary steps for correct start-up of the CAN interface are explained. Caution: It is very important that the software programmer observes the sequence given in the following paragraphs. Otherwise unexpected operation of the CAN interface or any CAN module can occur.
Page 516 Chapter 14 FCAN Interface Function Example for C routine: int CAN_GlobalInit (void) unsigned char i; // if GOM flag is already set if(CGST & 0x01) // disable all CAN modules for(i=0; i <= CAN_MODULES; i++) CAN_ModuleStop(i); // clear GOM flag CGST = 0x0001;...
Page 517: Figure 14-47: Initialisation Sequence For A Can Module
Chapter 14 FCAN Interface Function Initialisation sequence for a CAN Module Each CAN module must be initialised by the sequence according to Figure 14-47. Figure 14-47: Initialisation Sequence for a CAN module INIT CAN MODULE Init the module registers: - CxCTRL (but do not clear the INIT flag) - CxDEF - CxIE...
Page 518 Chapter 14 FCAN Interface Function Example for C routine: int CAN_ModuleInit (unsigned char module_no, unsigned short brp_value, unsigned short sync_value) can_module_type *can_mod_ptr; // define ptr can_mod_ptr = &can_module[module_no]; // load ptr can_mod_ptr->CxCTRL = 0x00FE; // clear CxCTRL // except INIT can_mod_ptr->CxDEF = 0x00FF;...
Page 519: Figure 14-48: Setting Can Module Into Initialisation State
Chapter 14 FCAN Interface Function Setting a CAN Module into initialisation state The following routine is required if a CAN module has to be set from normal operation into initiali- sation mode. Please notice that all CAN modules are automatically set to initialisation mode after reset. There- fore the sequence is only required if the CAN module is already in normal operation.
Page 520 Chapter 14 FCAN Interface Function Example for C routine: int CAN_ModuleStop (unsigned char module_no) can_module_type *can_mod_ptr; // define CAN module ptr can_mod_ptr = &can_module[module_no]; // load CAN module ptr if ((can_mod_ptr->CxCTRL & 0x0001)==0) // if INIT flag not yet set: can_mod_ptr->CxCTRL=0x0100;...
Page 521 Chapter 14 FCAN Interface Function Shutdown of the FCAN system If the clock to the CAN interface should be switched off for power saving, the following sequence has to be executed for correct termination of any CAN bus activity: <1> For each CAN module x (x = 1 to 4 for the derivatives µPD703129(A) and µPD703129(A1), x = 1 to 2 for the derivative µPD703128(A)).
Page 522 [MEMO] Preliminary User’s Manual U15839EE1V0UM00...
Page 523: Chapter 15 A/D Converter
Chapter 15 A/D Converter 15.1 Features • 10-bit resolution on-chip A/D converter • Analog inputs: 12 channels • Standby function: - Current cut between AV - AGND if A/D conversion is stopped - Current cut between AV - AGND if A/D conversion is stopped •...
Page 524: Configuration
Chapter 15 A/D Converter 15.2 Configuration The A/D converter, which employs a successive approximation technique, performs A/D conversion operation using A/D converter mode register ADM, A/D converter register ADS and A/D conversion result registers ADCRL/ADCRH. The A/D converter consists of the following hardware. Table 15-1: A/D Converter Configuration Item Configuration...
Page 525 Chapter 15 A/D Converter A/D conversion result register (ADCR/ADCRL/ADCRH) The ADCR register is an 16-bit register that holds all 10 bits of an A/D conversion result. ADCRL is an 8-bit register that holds the lower 2 bits of an A/D conversion result. ADCRH is an 8-bit register that holds the higher 8 bits of an A/D conversion result.
Page 526: Figure 15-1: Block Diagram Of A/D Converter
Chapter 15 A/D Converter Figure 15-1: Block Diagram of A/D Converter ANI0 ANI1 ANI2 ANI3 Sample & hold circuit ANI4 Comparator ANI5 and D/A ANI6 Converter ANI7 ANI8 ANI9 ANI10 Successive approximation ANI11 register SAR Controller INTAD ADCR ADCRH ADCRL A/D conversion result ADS3 ADS2 ADS1 ADS0 ADCS...
Page 527: Control Registers
Chapter 15 A/D Converter 15.3 Control Registers The following 2 types of registers are used to control A/D converter: • A/D converter mode register (ADM) • Analog input channel setting register (ADS) 15.3.1 Register format of A/D Converter Control Register Table 15-2: Register format of A/D Converter Control Register SFR name Symbol...
Page 528: Figure 15-2: A/D Converter Mode Register (Adm)
Chapter 15 A/D Converter A/D converter mode register (ADM) The ADM register is an 8-bit register that enables A/D conversion and the conversion time. It can be read or written in 1-bit or 8-bit units. However, writing to the ADM register during A/D conversion operation interrupts the conversion operation and the data is lost.
Page 529 Chapter 15 A/D Converter (a) Conversion time setting In order to prevent a drastic change of A/D conversion time even when the oscillation frequency is changed, the conversion speed of an A/D conversion can be adjusted. By the selection bits FR3 to FR0 in the ADM register the number of the conversion clocks can be set in the range of 84 to 216.
Page 530: Figure 15-3: A/D Converter Register (Ads)
Chapter 15 A/D Converter A/D converter register (ADS) The ADS register is an 8-bit register that selects the analog input channel for the A/D conversion. It can be read or written in 1-bit or 8-bit units. Writing to the ADS register during A/D conversion operation interrupts the conversion operation and the data is lost.
Page 531: Figure 15-4: A/D Conversion Result Register (Adcr)
Chapter 15 A/D Converter A/D conversion result register (ADCR) The ADCR registers is the A/D conversion result register that holds the result of the A/D conver- sion. When reading 10 bits of data of an A/D conversion result from the ADCR register, only the higher 10 bits are valid and the lower 6 bits are always read 0.
Page 532: Figure 15-6: A/D Conversion Result Register (Adcrh)
Chapter 15 A/D Converter A/D conversion result register H (ADCRH) The ADCRH register is the A/D conversion result register that holds the upper 8-bit result of the A/D conversion. The ADCRH register is the same as the higher byte of the ADCR register. This register can be read in 1-bit or 8-bit units.
Page 533: Figure 15-7: Port Function Register (Port7/Port8)
Chapter 15 A/D Converter Port function register 7/8 (PORT7/PORT8) The PORT7/PORT8 register holds the digital input values of the A/D input channels ANI0 to ANI11 (P70 to P77, P80 to P83). This register can only be read in 16-bit units. Figure 15-7: Port Function Register (PORT7/PORT8) Initial Address...
Page 534: Figure 15-8: Port Function Register 7 (Port7)
Chapter 15 A/D Converter Port function register 7 (PORT7) The PORT7 register holds the digital input values of the A/D input channels ANI0 to ANI7 (P70 to P77). This register can be read in 1-bit and 8-bit units. Figure 15-8: Port Function Register 7 (PORT7) Address Initial value...
Page 535: Input Voltage And Conversion Results
Chapter 15 A/D Converter 15.3.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI11) and the A/D conversion result (stored in the A/D conversion result registers (ADCR)) is shown by the following expression: ×...
Page 536: Interrupt Request
Chapter 15 A/D Converter Figure 15-9: Relation between Analog Input Voltage and A/D Conversion Result 1023 1022 1021 A/D conversion result (ADCR) 2047 2045 1022 2046 1023 2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 Input voltage/AV 15.4 Interrupt Request The A/D converter generates a dedicated interrupt.
Page 537: A/D Converter Operation
Chapter 15 A/D Converter 15.5 A/D Converter Operation 15.5.1 A/D converter basic operation A/D conversion is performed using the following procedure. Note 1 Note 2 Set the analog input selection using the ADS register. Setting (1) the ADCS bit of the Note 1 register starts the A/D conversion for the selected A/D input channel.
Page 538: Operation Modes
Chapter 15 A/D Converter 15.5.2 Operation modes The operation mode of the A/D converter is the soft-trigger mode. One analog channel is selected from among ANI0 to ANI11 with the analog input channel setting register (ADS). (a) Soft-trigger mode In the soft-trigger mode the A/D converter converts one analog input specified in the ADS register. The conversion result is stored in the ADCR, ADCRL, ADCRH register.
Page 539: Figure 15-11: Adcs Bit Is Cleared (0) During A/D Conversion Operation
Chapter 15 A/D Converter Figure 15-11: ADCS bit is cleared (0) during A/D conversion operation ANI0 (Input) Data 1 Data 2 Data 3 Data 1 Data 2 A/D conversion (ANI0) (ANI0) A/D conversion stops (ADCS bit of ADM register is cleared (0)) ADCR, ADCRL, ADCRH Data 1 Data 2...
Page 540: Figure 15-12: A Write Operation Is Made To The Ads Register During A/D Conversion Operation
Chapter 15 A/D Converter Figure 15-12: A write operation is made to the ADS register during A/D conversion operation Write operation to ADS register (ADS0 bit is set (1)) Data 2 ANI0 (Input) Data 1 ANI1 (Input) Data 5 Data 4 Data 3 Data 1 Data 2...
Page 541: A/D Converter Precautions
Chapter 15 A/D Converter 15.6 A/D Converter Precautions Current consumption in standby mode A/D converter current consumption can be reduced by stopping the A/D conversion operation. A/D conversion operation is stopped by resetting the ADCS bit of the A/D converter mode register ADM to (0).
Page 542: How To Read The A/D Converter Characteristics Table
Chapter 15 A/D Converter 15.7 How to read the A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the ana- log input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 543: Figure 15-15: Quantization Error
Chapter 15 A/D Converter Quantization Error When analog values are converted to digital values, a ±1/2 LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2 LSB is converted to the same digital code, so a quantization error cannot be avoided.
Page 544: Figure 15-17: Full-Scale Error
Chapter 15 A/D Converter Full-scale Error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2 LSB) when the digital output changes from 1...110 to 1...111. Figure 15-17: Full-Scale Error Full-scale error Ideal line Analog input (LSB) Nonlinearity Error...
Page 545: Chapter 16 Port Functions
Chapter 16 Port Functions 16.1 Features • Input/Output ports (5 V): • Input ports (5 V): • Input/Output ports (3.3 V): • Ports alternate as input/output pins of other peripheral functions • Input or output can be specified in bit units Preliminary User’s Manual U15839EE1V0UM00...
Page 546: Port Configuration
Chapter 16 Port Functions 16.2 Port Configuration The V850E/CA2 incorporates a total of 78 input/output ports (12 ports are input only, 15 input/output ports have 3.3 V power). The ports are named ports P1 through P9, and PAH, PCM, PCT and PCS. The configuration is shown below.
Page 547: Table 16-1: Functions Of Each Port
Chapter 16 Port Functions Functions of each port The V850E/CA2 has the ports shown below. Any port can operate in 8- or 1-bit units and can provide a variety of controls. Moreover, besides its function as a port, some have functions as the input/output pins of on-chip peripheral I/O in control mode.
Page 548: Table 16-2: Port Pin Functions
Chapter 16 Port Functions Functions of each port pin on reset and registers that set port or control mode Table 16-2: Port Pin Functions (1/3) Mode-Setting Port Name Pin Name Pin Function after Reset Register P10/CRXD1 P10 (Input mode) P11/CTXD1 P11 (Input mode) P12/CRXD2 P12 (Input mode)
Page 549 Chapter 16 Port Functions Table 16-2: Port Pin Functions (2/3) Mode-Setting Port Name Pin Name Pin Function after Reset Register P60/NMI P60 (Input mode) P61/IINTP0 P61 (Input mode) P62/INTP1 P62 (Input mode) P63/INTP2 P63 (Input mode) Port 6 PMC6 P64/INTP3 P64 (Input mode) P65/SI2 P65 (Input mode)
Page 550 Chapter 16 Port Functions Table 16-2: Port Pin Functions (3/3) Mode-Setting Port Name Pin Name Pin Function after Reset Register PCT0/LWR PCT0 (Input mode) Port CT PCT1/UWR PCT1 (Input mode) PMCCT PCT4/RD RD (Read strobe signal output mode) Port CM PCM0/WAIT WAIT (Wait insertion signal input mode) PMCCM...
Page 551: Figure 16-2: Type A Block Diagram
Chapter 16 Port Functions Port block diagram Figure 16-2: Type A Block Diagram PMC Nn PMC Nn PM Nn PM Nn Peripheral P Nn Function P Nn P Nn Address P Nn Peripheral Function Remark: N = 1 to 6, 9: Port number n = 0 to 7: Port pin for port number 1, 2, 6, 9 n = 0 to 6:...
Page 552: Figure 16-3: Type B Block Diagram
Chapter 16 Port Functions Figure 16-3: Type B Block Diagram PMCAHn PMCAHn PMAHn PMAHn A23 - A16 PAHn PAHn PAHn Address PAHn Remark: n = 0 to 7 Preliminary User’s Manual U15839EE1V0UM00...
Page 553: Figure 16-4: Type C Block Diagram
Chapter 16 Port Functions Figure 16-4: Type C Block Diagram PMCCSn PMCCSn PMCSn PMCSn CS0, CS3, CS4 PCSn PCSn PCSn Address PCSn Remark: n = 0, 3, 4 Preliminary User’s Manual U15839EE1V0UM00...
Page 554: Figure 16-5: Type D Block Diagram
Chapter 16 Port Functions Figure 16-5: Type D Block Diagram PMCCTn PMCCTn PMCTn PMCTn WR0, WR1, RD PCTn PCTn PCTn Address PCTn Remark: n = 0, 1, 4 Preliminary User’s Manual U15839EE1V0UM00...
Page 555: Figure 16-6: Type E Block Diagram
Chapter 16 Port Functions Figure 16-6: Type E Block Diagram PMCCMn PMCCMn PMCMn PMCMn PCMn PCMn PCMn Address PCMn WAIT Preliminary User’s Manual U15839EE1V0UM00...
Page 556: Pin Functions Of Each Port
Chapter 16 Port Functions 16.3 Pin Functions of Each Port 16.3.1 Port 1 Port 1 is a 8-bit input/output port in which input or output can be specified in 1-bit units. Each port bit Note 1 can be independently configured to port input, port output or peripheral function This register can be read or written in 1-bit and 8-bit units.
Page 557: Figure 16-8: Port 1 Mode Register (Pm1)
Chapter 16 Port Functions Setting in input/output mode and control mode Port 1 is set in input/output mode using the port 1 mode register (PM1). In control mode, it is set using the port 1 mode control register (PMC1). (a) Port 1 mode register (PM1) This register can be read or written in 8-bit or 1-bit units.
Page 558: Figure 16-9: Port 1 Mode Control Register (Pmc1)
Chapter 16 Port Functions (b) Port 1 mode control register (PMC1) This register can be read or written in 8-bit or 1-bit units. Figure 16-9: Port 1 Mode Control Register (PMC1) Address At Reset PMC1 PMC17 PMC16 PMC15 PMC14 PMC13 PMC12 PMC11 PMC10 FFFFF440H Bit Position Bit Name Function...
Page 559: Port 2
Chapter 16 Port Functions 16.3.2 Port 2 Port 2 is an 8-bit input/output port in which input or output can be specified in 1-bit units. Each port bit Note 1 can be independently configured to port input, port output or peripheral function This register can be read or written in 1-bit and 8-bit units.
Page 560: Figure 16-11: Port 2 Mode Register (Pm2)
Chapter 16 Port Functions Setting in input/output mode and control mode Port 2 is set in input/output mode using the port 1 mode register (PM2). In control mode, it is set using the port 2 mode control register (PMC2). (a) Port 2 mode register (PM2) This register can be read or written in 8-bit or 1-bit units.
Page 561: Figure 16-12: Port 2 Mode Control Register (Pmc2)
Chapter 16 Port Functions (b) Port 2 mode control register (PMC2) This register can be read or written in 8-bit or 1-bit units. Figure 16-12: Port 2 Mode Control Register (PMC2) Address At Reset PMC2 PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 FFFFF442H Bit Position Bit Name Function...
Page 562: Port 3
Chapter 16 Port Functions 16.3.3 Port 3 Port 3 is a 6-bit input/output port in which input or output can be specified in 1-bit units. Each port bit Note 1 can be independently configured to port input, port output or peripheral function This register can be read or written in 1-bit and 8-bit units.
Page 563: Figure 16-14: Port 3 Mode Register (Pm3)
Chapter 16 Port Functions Setting in input/output mode and control mode Port 3 is set in input/output mode using the port 3 mode register (PM3). In control mode, it is set using the port 3 mode control register (PMC3). (a) Port 3 mode register (PM3) This register can be read or written in 8-bit or 1-bit units.
Page 564: Port 4
Chapter 16 Port Functions 16.3.4 Port 4 Port 4 is a 6-bit input/output port in which input or output can be specified in 1-bit units. Each port bit Note 1 can be independently configured to port input, port output or peripheral function This register can be read or written in 1-bit and 8-bit units.
Page 565: Figure 16-17: Port 4 Mode Register (Pm4)
Chapter 16 Port Functions Setting in input/output mode and control mode Port 4 is set in input/output mode using the port 4 mode register (PM4). In control mode, it is set using the port 4 mode control register (PMC4). (a) Port 4 mode register (PM4) This register can be read or written in 8-bit or 1-bit units.
Page 566: Port 5
Chapter 16 Port Functions 16.3.5 Port 5 Port 5 is a 7-bit input/output port in which input or output can be specified in 1-bit units. Each port bit Note 1 can be independently configured to port input, port output or peripheral function This register can be read or written in 1-bit and 8-bit units.
Page 567: Figure 16-20: Port 5 Mode Register (Pm5)
Chapter 16 Port Functions Setting in input/output mode and control mode Port 5 is set in input/output mode using the port 5 mode register (PM5). In control mode, it is set using the port 5 mode control register (PMC5). (a) Port 5 mode register (PM5) This register can be read or written in 8-bit or 1-bit units.
Page 568: Figure 16-21: Port 5 Mode Control Register (Pmc5)
Chapter 16 Port Functions (b) Port 5 mode control register (PMC5) This register can be read or written in 8-bit or 1-bit units. Figure 16-21: Port 5 Mode Control Register (PMC5) Address At Reset PMC5 PMC56 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 FFFFF448H Bit Position Bit Name Function...
Page 569: Port 6
Chapter 16 Port Functions 16.3.6 Port 6 Port 6 is an 8-bit input/output port in which input or output can be specified in 1-bit units. Each port bit Note 1 can be independently configured to port input, port output or peripheral function This register can be read or written in 1-bit and 8-bit units.
Page 570: Figure 16-23: Port 6 Mode Register (Pm6)
Chapter 16 Port Functions Setting in input/output mode and control mode Port 6 is set in input/output mode using the port 6 mode register (PM6). In control mode, it is set using the port 6 mode control register (PMC6). (a) Port 6 mode register (PM6) This register can be read or written in 8-bit or 1-bit units.
Page 571: Figure 16-24: Port 6 Mode Control Register (Pmc6)
Chapter 16 Port Functions (b) Port 6 mode control register (PMC6) This register can be read or written in 8-bit or 1-bit units. Figure 16-24: Port 6 Mode Control Register (PMC6) Address At Reset PMC6 PMC66 PMC66 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 FFFFF44AH Bit Position Bit Name Function...
Page 572: Port 7
Chapter 16 Port Functions 16.3.7 Port 7 Port 7 is an 8-bit input port which is shared with the ADC input channels ANI0 to ANI7. Port 7 holds the digital input values of the A/D input channels ANI0 to ANI7 (P70 to P77). Port mode and port mode con- trol are not available for port 7.
Page 573: Port 7/8
Chapter 16 Port Functions 16.3.8 Port 7/8 Port 7/8 is a 16-bit input port which is shared with the ADC input channels ANI0 to ANI11. Port 7/8 holds the digital input values of the A/D input channels ANI0 to ANI11 (P70 to P77, P80 to P83). Port mode and port mode control are not available for port 7/8.
Page 574: Port 9
Chapter 16 Port Functions 16.3.9 Port 9 Port 9 is an 8-bit input/output port in which input or output can be specified in 1-bit units. Port mode con- trol is not available for port 9. This register can be read or written in 1-bit and 8-bit units. Figure 16-27: Port 9 (P9) Address At Reset...
Page 575: 10Port Ah
Chapter 16 Port Functions 16.3.10 Port AH Port AH is an 8-bit input/output port in which input or output can be specified in 1-bit units. After reset, the port AH pins operate as an address bus to address external memories respectively peripherals. Note 1 Each port bit can be independently configured to port input, port output or peripheral function This register can be read in 1-bit and 8-bit units.
Page 576: Figure 16-30: Port Ah Mode Register (Pmah)
Chapter 16 Port Functions Setting in input/output mode and control mode Port AH is set in input/output mode using the port AH mode register (PMAH). In control mode, it is set using the port AH mode control register (PMCAH). (a) Port AH mode register (PMAH) This register can be read or written in 8-bit or 1-bit units.
Page 577: 11Port Cs
Chapter 16 Port Functions 16.3.11 Port CS Port CS is a 3-bit input/output port in which input or output can be specified in 1-bit units. After reset, port PCS0 operates as a chip select output pin (CS0). The port pins PCS3 and PCS4 operate as port input after reset.
Page 578: Figure 16-33: Port Cs Mode Register (Pmcs)
Chapter 16 Port Functions Setting in input/output mode and control mode Port CS is set in input/output mode using the port CS mode register (PMCS). In control mode, it is set using the port CS mode control register (PMCS). (a) Port CS mode register (PMCS) This register can be read or written in 8-bit or 1-bit units.
Page 579: 12Port Ct
Chapter 16 Port Functions 16.3.12 Port CT Port CT is a 3-bit input/output port in which input or output can be specified in 1-bit units. After reset, port pin PCT4 operates as a read strobe signal output (RD). The port pins PCT0 and PCT1 operate as port input after reset.
Page 580: Figure 16-36: Port Ct Mode Register (Pmct)
Chapter 16 Port Functions Setting in input/output mode and control mode Port CT is set in input/output mode using the port CT mode register (PMCT). In control mode, it is set using the port CT mode control register (PMCT). (a) Port CT mode register (PMCT) This register can be read or written in 8-bit or 1-bit units.
Page 581: 13Port Cm
Chapter 16 Port Functions 16.3.13 Port CM Port CM is an 1-bit input/output port in which input or output can be specified in 1-bit units. After reset, port pin PCM0 operates as the wait insertion input (WAIT). This port bit can be configured to port input, Note 1 port output or peripheral function This register can be read in 1-bit and 8-bit units.
Page 582: Figure 16-39: Port Cm Mode Register (Pmcm)
Chapter 16 Port Functions Setting in input/output mode and control mode Port CM is set in input/output mode using the port CM mode register (PMCM). In control mode, it is set using the port CM mode control register (PMCM). (a) Port CM mode register (PMCM) This register can be read or written in 8-bit or 1-bit units.
Page 583: Chapter 17 Reset
Chapter 17 RESET 17.1 Reset Overview Jupiter needs a system reset in order to initialize on power-up or re-initialize to escape from power save mode or system malfunction by Watchdog Timer. Regarding to the Mode setting and source of reset, different actions are performed on reset.
Page 584: Table 17-1: Operation Status Of Each Pin During Reset Period
Chapter 17 RESET Table 17-1 shows the operation status of each pin during Reset period. Table 17-1: Operation Status of each pin during Reset period Pin Function RESET D[15:0] Hi-Z A[23-0] Hi-Z CS[4:3, 0] Hi-Z WR[1:0] Hi-Z Hi-Z WAIT RESOUT TIG05 to TIG00, TIG15 to TIG10, N.A.
Page 585: Reset By Reset Pin
Chapter 17 RESET 17.4 Reset by RESET Pin If a low-level signal is input to the RESET pin, a system reset is performed and the hardware is initial- ized. When the RESET pin level changes from low to high, the Reset State is released and the program execution is started.
Page 586: Figure 17-2: Reset At Power-On
Chapter 17 RESET Reset at power-on A low level for the oscillator stabilization time has to be applied to the RESET pin. This is to secure the clock stabilization time that is necessary after the power is turned on and before a reset signal can be acknowledged.
Page 587: Reset By Watchdog Timer
Chapter 17 RESET 17.5 Reset by Watchdog Timer Jupiter’s watchdog timer can be configured to generate a Reset in case watchdog time expires. This signal is expanded by the clock controller. An output from clock controller is input into the Reset circuit. Oscillation stabilization time is not required after this reset.
Page 588: Initialization
Chapter 17 RESET 17.7 Initialization Initialize the contents of each register as needed within a program. Table 17-2 shows the initial values of the CPU, internal RAM, and on-chip peripheral I/O’s after reset. Table 17-2: Initial Values of CPU and Internal RAM After Reset Initial Value On-Chip Hardware Register Name...
Page 589: Appendix A List Of Instruction Sets
Appendix A List of Instruction Sets Figure A-1: How to Read Instruction Set List This column shows instruction groups. Instructions are divided into each instruciton group and described. This column shows instruction mnemonics. This column shows instruction operands (refer to Table B-1 ). This column shows instruction codes (opcode) in binary format.
Page 590: Table A-1: Symbols In Operand Description
Appendix A List of Instruction Sets Table A-1: Symbols in Operand Description Symbol Description reg1 General register (r0 to r31): Used as source register reg2 General register (r0 to r31): Mainly used as destination register Element pointer (r30) bit#3 3-bit data for bit number specification ×-bit immediate data imm×...
Page 591: Table A-3: Symbols Used For Operation Description
Appendix A List of Instruction Sets Table A-3: Symbols Used for Operation Description Symbol Description ← Assignment GR[ ] General register SR[ ] System register zero-extend (n) Zero-extends n to word length. sign-extend (n) Sign-extends n to word length. load-memory (a,b) Reads data of size b from address a.
Page 592: Table A-5: Condition Codes
Appendix A List of Instruction Sets Table A-5: Condition Codes Condition Name Condition Code Conditional Expression Description (cond) (cccc) 0000 OV = 1 Overflow 1000 OV = 0 No overflow Carry 0001 CY = 1 Lower (Less than) No carry NC/NL 1001 CY = 0...
Page 593: Table A-6: Instruction Set List
Appendix A List of Instruction Sets Table A-6: Instruction Set List (1/7) Flag Instruction Mne- Operand Opcode Operation Group monic CY OV adr ← ep + zero-extend (disp7) disp7 [ep], rrrrr0110 GR [reg2] ← sign-extend (Load- SLD.B reg2 ddddddd memory (adr, Byte)) adr ←...
Page 594 Appendix A List of Instruction Sets Table A-6: Instruction Set List (2/7) Flag Instruction Mne- Operand Opcode Operation Group monic CY OV rrrrr1110 adr ← GR [reg1] + sign-extend 11RRRRR reg2, (disp16) ST.H ddddddddd disp16 [reg1] Store-memory (adr, GR [reg2], dddddd0 Halfword) Note 3...
Page 595 Appendix A List of Instruction Sets Table A-6: Instruction Set List (3/7) Flag Instruction Mne- Operand Opcode Operation Group monic CY OV rrrrr110 GR [reg2] ← GR [reg1] + sign- imm16, reg1, 000RRRRR × × × × ADDI reg2 extend (imm16) iiiiiiii iiiiiiii GR [reg2] ←...
Page 596 Appendix A List of Instruction Sets Table A-6: Instruction Set List (4/7) Flag Instruction Mne- Operand Opcode Operation Group monic CY OV rrrrr110 GR [reg2] ← saturated (GR [reg1] SAT- imm16, reg1, 011RRRRR × × × × × SUBI reg2 - sign-extend (imm16)) iiiiiiii Saturated...
Page 597 Appendix A List of Instruction Sets Table A-6: Instruction Set List (5/7) Flag Instruction Mne- Operand Opcode Operation Group monic CY OV rrrrr1111 GR [reg2] ← GR [reg2] logically 111cccc × × × reg1, reg2 shift right by GR [reg1] 000000001 0000000 GR [reg2] ←...
Page 598 Appendix A List of Instruction Sets Table A-6: Instruction Set List (6/7) Flag Instruction Mne- Operand Opcode Operation Group monic CY OV adr ← GR [reg1] + sign-extend (disp16) 01bbb1111 Z flag ← Not (Load-memory-bit bit#3, 10RRRRR × NOT1 disp16 [reg1] (adr, bit#3)) ddddddddd Store-memory-bit (adr, bit#3, Z...
Page 599 Appendix A List of Instruction Sets Table A-6: Instruction Set List (7/7) Flag Instruction Mne- Operand Opcode Operation Group monic CY OV 000001111 PSW.ID ← 1 1100000 (Maskable interrupt disabled) 000000010 1100000 100001111 PSW.ID ← 0 1100000 (Maskable interrupt enabled) 000000010 1100000 Uses 1 clock cycle without doing...
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Page 601: Appendix B Index
Appendix B Index Numerics 2-way-associative instruction memory ..........155 A/D conversion result register .
Page 602 Appendix B Index Cache configuration register (BHC) ..........118 CALLT .
Page 603 Appendix B Index DDAL0 ............... . 173 DDAL3 .
Page 604 Appendix B Index exception table ..............70 Exception trap .
Page 605 Appendix B Index Internal RAM area ..............73 Internal ROM area .
Page 606 Appendix B Index Non-port pins ..............36 NP .
Page 607 Appendix B Index DMA controller (DMAC) ............198 Prescaler compare registers 0, 1 .
Page 608 Appendix B Index SOTBFL0 to SOTBFL2 ............405 SOTBL0 to SOTBL2 .
Page 609 Appendix B Index VSWC ............... . 107 WAIT .
Page 610 Preliminary User’s Manual U15839EE1V0UM00...
Page 611 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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NEC V850E/CA2 JUPITER Preliminary User's Manual

Chapter 1 Introduction

General

Device Features

Application Fields

Ordering Information

Pin Configuration (Top View)

Function Block Diagram

Chapter 2 Pin Functions

List of Pin Functions

Description of Pin Functions

Types of Pin I/O Circuit and Connection of Unused Pins

Chapter 3 CPU Function

Features

CPU Register Set

Operation Modes

Address Space

Memory Map

Specific Registers

Chapter 4 Bus Control Function

Features

Bus Control Pins

Memory Block Function

Programmable Peripheral I/O Registers

Bus Cycle Type Control Function

Bus Access

Cache Configuration

Wait Function

Idle State Insertion Function

Bus Priority Order

Boundary Operation Conditions

Chapter 5 Memory Access Control Function

SRAM, External ROM, External I/O Interface

Page ROM Controller (ROMC)

Chapter 6 Instruction Cache

Features

Configuration

Control Registers

Instruction Cache Operation

Instruction Cache Initialisation

Operating Precautions

Chapter 7 DMA Functions (DMA Controller)

Features

Control Registers

Next Address Setting Function

DMA Bus States

Transfer Mode

Transfer Types

Transfer Object

DMA Channel Priorities

DMA Transfer Start Factors

Forcible Interruption

Forcible Termination

DMA Transfer Completion

Precautions

Chapter 8 Interrupt/Exception Processing Function

Features

Non-Maskable Interrupts

Maskable Interrupts

Noise Elimination Circuit

Software Exception

Exception Trap

Multiple Interrupt Processing Control

Interrupt Response Time

Periods in Which Interrupts Are Not Acknowledged

Chapter 9 Clock Generator

Features

Configuration

Control Registers

Power Saving Functions

Register Description

Quick Links

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Summary of Contents for NEC V850E/CA2 JUPITER