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Appendix B
916
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B.6 Watchdog Timer
Register
all
Access
R/W
(
T
=
SUWL
+
VSWL
Formular
a
B.7 Asynchronous Serial Interface (UARTA)
Register
all
Access
R/W
(
T
=
SUWL
+
VSWL
Formular
a
B.8 Clocked Serial Interface (CSIB)
Register
all
Access
R/W
(
T
SUWL
VSWL
=
+
Formular
a
2
B.9 I
C Bus
Register
IICSn
Access
R
(
T
=
SUWL
+
3 VSWL
Formular
a
Register
all other
Access
R/W
(
T
=
SUWL
+
VSWL
Formular
a
Preliminary User's Manual U17566EE1V2UM00
1
)
⋅
----------------- -
+
3
f
VBCLK
1
)
⋅
----------------- -
+
3
f
VBCLK
1
)
⋅
3
----------------- -
+
f
VBCLK
1
⋅
)
⋅
----------------- -
+
7
f
VBCLK
1
)
⋅
----------------- -
+
3
f
VBCLK
Registers Access Times
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